Sanyo AVM2780G Schematic

SANYO FISHER SERVICE CORPORATION

TRAINING MANUAL

REFERENCE No. TI780010

INTRODUCTION TO THE VB7C CHASSIS (AVM-2780G)

AS FGH

– i –

FOREWORD

This technical publication familiarizes service technicians with the C-003 CPU circuits, the new BUS Controlled Signal Processor, the new MTS Processor, the new PIP Signal Processor, the new Comb Filter and the new Switching Power Supply circuits employed in type VB7C color television chassis. The C-003 CPU is used on all models using the VB7C chassis, which includes the AVM-2550S, AVM-2580G, AVM-2759S (Chassis No. G5G-2759S2), AVM2760S, AVM-2780G, AVM-3259G (Chassis No. G5R-3259G2/3/4), AVM3260G, AVM-3259S (Chassis No. G5R-3259S1), AVM-3280G, AVM-3650G, AVM-3680G, PC-25S00, PC-27S90 (Chassis No. G5G-27S901/2), PC-32S90 (Chassis No. G5R-32S901/2) and PC-36S00. The descriptions given in this manual for the circuit operations use model AVM-2780G for the schematic nomenclature. Circuit operations for all VB7C chassis will be the same, however, schematic nomenclature may vary with the model.

Note: This publication should be used only as a training aid. Refer to the

specific service data for information about parts, CPU programming, safety and alignment procedures.

Safety Information:

All product safety requirements and testing must be completed prior to returning the television to the consumer. Do not defeat safety features or fail to perform safety checks. Failure to comply with these safety procedures may result in damage or personal injury.

Integrated circuits and many other semiconductors are electrostatically sensitive. Special handling techniques are required when handling these components.

Many electrical and mechanical parts have special safety related characteristics, some of which are often not evident from visual inspection, nor can the protection they give necessarily be obtained by replacing the parts with components rated for higher voltage, wattage, etc. Such parts are often identified in the service literature. A common means of identification is

shading or a ★ on the schematic and/or parts list. Always be on the alert for

any special product safety notices, special parts identification etc. Use of a substitute part that does not have the same safety characteristics can create shock, fire, and/or other hazards. Use the part recommended in the service literature.

– 1 –

TABLE OF CONTENTS

INTRODUCTION TO THE C-003 CPU • • • • • • • • • • • • • • 2 CPU PROGRAMMING • • • • • • • • • • • • • • • • • • • • • • • • 4

KEY SCAN CIRCUIT • • • • • • • • • • • • • • • • • • • • • • • • • 6

REMOTE CONTROL INPUT • • • • • • • • • • • • • • • • • • • • 8

PLL DATA OUT CIRCUIT • • • • • • • • • • • • • • • • • • • • • • 10

AFT CIRCUIT • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 12

SIGNAL PROCESSOR BUS CONTROL CIRCUIT • • • • • • 14

MTS PROCESSOR BUS CONTROL CIRCUITS • • • • • • • 16 SOUND CONTROL CIRCUIT • • • • • • • • • • • • • • • • • • • • 18

DIGITAL CONTROL CIRCUITS • • • • • • • • • • • • • • • • • • • 20

POWER ON/OFF and PROTECTION CIRCUITS • • • • • • • 22 TV/AV SWITCHING CIRCUITS • • • • • • • • • • • • • • • • • • • 24

REFERENCE OSCILLATOR • • • • • • • • • • • • • • • • • • • • 26

CRT DISPLAY CIRCUIT • • • • • • • • • • • • • • • • • • • • • • • 27

MEMORY CONTROL CIRCUIT • • • • • • • • • • • • • • • • • • • 28

MOMENTARY MUTE CIRCUIT • • • • • • • • • • • • • • • • • • • 30

AFT DEFEAT CIRCUIT • • • • • • • • • • • • • • • • • • • • • • • • 32

CPU RESET OPERATION • • • • • • • • • • • • • • • • • • • • • • 34

AUTOMATIC BRIGHT LEVEL ADJUSTMENT SYSTEM • • 36

AUTOMATIC RF AGC ADJUSTMENT SYSTEM • • • • • • • 40

CLOSED-CAPTIONING DESCRIPTION • • • • • • • • • • • • • 44

THE CLOSED-CAPTION DECODER SECTION • • • • • • • 46

CAPTION DATA SLICER • • • • • • • • • • • • • • • • • • • • • • • 48

F/S TUNING SYSTEM DESCRIPTION • • • • • • • • • • • • • • 52 PLL OPERATION • • • • • • • • • • • • • • • • • • • • • • • • • • • • 54 PIP CONTROL CIRCUITS • • • • • • • • • • • • • • • • • • • • • • 56 PIP CIRCUITS • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 58 MTS CIRCUIT • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 60

COLOR ENHANCER CONTROL CIRCUIT • • • • • • • • • • • 62

COMB FILTER • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 63 SWITCHING POWER SUPPLY • • • • • • • • • • • • • • • • • • 64

CPU TROUBLESHOOTING HINTS • • • • • • • • • • • • • • • • 70

– 2 –

INTRODUCTION TO THE C-003 CPU

The C-003 CPU tuning system is capable of electronically tuning 181 different channels and is similar to conventional synthesized tuning systems described in earlier training manuals. The major difference between the C-003 and previous C-983 CPU systems is the additional circuits for the new BUS Controlled PIP Signal Processor and the new BUS Controlled MTS Processor.

The C-003 is a multi-purpose CPU and uses the On-screen Service Adjustment Menu to program the options available for each model.

The block diagram of the C-003 frequency synthesizer (F/S) tuning system and the BUS control circuits is shown in the diagram below. An outline of the operation of each block is given below.

A. CPU

The CPU is the nucleus of the system, controlling each block according to the signals input from the keyboard or remote control transmitter. The basic function which the CPU controls are as follows:

1. Blanking and multi-color CRT signals for the on-screen displays

2. Time of Day clock and Sleep Timer function

3. Auto Program, Channel Memory function

4. Auto Shut-Off function (Turns TV OFF if no video signals are received for 15 minutes)

5. TV/AV input switching function

6. Phase Locked Loop function (PLL) (programmable divider and phase detector)

7. Power supply protection function

8. Digital control functions for picture and audio

9. Trilingual (English/Spanish/French) On-Screen menu system

10. AFT search function

11. Caption Data Slicer

12. V-Guide control function

13. Color Enhancer control function

14. On-screen Service Adjustment Menu system

15. Automatic RF AGC adjustment system

16. Automatic Bright Level adjustment system

17. Signal Processor BUS control function

18. MTS Processor control function

19. Front Surround control function

20. PIP control function

21. EEPROM control

B. Key Matrix

1. Produces DC voltages for the keyboard input.

C. BUS Control Output Circuit

1. Outputs the BUS data from the CPU to each control register within the UHF/VHF tuner, the new Signal Processor, the new PIP Signal Processor, and the new MTS Processor.

D. EEPROM (Nonvolatile Memory)

1. Stores channel memory, antenna mode, customer settings of digital control, caption mode, and language mode.

2. Stores the BUS data used for factory/service adjustment.

E. RF AGC A/D Input Circuit

1. Detects and resistive divides the RF AGC voltage supplied from the new Signal Processor to match with the A/D input of the CPU.

F. Beam Current Detector

1. Detects and converts the CRT beam current from the flyback transformer to DC voltages for the A/D input of the CPU.

G. Remote Control Input

1. Amplifies and couples the remote control data to the CPU.

– 3 –

C-003 Tuning System Block Diagram

RC

PRE-AMP

COMPOSITE VIDEO

TUNER

PLL

PRE-SCALER

BAND SW

KEY

BOARD

EEPROM

CAPTION

DATA SLICER

CPU

(C-003)

OSD

DISPLAY

RF AGC A/D INPUT

BEAM CURRENT DETECTOR

DIGICON SOUND AV MTS PIP AFT

BUS CONTROLLED SIGNAL PROCESSOR

– 4 –

CPU PROGRAMMING

The On-screen Service Adjustment Menu system employed in the VB7C chassis replaces the resistors used to change the voltage on the option pins of the previous CPU. In order to program the CPU for the different options available for the VB7C chassis, the On-screen Service Adjustment Menu is used to change the option data in IC802, the EEPROM.

The Service Adjustment Menu display shown below and the following table show the different options available and the necessary data. The option data shown are for Mode AVM-2780G and include these options: with Clock, with Surround, with Software for PIP Rating Information Processing, with Color Enhancer, with Initial Channel, with PIP, with 2 AV Inputs, and with Bass & Treble controls.

Memory Control Circuits

IC801

CPU

R808

ALWAYS 

L801

IC802

EEPROM

C801

IIC

SCL

IIC

SDA

33

31

R807

6

5

SCL

SDA

– 5 –

PROGRAM CODES

The microprocessor used in the VB7C chassis is a multi-purpose type and is used in several different models. To ensure proper operation and the correct features for your particular model, the Program Codes must be correct.

Note: To enter the service adjustment menu, connect the AC power cord

while pressing the MENU key. The service adjustment can be made with the remote control. To exit the service adjustment mode, press the MENU key again. Refer to the specific Service Manual for your model for complete adjustment procedure.

* . . . .When the Initial Channel option is used, the Initial Channel (the TV can

be set automatically to tune to a specific channel each time it is turned on.) and XDS (Extended Data Service) features are available.

BIT FUNCTION

DATA

0 NOT USED

–– ––

1 NOT USED

–– ––

2 NOT USED

–– ––

00: NONE

3, 4 CLOCK 01: YES (AC 60 Hz)

10: YES (INT OSC) 11: INHIBITED (=NONE)

5 NOT USED

–– ––

6 SURROUND NONE YES 7 NOT USED –– ––

BIT FUNCTION

DATA

0 PIP RATING INFO.

–– ––

1 COLOR ENHANCER NONE YES

2 INITIAL CHANNEL NONE YES * 3 NOT USED –– ––

4 PIP NONE YES

5 AV1 / AV1, AV2 AV1 AV1, AV2

6 TONE / BASS, TREBLE BASS, TRE. TONE

7 NOT USED

–– ––

NO. DATA XXX OPT XXX XXXXXXXX

DECIMAL DATA (ZERO SUPPRESSED)

NO. 29, 30

TITLE OPT, OP2

BINARY DATA (8 bit)

Option Data 1

Option Data 2

– 6 –

Key Scan

The Key Scan circuit uses an analog circuit to generate and send voltage to the CPU when a key is pressed. The CPU uses this voltage to determine which key was pressed. This resistive circuit eliminates the need for encoder/decoder devices, simplifying design and adding to the reliability of the receiver.

The CPU performs a key scan approximately every 20ms to check for a pressed key. When the key data change is the same for two consecutive reads, it is determined that a key has been pressed and the corresponding command executed.

The table below shows the voltages input to CPU pin 9 when a given key is pressed.

Key Input

The function of the keys on keyboard and those of the remote control transmitter are the same.

The following keys, when activated, perform a series step action. The time of each series step action is also shown below.

A . CH Up/Down 500 ms/step. B . Vol Up/Down 140ms/step. It takes about 9 seconds to change from

minimum to maximum volume.

Preceding and succeeding mutes are performed when turning power Off/On, changing channels, switching Antenna mode, searching channels, changing MTS or TV/AV mode, exchanging programs between the main screen and PIP window, or switching Surround sound mode.

Channel and Mode Change Mutes

Key Scan Voltages

KEY INPUT VOLTAGE FUNCTION SW1901 4.26 ~ 5.00 POWER SW1902 3.63 ~ 4.26 VOL + SW1903 3.01 ~ 3.63 VOL SW1904 2.38 ~ 3.01

CH ▲

SW1905 1.60 ~ 2.38

CH ▼

SW1906 1.13 ~ 1.60 MENU

OFF 0.00 ~ 1.13

–––

KEY SCAN CIRCUIT

PRESSING KEY

MODE OUTPUT

MODE CHANGE

PRECEDING MUTE

MUTE SIGNAL MUTE OFFMUTE ON

SUCCEEDING MUTE

– 7 –

IC801

Key Scan Circuit

CPU

ALWAYS

R1910

R1907R1906R1905R1904R1903R1902

R1901

L1901

SW1901 (POWER)

SW1902 (VOL + )

SW1903 (VOL – )

SW1904

(CH ▲ )

SW1905

(CH ▼ )

SW1906 (MENU)

C1902

D1901 (7.5V)

– 8 –

REMOTE CONTROL INPUT

The data received from the remote control is first amplified to 5 V digital pulses by the pre-amplifier module A1901 and then input to the CPU on pin

10. See Remote Transfer Code figure below. The remote data is a transfer code consisting of a leader code, an 8-bit custom code, and an 8-bit data code. A signal transfer code is 32 bits which allows the custom and data codes to be sent twice, once in the normal mode and then inverted. This provides a type of redundancy check to prevent misoperation.

Custom and Data codes differentiate between the “1” and “9” values by the pulse duration. See “1” and “0” Pulse Duration diagram below.

The custom code is a unique code assigned to each manufacturer. Its purpose is to help prevent operation of the TV by remote controls for other components such as VCRs, CD players etc. The code assigned to our company is 38H. See Custom Code figure below. The data code is the command, or channel number.



Remote Input Circuit

IC801

CPU

L1901

R1909

ALWAYS

A1901

RC PRE-AMP

D1901 (7.5V)

C1902

– 9 –

LEADER CODE CUSTOM CODE CUSTOM CODE DATA CODE DATA CODE

C0C1C2C3C4C5C6C7

Remote Transfer Code

0.56msms

1.125ms 2.25ms 1.125ms 2.25ms

" 0 " " 1 " " 0 " " 1 "

"1" and "0" Pulse Duration

D0D1D2D3D4D5D6D7

27ms9ms 4.5ms 27ms

0

000

LEADER CODE DATA CODE 

111

00

111

00

1

Custom Code

– 10 –

PLL DATA OUT CIRCUIT

The VB7C chassis uses a new BUS-Controlled UHF/VHF Tuner with a builtin Phase Locked Loop, Prescaler and Band Switch. Including these circuits in the tuner reduced RF radiation and simplified shielding requirements and printed wiring board layout. The primary difference between this chassis and the previous chassis (C-983) is the exclusive PLL control lines (PLL Enable, PLL Data, PLL Clock) are unified to the common BUS control lines (BUS SDA, BUS SCL), and the BUS control program is incorporated in the CPU (C-003).

Channel selection requires only two inputs from the CPU. These are the Data signal input from pin 32, and the Clock signal input from pin 34. The Data signal controls the band switching, the channel selection and the AFT. The channel selection and the AFT function are controlled by changing the divide ratio for the PLL. The tuning data format is composed of 5 byte data. See Tuning Data Format figure below.

PLL Data Circuit

IC801

CPU

BUS SDA

L881

R881

A101

TUNER

R856

DATA

BUS

SCL

L882

R882

R857

CLOCK

– 11 –

BYTE (MSB) DATA BYTE (LSB) COMMAND

Address byte (ADB) 1 1 0 0 0 MA1 MA0 0 A Divider byte 1 (DB1) 0 M9 M8 M7 M6 M5 M4 M3 A Divider byte 2 (DB2) M2 M1 M0 S4 S3 S2 S1 S0 A Control byte (CB) 1 CP T1 CD X 1 1 0 A Band switch byte (BB) X X X X BU FMT BVH BVL A

PLL Data Format

A • • • • • • • • • • • • • • acknowledge MA1 and MA2 • • • • • address selection bits M8~M0, S4~S0 • • • • programmable divider bits CP • • • • • • • • • • • • • charge pump current (tuning speed) switch control T1 • • • • • • • • • • • • • test mode selection CD • • • • • • • • • • • • • charge pump defeat switch control X • • • • • • • • • • • • • • don’t care bit BU • • • • • • • • • • • • • UHF band switch control FMT • • • • • • • • • • • • FM trap (92.5MHz) switch control at channel 6 BVH • • • • • • • • • • • • VH band switch control BVL • • • • • • • • • • • • VL band switch control

BAND BU FMT BVH BVL

VL (WITHOUT CH 06 ONLY) L L L H VL (CH 06 ONLY) L H L H VH L LHL UHF H L L L

Band Switch Control Data

– 12 –

AFT CIRCUIT

The Automatic Fine Tuning (AFT) program incorporated in the CPU functions to fine tune the tuner local oscillator to the center of the actual broadcast frequency. This is necessary because the transmitted TV signal may not be exactly on its assigned channel frequency. In addition, certain CATV channels are purposely slightly offset to reduce interference from broadcast frequencies. The operating range of the AFT is ± 2.25 MHz from FCC center.

Specifically, the AFT searches the frequency band ± 2.25 MHz from FCC center in 62.5 KHz steps by changing the PLL division ratios while evaluating the binary signals from IC101, the Signal Processor.

The station center is determined to have been found when the Time Base signal at pin 26 is High and the AFT S-Curve signal at pin 29 is between 3.3 VDC and 1.67 VDC. However, the slope (right down) is also checked to distinguish the station center from a pseudo-tuning point.

The Time Base signal is the AND signal of the horizontal sync signal from the flyback transformer and the horizontal sync signal from the video (Y) signal.

The AFT S-Curve signal is an indication of the video IF carrier frequency

45.75 MHz.

The Time Base and AFT S-Curve signals are checked after each stepping action. If station center cannot be confirmed after a complete search of the upper and lower limits of the AFT range, the frequency is returned to FCC center and the AFT action ceased.

The AFT only operates when first entering the channel. When entering the channel C05 or C06, the operating range of the AFT is ± 2.25MHz from FCC center +125 KHz (2 steps).

AFT Circuit

IC801

CPU

R167

AFT

S-CURVE

R168

C161

7.6 V

IC101 SIGNAL PROCESSOR

R161

R162

TIME

BASE

R371

R377

Q372

R376

R372

Q371

C258

R373

C371

– 13 –

CPU

RANGE OF 0 ~ 5 V

AFT

S-CURVE

TIME BASE

SIGNAL

3.3 V

1.67 V

TUNING

POINT

AFT S-Curve Signal

Time Base Signal

Station Center

– 14 –

SIGNAL PROCESSOR BUS CONTROL CIRCUIT

The VB7C chassis is equipped with a new single-chip BUS-Controlled NTSC Signal Processor IC to replace much of the mechanically adjusted factory/service controls and all of the low pass filters in the PWM control lines for the customer setting digital controls used in the conventional chassis.

The primary difference between this chassis and the conventional chassis is the addition of the BUS Interface circuit and the movement of the control registers into the Signal Processor IC, and the BUS control program incorporated in the CPU (C-003).

The advantages of this chassis include reduced control lines and associated circuitry, and improved productivity and increased accuracy of the factory adjustments during production. This is due to the computerized and digitized control circuit which allows remote operation.

Control of the Signal Processor IC is through CPU pins 32 and 34.

Pin 34 is the BUS SCL (Serial Data) signal. The BUS SDA is a bi-directional signal and is used to transfer data into and out of the control registers within IC101. Data is processed through an 8 bit read or write for each sub address in an IC address “1011010” with in IC101.

See Bit Map below for IC Address, Sub Address or Data for details.

IC801

CPU

BUS

SCL

BUS SDA

L814

L813

SIGNAL PROCESSOR

R804

CLK

R803

DATA

IC101

BUS Interface

STA

ICW SUB DA STO

STA = START Condition ICW = IC Address* + Write SUB = Sub. Address* DA = Data* STO = STOP Condition

Control Registers

Signal Processor BUS Control Circuit

See Bit Map below for IC Address, Sub Address or Data for details.

BUS Data Format In Write Mode

– 15 –

T Enable 1 Disable the Test SW & enable Video Mute SW Video Mute 1 Disable video outputs Sync Kill 1 Force free-run mode ABL Defeat SW 1 Disable ABL function AFC Gain 2 Select horizontal first loop gain Horizontal Phase 5 Align sync to flyback phase IF AGC SW 1 Disable IF and RF AGC AFT Defeat 1 Disable AFT output RF AGC Delay 6 Align RF AGC threshold Video SW 1 Select Video Signal (INT/EXT) PLL Tuning 7 Align IF VCO frequency BNI Enable 1 Enable black noise inverter Audio Mute 1 Disable audio outputs APC Det Adjust 6 Align AFT crossover V Count Down Mode 1 Selected vertical countdown mode Vertical Test Enable 3 Selected vertical DAC test modes Vertical DC 6 Align Vertical DC bias Vertical Kill 1 Disable vertical output Color Kill 1 Enable Color Killer Vertical Size 6 Align vertical amplitude Red Bias 8 Align Red OUT DC level Green Bias 8 Align Green OUT DC level Blue Bias 8 Align Blue OUT DC level Blanking Defeat 1 Disable RGB output blanking Red Drive 7 Align Red OUT AC level Drive Test 1 Enable drive DAC test mode Blue Drive 7 Align Blue OUT AC level Color Difference Mode Enable 1 Enable Color difference mode Brightness Control 7 Customer brightness control Contrast Test 1 Enable Contrast DAC test mode Contrast Control 7 Customer contrast control Trap & Delay SW 1 Select luma filter mode AutoFlesh Enable 1 Enable autoflesh function Black Stretch Defeat 1 Disable black stretch Sharpness Control 5 Customer sharpness control Tint Test 1 Enable tint DAC test mode Tint Control 7 Customer tint control Color Test Enable 1 Enable color DAC test mode Color Control 7 Customer color control White Peak Limiter Enable 1 Disable White Peak Limiter G Drive Reduction 4 Select Green OUT AC level V Size Compensation 3 Selected Gain of V Size Compensation Video Level 3 Align IF video level FM Level 5 Align WBA output level Audio SW 1 Select Audio Signal (INT/EXT) Volume Control 7 Customer volume control

Control Register Descriptions

IC Address: BAh (10111010)

Sub Address (MSB) DATA (LSB)

• • • • • •

D0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

$00 ✻✻✻✻T_Enable ✻ Vid_Mute

SSnncc KKiilll

(tr0) 1 0 0 $01 ABL DEF AFC Gain H_Phase (tr1) 1 1 1 0 1 1 1 1 $02 IF AGC SW

AAFFTTDDEEF

F RF_AGC_Delay (Note-1)

(tr2) 0 0 1 1 0 0 1 0 $03 VIDEO SW PLL TUNING (tr3) 0 1 0 0 0 0 0 0 $04 N/I SW Audio_Mute APC DET ADJUST (tr4) 1 0 0 1 1 1 1 1 $05 VCD MODE V_Test Ver_DC (tr5) 0 0 1 0 0 0 0 0 $06

VVeerr KKiillllCCooll KKiilll

l Ver_size

(tr6) 0 0 1 0 0 0 0 0 $07 R_Bias (Note-2) (tr7) 0 0 0 0 0 0 0 0 $08 G_Bias (Note-2) (tr8) 0 0 0 0 0 0 0 0 $09 B_Bias (Note-2) (tr9) 0 0 0 0 0 0 0 0 $0A BLK_DEF R-Drive

(tr10) 0 0 1 1 0 1 1 1

$0B Drv_Test B_Drive

(tr11) 0 0 1 1 0 1 1 1

$0C C_Diff

BBrriigghht

(tr12) 0 1 0 0 0 0 0 0

$0D Cot_Test

CCoonnttrraasst

(tr13) 0 1 1 1 1 1 1 1

$0E Trap&D_SW A Flesh Black ST

SShhaarrppnneesss

(tr14) 0 1 0 1 0 0 0 0

$0F Tin_Test

TTiinnt

(tr15) 0 1 0 0 0 0 0 0

$10 Col_Test

CCoolloor

(tr16) 0 1 0 0 0 0 0 0

$11 W Peak G Drive Reduction V-Comp.

(tr17) 1 1 0 0 0 0 0 0

$12 VIDEO LEVEL FM LEVEL

(tr18) 1 0 0 0 1 1 1 1

$13 AUDIO SW Volume

(tr19) 1 1 1 1 1 1 1 1

• The shaded data shows fixed data.

• The outlined data can be changed except during the Service Menu mode.

• The data except above can be set with the Service Menu.

• Note-1: shows the data that can be set with the Service Menu or the Automatic Adjustment Menu.

• Note-2: shows the data that can be set with the R/G/B Bias Adjustments in the Service Menu.

Bit Map

– 16 –

MTS PROCESSOR BUS CONTROL CIRCUIT

The VB7C chassis is equipped with a new single-chip BUS-Controlled MTS Processor IC to replace much of the mechanically adjusted factory/service controls and all of the low pass filters in the PWM control lines for the customer setting digital controls used in the conventional chassis. In addition, the Bass, Treble and Volume control circuits have been also integrated into a single-chip IC.

The primary difference between this chassis and the conventional chassis is the addition of the BUS Interface circuit and movement of the control registers into the MTS Processor IC, and the BUS control program incorporated in the CPU (C-003).

Control of the MTS Processor IC is through CPU pins 32 and 34.

Pin 34 is the BUS SCL (Serial Clock) signal. The BUS SCL input is used to clock all data into and out of IC101.

Pin 32 is the BUS SDA (Serial Data) signal. The BUS SDA is a bi-directional signal and is used to transfer data into and out of the control registers within IC3401. Data is processed through an 8-bit read or write for each sub address in an IC address “10000100” (Read Address) or “10000101” (Write Address) within IC3401.

See Bit Map below for IC Address, Sub Address or Data for details.

IC801

CPU

IC3401

MTS PROCESSOR

STA

ICA SUB DA STO

BUS SDA

L881

R3401

SDA

BUS

R881

Interface

BUS

SCL

L882

R882

R3402

SCL

Control Registers

MTS Processor BUS Control Circuit

STA = START Condition ICA = IC Address* + Read or Write SUB = Sub. Address* (needed only in Write mode) DA = Data* STO = STOP Condition

See Bit Map below for IC Address, Sub Address or Data for details.

BUS Data Format in Write Mode

– 17 –

IC Write Address: 84h (10000100)

Sub Address (MSB) DATA (LSB)

• • • • • •

D0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

00h ✻✻TEST-DA TEST 1 ATT (Note-1)

01h ✻✻ SPECTRAL (Note-2)

02h ✻✻ WIDEBAND (Note-2)

03h ✻ M2 EXT1 EXT2 NRSW FOMO SAPC M1

(Note-5) (Note-3) (Note-3) (Note-4) (Note-4) 0 (Note-5)

04h ✻ PSW ✻ SURR ATT SW ✻ FEXT1 FEXT2

0 (Note-6) 0 0 0

05h ✻✻ BASS (Note-7)

06h ✻✻ TREBLE (Note-7)

07h ✻✻ VOL-L (Note-8)

08h ✻✻ VOL-R (Note-8)

• Note-1: ATT for the Input Level Adjustment.

• Note-2: SPECTRAL for the High Separation and WIDEBAND for Low Separation

Adjustments.

• Note-3: EXT1 and EXT2 for the AV Selection.

• Note-4: NRSW for Stereo/SAP Selection and FOMO for Forced Mono Selection.

Mode EXT1 EXT2

TV 0 0 AV1 1 0 AV2 1 1

Mode selected Receiving Signal NRSW FOMO Output Signal

MONO Mono 0 ✻ MONO

Stereo 0 1 MONO

SAP + Mono 0 1 MONO

SAP + Stereo 0 1 MONO

STEREO Mono 0 1 MONO

Stereo 0 0 STEREO

SAP + Mono 0 1 MONO

SAP + Stereo 0 0 STEREO

SAP Mono 0 1 MONO

Stereo 0 0 STEREO

SAP + Mono 1 0 SAP

SAP + Stereo 1 0 SAP

• Note-5: M1 for TVOUT Mute and M2 for LSOUT Mute functions. LSOUT Mute is accomplished by M2 and Volume Mute.

Mode Data

MUTE ON 0

MUTE OFF 1

• Note-6: SURR for Surround On/Off Selection.

Mode Data

SURROUND OFF 0

SURROUND ON 1

• Note-7: BASS for Bass Control and TREBLE for Treble Control.

Control Level Data

MAXIMUM 3Fh (111111b )

CENTER 1Fh (011111b)

MINIMUM 00h (000000b)

• Note-8: VOL-L for L-Channel Volume Control and VOL-R for R-Channel Volume Control.

IC Read Address: 85h (10000101)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POWER STEREO SAP NOISE –– –– –– ––

✻: Don’t care bit.

POWER=1 : Reset STEREO=1 : Stereo is present. STEREO=0 : Stereo is absent. SAP=1, NOISE=0 : SAP is present. SAP=1, NOISE=1 : SAP is absent. SAP=0 : SAP is absent.

– 18 –

SOUND CONTROL CIRCUIT

The sound level is controlled by the BUS control signal form the CPU, the BUS SDA (Serial Data) signal from pin 32, and the BUS SCL (Serial Clock) signal from pin 34. The BUS control signals from the CPU are coupled to the BUS Interface circuit within IC3401, the MTS Processor. The BUS Interface circuit transfers a 6-bit volume data into both of the Volume Control Registers VOL-L and VOL-R. A 6-bit volume control data from each of the Volume Control Registers is converted to a 0-63 steps analog signal (DC voltages) in the Volume D/A converter for input to the Volume Control Circuit. Now the audio signal is output from pins 3 and 4 of IC3401.

The volume control data “000000” and the audio mute control data “0” are input to the Volume Control Registers VOL-L and VOL-R, and the Audio Mute Control Register M2 (Sub Address 03h, Bit 6), respectively to set the output sound level to step 0/63 during Mute ON. (See page 30 for the Audio Mute Control Register M2.) In addition, the CPU outputs the Mute (High) signal from pin 38 to prevent buzz or static in the speakers when turning On/Off or during Standby mode. The Mute (High) is coupled to the base of Q001, switching Q001 On, grounding pin 5 of the Audio Amplifier IC001.

BUS Data Format in Write Mode - Volume Level at 16/63 step

STA ICW SUB DA STO

D7 D0D1D2D3

D0D1D2D3

00000011

STA: START Condition ICW: IC Address + Write SUB: Sub. Address DA : Data STO: STOP Condition

DA7

1000001

✻✻010000

DA6

DA5

DA4

DA1

DA2DA3

(LSB)(LSB) (LSB) (MSB)(MSB)(MSB)

DA0

IC WRITE ADDRESS

D7 D0D1D2D3

SUB. ADDRESS

00000011 00100000

IC WRITE ADDRESS

SUB. ADDRESS

Don't care bits

DA7D0D1D2D3

DA6

DA5

DA4

VOL-L

(LSB)(LSB) (LSB) (MSB)(MSB)(MSB)

DA0DA1DA2DA3

✻✻010000

Don't care bits

VOL-R

– 19 –

Sound Control Circuit

IC801

CPU

BUS SDA

BUS

SCL

MUTE

L881

L882

R881

R882

R3401

R3402

AV1-R

AV1-L

AV2-R



BUS

Interface

to BUS Line

FEXT1

IC3401

MTS PROCESSOR

VOL-R

VOL-L

TREBLE

BASS

SURR

EXT1/EXT2/M1

VOLUME

CONTROL

BASS/TREBLE

CONTROL

SURROUND

BLOCK

AUDIO SW

IC001

AUDIO AMP.

C002

C001

C007

R011

R012

Q001 MOMENTARY MUTE

C3437

C3435

C010

SP901

C011

SPEAKER (R)

SP902

SPEAKER (L)

K1011 FIXED AUDIO OUT (R)

K1021 FIXED AUDIO OUT (L)

AV2-L

SIF In

FEXT2

MTS DECODER

BLOCK

– 20 –

DIGITAL CONTROL CIRCUITS

Digital electronic controls replace the mechanical customer controls. This provides a more precise setting of the controls as well as allowing the convenience of remote operation. The BUS data output from the CPU for each Control Register are essentially the same as those previously described for the Sound Control Circuit.

The BUS Interface circuit (see diagram below) is necessary to transfer each control data in the BUS data from the CPU into a corresponding Control Register in the Signal Processor IC101, and the MTS Processor IC3401.

After accessing the on-screen main menu system with the MENU key and

selecting the Picture/Sound Manual adjustment menu with the CH ▲ / ▼ and

VOL – / + keys, digital control is carried out by pressing the MENU key for

seven separate controls. the CH ▲ / ▼ key is used to select the control to be changed. Each time a CH ▲ / ▼ key is pressed, the mode will advance

to the next control. The sequence is: Color, Tint, Contrast, Brightness, Sharpness, Bass and Treble. the active control will be displayed on the screen and then can be adjusted with the VOL – / + keys.

It takes 140 ms per step to change the control level with the VOL – / + keys. There are 64 step control level changes in each control mode with the output characteristics of each control mode independent of the others. When a VOL – / + key is pressed it takes approximately 5 seconds to change from center to minimum or center to maximum. The BUS data changes for the controls are the same as those shown for the volume control.

When the FACTORY PRESET mode is selected with the RESET key, the Picture/Sound controls will return to the factory settings. During FACTORY PRESET mode the settings are as follows: COLOR 32/64*

, TINT 32/64*1,

CONTRAST 64/64*

, BRIGHTNESS 32/64*3, SHARPNESS 32/64*4, BASS 32/64, TREBLE 32/64. Furthermore, the FACTORY PRESET mode clears all the other customized settings.

When the FACTORY PRESET mode is selected, the customized settings of the digital controls will be reset. If desired, customized settings can be made again using the on-screen menu.

A 7-bit control data up to 127 steps are output for each control register. One and one half of the customer control steps (1.5x64 =96 steps) are assigned for customer setting and the remainder (31 steps) are provided for service adjustment.

A 7-bit control data up to 127 steps are output for this control register. One and one half of the customer control steps (1.5x64 =96 steps) are assigned for customer setting and the remainder (31 steps) are always output.

A 7-bit control data up to 127 steps are output for this control register. 64 steps are assigned for customer setting and the remainder (63 steps) are provided for service adjustment.

A 5-bit control data up to 31 steps are output for this control register. One fourth of the customer control steps (1/4x64=16 steps) are assigned for customer setting and the remainder (15 steps) are provided for service adjustment.

– 21 –

Output Range of BUS Data

IC801

FUNCTION BTS

OUTPUT

RANGE OF

BUS DATA

RANGE OF STEPS

CUSTOMER

CONTROL

SERVICE

ADJUSTMENT

Color 7 0 ~ 127

(0~64)/127x1.5 =0/127~96/127

(0~31)/127

=0/127~31/127

Tint 7 0 ~ 127

(0~64)/127x1.5 =0/127~96/127

(0~31)/127

=0/127~31/127

Contrast 7 31 ~ 127

(0~64)/127x1.5+31/127

=31/127~127/127

(0)/127 =0/127

Brightness 7 0 ~ 127

(0~64)/127

=0/127~64/127

(0~63)/127

=0/127~63/127

Sharpness 5 0 ~ 31

(0~64)/31x1/4

=0/31~16/31

(0~15)/31

=0/31~15/31

Volume 6 0 ~ 63 0/63~63/63 ––

Bass 6 10 ~ 54 10/63~54/63 ––

Treble 6 10 ~ 54 10/63~54/63

––

CPU

BUS SDA

BUS

SCL

L813

L814

R803

R804

SIGNAL PROCESSOR

IC101

Color

BUS

Interface

to BUS Line

Tint

Contrast

Brightness

Sharpness

Write

7 bit

Write

7 bit

Write

7 bit

Write

7 bit

Write

5 bit

CRT

Video/Chroma

Processing Circuit

R881

L882

R882

L881

R3401

R3402

Digital Controls

IC3401

MTS PROCESSOR

Volume

-L/R

BUS

Interface

to BUS Line

Treble

Bass

Write

6/6 bit

Write

6 bit

Write

6 bit

MTS Signal

Processing Circuit

R-OUT

L-OUT

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