.
COLOUR TELEVISION
TRAINING MANUAL
FILE NO.
Chassis Series AAI-A
CIRCUIT DESCRIPTION
BLOCK DIAGRAM OF Ics
TROUBLE SHOOTING
REFERENCE NO. TI 520004
Table of Contents
Part 1 Chassis Description
lJ
1. Circuit Function Description
2. CPU ..........................................................................................................................................6.l9
2-1 A-D Key Identification .........................................................................................................................8
2-2 Option Switches ............................................................................................................................9.lO
2-3 System Switch Output
2-4 Chroma lD ........................................................................................................................................l3
2-5 ldent ..................................................................................................................................................l3
2-6 Sync. lD ............................................................................................................................................l4
2-7 IPC
2-8 Band Switching .................................................................................................................................l5
2-9 Tuning & Digital AFT
2-1o Power & Protect ..............................................................................................................................l8
2-11 Horiz./Vert. Pulse ............................................................................................................................l9
3. System Switches
3-1 Sound Carrier Trap ...........................................................................................................................22
3-2 SIF Filtering ......................................................................................................................................23
3-3 Chroma Crystal Selection .................................................................................................................24
External/Internal Source Selection ...........................................................................................25
4.
5. lF/Video/Chroma/Def.
6. Audio Circuit
6-1 Monaural Circuit ...............................................................................................................................27
6-2 A2 Stereo Circuit ..............................................................................................................................28
6-3 A2 Stereo & Nicam Circuit ................................................................................................................29
Double/Full-wave Rectifier Circuit
7.
BUS .., ...... ............... ....... ....... ......... ...... .................. . ....... . . ..... . . . . ..... . ...... ... ....... . . ........ ....... ........ ....
...................................................................................................................
................................................................................................................
.........................................................................................................................
....................................................................................................
.................................................................................................................l 1-12
...................................................................................................................l6.l7
............................................................................................
Part 2 Block Diagram of ICS
3-5
14
20-24
26
27-29
30
AA1-A
1. TDA8361 /8362 .dF/Video/Chroma/Def Iect ion>
2. TDA4661/V2 <1 H Delay>
3. TDA8395 cSECAM Decoder>
4. LA7833 <Vertical Output>
5. TDA2546A/V4 <SIF Decoder> ...................................................................................................35
6, MC44131 PB <Audio Multiple Decoder> ...................................................................................35
7, TDA8204
8. TDA8205 <NICAM QSPK Demodulator>
9, TDA7263M <Audio Output>
10. STR81 145A <Double/Full-wave Rectifier Switch>
cNICAM Decoder> .....................................................................................................36
............................................................................................................
..m..mm.............................................................................................34
..m......................................................................................................34
......................................................................................................
........................................................................
..................................................................................37
................................................................
32
33
38
38
Part 3 Trouble Shooting Chart
1. Dead .......................................................................................................................................4l-44
2. No picture/No sound .................................................................................................................45
3. No picture-sound OK .................................................................................................................46
4. No sound-picture OK (Stereo model) .................................................................................47.48
5. No sound-picture OK (Monaural model) ..................................................................................49
6. No colour
Incorrect colour phase
7.
8. No vertical deflection
....................................................................................................................................
..............................................................................................................
................................................................................................................
-2-
50
51
52
Part 1 Chassis Description
1. Circuit Function Description
The following figure shows a block diagram of the AA1-A chassis.
1
%
REAR
FRONT
-3-
AA1-A
1. POWER SUPPLY
The power supply circuit of the AAl -A chassis
comprises a primary rectifier smoothing circuit,
an oscillation circuit, a control circuit and an
output rectifier circuit.
The AC input voltage is rectified at the double or
full-wave rectifier smoothing circuit, and an
unstable DC voltage is generated at both
terminals of the smoothing capacitor C307. The
double or full-wave rectifier circuit is build by
switching the triac on or off in IC501
<STR81145A>. This voltage is supplied to the
oscillation circuit, which is composed of a
blocking oscillator circuit that switches the
switching transistor Q313 ON and OFF.
A square-wave oscillation is generated in the
input winding according to operation of the
control circuit. A square-wave with amplitude
dependent on the turns ratio of the input and
output windings is obtained in the output winding.
This is rectified in the output rectifier circuit, and
the desired DC voltage is produced.
2. IF& DEFLECTION (TDA8361/8362)
The IF output signal from the tuner passes
through the SAW filter, and it is inputted into pins
45 and 46 of IC101.
Within the IC, the IF signal passes through the IF
amplifier, video detection and video amplifier
circuits, and is outputted from pin 7 as a
composite video signal.
In the monaural model, this composite video
signal passes through the 5.5 MHz(B/G)/
6. 0MHz(l)/6.5MHz( D/K)/ 4.5 MHz(M) sound
bandpass filtering circuit, and it is inputted into
pin5 of IC101. In the stereo model, the SIF signal
is supplied from pin 14 of IC181 <TDA2546A> to
pin 5 of IC101 through the sound bandpass
circuit for modulation of the main carrier. In the
IC101, this sound IF signal passes through the
SIF amplifier, FM detector, external audio switch
and audio output circuit, and it is then outputted
from pin 50 as audio drive signal (Monaural
model). In the stereo model, the main audio
signal is fed from pinl to the stereo controller IC
(MC44131PB).
The video signals applied to pins 13 or 15 are
separated into vertical- and horizontal-sync.
signals respectively by the sync. separator in the
Ic.
The horizontal oscillator requires no external
components and is fully integrated. This
AA1-A
oscillator is always running when the start-pin 36 –
is supplied with 8V, and the horizontal drive
signal is outputted from pin 37. VR401 is used
for horizontal centring adjustment.
The separated vertical sync. signal from the
sync. separation circuit passes through the
vertical-separation circuit, and is applied to
trigger divider circuit.
The horizontal oscillation pulse and vertical sync.
pulse are monitored by the trigger divider circuit
to select either the 50Hz or 60Hz system, and
automatically adjust the vertical amplitude.
The output signal from the trigger divider triggers
the vertical oscillator circuit whose external
timing components consist of R402, C401 to pin
42, and the vertical ramp signal is outputted from
pin 43. VR451 is for controlling the amount of AC
feedback applied to pin 41 for adjustment of the _
vertical amplitude.
3. VIDEO CHROMA (TDA8361/8362)
The composite video signal output from the pin 7
of IC101, passes through Q122, and the sound
traps X124, X125, X126, X127 to reject the
sound carrier components, is then supplied to pin
13 through the equalizing circuit consisting of
Q135, Q132 and Q134. The external video signal
from SCART or other AV terminals is supplied to
pin 15.
The video signal input to pin 13 or pin 15 is
separated into luminance (Y) signal and chroma
signal in IC101. These pins are also common to
the H/V-sync. separation circuit input already
described.
The peaking of Y signal is adjusted by DC _
voltage on pin 14.(’’SHARPNESS” control)
The chroma signal is divided into R-Y and B-Y
chroma signals, which are demodulated and
output from pin 30 (R-Y) and pin 31 (B-Y). These
chroma signals pass through the 1H delay line
circuit (IC270), and are re-inputted at pin 29 (R-
Y) and pin 28 (B-Y). These R-Y/B-Y signals pass
through the RGB matrix circuit and the RGB
selector circuit of IC101. The internal RGB
signals are generated in the RGB matrix circuit
and the RGB selector, consisting of linear
amplifiers, clamps and selects either the internal
RGB signals or the external RGB signals input
from pin 22 (R) , pin 23 (G), pin 24 (B). Selection
is controlled by the voltage at the RGB switch
control (pin 21) and mixed RGB modes are
possible since the RGB switching is fast.
-4-
—
The RGB switch also functions as a fast blanking
pin by blanking the RGB output stages; here
internal and external RGB signals are overruled.
The RGB signals for the on-screen display are
superimposed onto the selected RGB signals at
the base of transistors Q21O, Q211 and Q212
respectively.
The saturation of colour gain is controlled by the
DC voltage of pin 26. (“COLOUR” control)
The contrast control voltage present at pin 25,
controls the RGB signal gain, and the brightness
control voltage present at pin 17, controls DC
level of RGB signals.
The RGB signals are finally buffered before
being presented to the RGB output pins [pin 20
(R), pin 19 (G), pin 18 (B)].
4. AUDIO OUTPUT
4-1 (AN5265)-Monaural model
The audio signal output from pin 50 of IC101 is
inputted to pin 2 of ICI 71 and passes through
the pre-amplifier circuit and the drive circuit into
the audio amplifier. The audio amplifier is the
SEPP (Single-Ended Push Pull) type and the
output from pin 8 drives the speaker directly.
4-2 (TDA7263M)-Stereo model
The audio signals output from pins 17 and 18 of
IC1l 01 (MC44131 PB) are inputted to pins 1(Left)
and 5( Right) of IC1102 and passes through the
pre-amplifier circuit and drive circuit, after which
it is input to the audio amplifier. The audio
amplifier is the SEPP (single-ended, push-pull)
OTL type and the outputs from pins 8( Right) and
10(Left) drive the speakers directly.
5. VERTICAL OUTPUT
An LA7833 is used for the vertical output circuit
in this chassis. The vertical ramp signal from pin
43 of IC101 is inputted to pin 4 of IC451. This
ramp drives IC451, and vertical scanning is
performed. In the first half of scanning a
deflecting current is outputted from pin 2 and
passes through the following path:
VCC(B4)+D451+ pin 3+ pin 2+ DY+ C461+
vR451/R459.
An electric charge is then stored in C461. [n the
last half of scanning the current path is:
C461+ DY+ pin 2+ pin 1+ VR451/R459 +
C461
In this way, an increasing
current flows directly to
sawtooth waveform
the DY to perform
electron beam deflection. During the first half of
the blanking period the vertical ramp signal
suddenly turns OFF. Since there is no longer any
current flowing into the DY, the magnetic field
collapses causing an induced current to flow as
follows:
pin 2+ pin 1+ VR451/R459+ C461 + DY
DY+
Once the magnetic field in DY has dissipated,
the current path becomes:
Vcc+ pin 6+ pin 7+ C452+ pin 3+ pin 2 +
DY+ C461 + VR451/R459
and when the prescribed current value is
reached, the vertical drive ramp signal turns ON.
This completes one cycle.
6. HORIZONTAL OUTPUT
The horizontal oscillation signal is outputted from
pin 37 of IC101 and used to switch the drive
transistor Q431. This switching signal is current
amplified by the drive transformer T431 and
drives the output transistor Q432. When Q432
turns ON, an increasing current flows directly to
the DY through
C441/C442+ L441/R441 + DY+ Q432-C +
Q432-E
and the deflection occurs during the last half of
the scanning period. When Q432 turns OFF, the
magnetic field stored in the DY up to that point
causes a resonant current to flow into the
capacitors C420 and C423 and charges them.
The current stored in C420 and C423 then flows
back to the DY causing an opposite magnetic
field to be stored in the DY. This field then
collapses increasing a current which switches
the dumper diode in Q432 ON. The resonance
state is completed, and an increasing current
then flows again directly to the DY through the
dumper diode.
By this means, the deflection in the first half of
the scanning period is performed. When Q432
turns ON at the end of the first half of the
scanning period, the deflection during the last
half is begun, thus completing one cycle.
In the PCC circuit consisting of Q461 and Q462,
the parabola signal supplied from the vertical
circuit is added at the horizontal output stage and
pincushion compensation is performed by
varying the DC bias. Further, the ABL voltage is
fedback to the base of Q462 to compensate for
width variations due to variations in the beam
current.
-5-
AAI-A
2. CPU
The following figure shows a block diagram of the CPU peripheral circuit.
il
!
I
I
0 a
cu.
—.—. —
—-—. — .
AA1-A
!7-—. —-— -’
-6-
a
c
u
The following table shows pin descriptions of the CPU.
Pin Description
1 Horizontal sync. signal input
2 Vertical sync. signal input
3 Volume control output
4
Colour control output
Brightness control output
5
6 Contrast control output
7 Sharpness control output
8 Tnt control output
9 AV1/AV2 switch output (AV1 :Low)
10 TV/AV switch output (TV: Hi)
11 AFT S-signal input
12
13
ipc bus SCL line
12C bus S(JA line
14 Tuning voltage output
15 Ident signal input
16
RC signal input
17 --18
19
20
Chroma ID input
Ignore signal input
Sync. ID input
21 ---
22
23
24
25
26
GND
GND
Oscillator input for CPU
Oscillator output for CPU
GND
Pin Description
27 +5V
28
29
30
31
power supply
Oscillator 2 for OSD
Oscillator 1 for OSD
Reset input
Detection power failure (Error: Lo)
32 AV2 option switch (Hi: AV2)
33 Option switch (System selection)
34 Key scan input (DV)
35
Key scan input (DC)
36 Option input & SIF output D/K
37 Option input & SIF output I
38 Option input & SIF output B/G
39 Option input & SIF output M/M
40
41
42
System switch output SECAM
System switch output 3.58
System switch output 4.43
43 Band switch output I (Low: VH)
44
Band switch output II (Low: VL)
45 AC switch off detection input
46
47
Option switch (RC status)
Sound mute output (Mute on:Low)
48 Power on/off output (P-On: Hi)
49
Blanking signal output for OSD
50 OSD blue signal output
51 OSD green signal output
52 OSD red signal output
-7-
AAI-A
2-1 A-D Key Identification Circuit
The key identification circuit used in this chassis uses a switched resistive ladder network in
A-D conversion circuit to generate and send a voltage to the CPU when a key is pressed.
an
The
CPU uses this voltage to determine which key was pressed. This resistive circuit
eliminates the need for encoder/decoder devices, simplifying design and adding to the
reliability of the TV.
The table shows the voltages input to CPU pin 34 and 35,
K1 5“ SW
Q
when a given key is pressed.
47kzizEa47k
CPU
4
35
34 +
Inputvoltageto pin 35
I Kev I ● flangeofvolta9es I Function
OFF
K1
K2
K3
K4
K5
K6
K7
KR
lessthan0.6V
0.6V- 1.2V
1.2V- 1.8V
1.8V- 2.4V
2.4V- 3.OV
3.OV- 3.7V
3.7V- 4.3V
4.3V- 4.9V
morethan4.9V
15’ K3
6.8k K’
4.7’ K5
2.7’ K6
1.8’ ~7
1.5’ K8
NoKey
Pos.+
Pos.vol.+(TuSlow)
Vol.
-(Tu Slow)
Function
PreseUMemory
ColourSystem
SIFSvstem
&o
— —
—
— —
— —
— —
[:1
Kll
~2
K13
K14
K15
15’
6.8’
4.7’
2.7’
1.8’
1.5’
150
$
10k
i
Inputvoltageto pin34
Key
OFF
Sw
K9
K1O
Kll
K12
K13
K14
K15
-,
● RangeofVoltages
lessthan 0.6V
0.6V- 1.2V
1.2V- 1.8V
1.8V-J2.4V
2.4V--3.OV
3.OV- 3.7V
3.7V- 4.3V
4.3V- 4.9V
morethan4.9V
● When the supply voltage is 5.oV.
Function
60prog. positions
30prog. positions
TVIAV
n/a
nla
nla
nla
nla
nla
AA1-A
AA1-A
-8-
2-2 Option switches
This chassis uses the option function switches to determine several different specifications of
TV set.
the
The CPU determines the specification of TV by detecting the voltage level on the following
pins.
Colour system: pin 33, SIF system: pins 36 to 39, No. of AV modes: pin 32, Remote control
status: pin 46, No. of programme position: pin 34.
Pins 36 to 39 also operate as SIF system selection outputs.
Colour system
system
SIF
CPU
--13
Pinll
Ov
0.5V
1.2V
1.8V
2.5V
3.OV
3.8V
4.3V
4.9V
r
Rx
open
82k
33k
18k
10k
6.8k
3.3k
1.5k
150
CPU
5
Rx
33
10k
Specification
Test
PALsystem
VMT system(PAL-TV, PAL/M-NTST/NTSC-AV)
East Europe system(PAL/N-NTSC/S ECAM-TV,AV)
Multi system(PAUM-NTSC/NTSC/SECAM-TV,AV)
China system(PAUM-NTSC/NTSC-TV,AV)
nla
nla
nla
10kx4
Swl
on
on
off
off
on
off
r
SW2 SW3 SW4
on
off on off
off
off on off
off off off
off off off
IL
39
38
37
36
on on
on
on
-9-
Specification
No SIF system
SIF system e (B/G, D/K)
SIF system d (M/M, B/G)
SIF system c (M/M, B/G, D/K)
SIF system b (B/G, 1,D/K)
SIF system a (B/G, D/K, 1,M/M)
AAl-A
AV modes
CPU
32 -
Remote control status
CPU
46
10k
“9
5
10k
9
P-
SW5 Specification
2 AV system (AV1/AV2)
11 AV system (AV)
Specification
w/o remote control function
w/ remote control function
I
off
on
SW6
off
on
I
No. of programme position
CPU
34
H
5
7’
d
Sw
Rx=
47k+15k+6.8k+4.7k
+2.7k+l .8k+l .5k+150
10k
Sw
off
on
Specification
60 programme positions
30 programme positions
AAl A
AA1-A
-10-
2-3 System switch output
The outputs from pins 40 to 42 of the CPU select the colour system and the outputs from
36 to 39 the
SIF system. These outputs drive the colour and SIF system switching circuits.
pins
The operation of each switching circuit is shown in the tables below.
.
Colour system sw
v
SECAM
I
I NTSC
SIF system switching output
1. Multi system(SIF system a option)
SIF system
thing output
Output pins
42 41 40
HHL
HLL
HLH
LHL
Output pins
Display
Auto
PAL/NTsc4.43
SECAM
NTSC
Display
39 38 37 36
Auto
B/G-5.5MHz
I-6.OMHZ
D/K-6.5MHz
M/M-4.5MHz
●
LHLL
LLHL
LLLH
HLLL
HHH
● It depends on receiving TV system
S1
S2
S3
S4
S5
2.3 system (SIF system b option)
~
B/G-5.5MHz
I-6.OMHZ
D/K-6.5MHz
3. China, PX (SIF system c option)
SIF system
input H
I
input L
input L
Output pins
39 38 37 36
●
Auto
H
BIH-5.5MHZ LH
DIK-6.5MHz LL
MIM-4.5MHZ HL
Display
S1
LL
HL
LH
input H
input L
input H
input L
● Itdepends on receiving TV system
S2
S3
S4
Display
S1
S2
S3
S4
-11-
AA1-A
4. Indonesia (SIF system d option)
SIF system Output pins Display
39 38 37 36
●
Auto
BIG-5.5MHZ
MIM-4.5MHZ
5. East Europe (SIF system e option)
H input input S1
LH
HL
input input S2
input input
S3
SIF system
Auto
B/G-5.5MHz
D/K-6.5MHz
6. No SIF system
SIF system Output pins
----
Output pins
I
39 38 37 36
I
input H
input H
input L
39 38 37 36
input input input input
input H
input L
input H
Display
I
I
Display
S1
S2
S3
AAlA
—
AA1-A
-12-
2-4 Chroma ID
The identification of a colour or black/white broadcast is achieved by sensing the voltage
level input at pin 18. This voltage is supplied from pin 26
Q771. When there is a black/white broadcast the voltage on pin 26 goes low.
Normally, pin 26 operates
as colour control function, and the control voltage is from pin 4 of
of ICI 01 through the inverter circuit,
the CPU.
To
identify the colour system during a black/white broadcast, the CPU judges that the system
is NTSC when the following conditions are detected at same time.
(1) The colour system is “AUTO” or “NTSC” system.
(2) The field frequency is 60 Hz.
(3) TV/AV mode is “TV” mode.
CPU
CHROMA ID
btE!zzd
COLOUR
18
R773
10k
4
....................................
4
i Colour control
~ D/A circuit ~
....................................
R774
220k
1 “T
R775
12k
U
ICI 01
Chroma/Def.
26
COLOUR
2-5 Ident (Identification)
The identification of the receiving signal status is done by the CPU sensing the voltage level
at the input pin 15, as shown below. The ident signal is presented at pin 4 of IC101 and fed to
pin 15 of the CPU through the converter circuit consisting of Q700, R706 and R722.
When the CPU judges that the system is 4.43MHz, it outputs a “Low” signal from pin 39 to
select the PAUSECAM system.
CPU
0
12V
ICI 01
I
Chroma/Def.
Pin39
L
H
L
IDENT 15
4.5 MHZ 39
Pin15
O-1.8V 4.43 MHZ No sync.
1.8V - 4.3V
4.3 v -
5.OV 4.43 MHZ Signal present
Judgement
3.58 MHz Signal present
-13-
,
Signal status
AA1-A
AAl -A
2-6 Sync. ID
When no signal is received the voltage on pin 14 of IC101 changes to “Low”. As a
consequence, D783 and Q718 are turned on, and a “High” is supplied to pin 20 of the CPU.
As a result, the CPU judges that no signal is being received. In the AV mode, the CPU
outputs a “High” signal from pin 51 to drive the blue back function.
—
CPU
Q718
a
SYNC. ID 20
R785
5.6k
E!zE5E9
SHARPNESS 7
2-7 Bus control
This chassis uses the IPC bus as the interface for operation control between ICS, and the
CPU is used as the master for operation control of the Teletext decoder, A2 Stereo decoder,
Nicam decoder and Memory IC.
The IPC bus is composed of the SCL(Serial Clock Line) and SDA(Serial Data Line) lines.
Data is transmitted over the SDA line in 8-bit units in synchronisation with the SCL line.
These lines are also used for the option function. When the TV set turns on, the CPU once
sends the slave address of the Teletext IC, Nicam IC and Stereo IC via the SDA line and
waits the ACK(Acknowledge) signal from each IC.
The CPU judges which decoder is available by receiving the ACK signal.
—;
.......................................
Sharpness control
~ D/Acircuit
.......................................
:4
Iclol
Chroma/Def.
14 SHARPNESS
L
AA1-A
CPU
SCL 12
SDA 13
IC790
R746
3.9k
d
Memory IC
6 SCL
5 SDA
AAl -A
.
2-8 Band switching circuit
The band switching control signals are outputted from pins 43and440f the CPUand fed to
the base of Q781, Q782 and Q784, band switching transistors.
The one of these transistors then outputs the drive voltage(+l 2V) to the tuner according to
output signal as shown below table.
When the UHF band is selected, “High” signal are sent from both pins 43 and 44. The D781
and D782 are cut off, then Q784 and Q783 are turned on and +12V is supplied to UHF
terminal on the tuner.
Antenna
Tuner
4
L
VI-
VH
s-
Q781
0782
44 BandII
4.7k
43 Band I
4,7k
CPU
4
u
Band Switching Logic
output
Pin43 Pin44
H
L
H H
Q783
L
H
Q784
* ---
1
Q781 Q782 Q783
I
on
off
off
off off
on off VHF-High
off on UHF
Selected Band
I
VHF-Low
-15-
AAl -A
AA1-A
2-9 Tuning and Digital AFT
The tuning system of this chassis also utilises a digital AFT system.
In this operation, the tuner is automatically adjusted to the required tuning point of the
broadcast signal by increasing and decreasing the tuning voltage within the synchronisation
range, whilst checking the 2 signals from the lF/Video decoder IC,
The signals which are outputted from
pins 4 and 44 of IC101 are fed to pins 15 and 11 of the
ICI 01 <TDA8361/8362>.
CPU via the impedance and voltage converler circuit.
The CPU checks the voltage level of the Ident signal at
11, and controls the tuning voltage which is supplied to the tuner.
pin 15 and the AFT-S signal at pin
The CPU determines that the correct tuning point is achieved when the Ident signal is Hi(5V)
and the AFT-S signal is between 2.OV to 3.OV.
When the Ident signal is Hi(5V) and AFT-S signal is greater than 3.OV, the CPU judges that
the tuning point is incorrect and increases the tuning voltage output from pin 14 of CPU to
correct the tuning point.
When the Ident signal is Hi(5V) and AFT-S signal is less than 2.OV, the CPU
that the tuning point is incorrect and decreases the tuning voltage output from
again judges –
pin 14 of CPU
to correct the tuning point.
The CPU
always maintains the correct tuning point by monitoring these two signals.
AA1-A
-16-
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