Sanyo 22VT10 Schematic

FILE NO.

SERVICE MANUAL

DVD built-in LCD TV

LCD-22VT10DVD(B)

PRODUCT CODE NO.:

1 682 348 96

REFERENCE No. SM0948001

CONTENTS

Safety precautions………………………………………………………………………..…
Alignment instructions …………………………….…….…………………………………
Method of software upgrading……………………………………………………………..
Working principle analysis of the unit……………………………….………….………….
Block diagram…………………………………..………………………………….…………
IC block diagram………………………………………………………………………..……
Wiring diagram …………………………………………………………………………….
Troubleshooting guide ………………………………………………………………..……
Schematic diagram…………………………………………………………………………
APPENDIX-A: Assembly list
APPENDIX-B: Exploded View
Removing or Installing the Stand
Wall mounting instructions

Safety precautions

1. Instructions

Be sure to switch off the power supply before replacing or welding any components or
inserting/plugging in connection wire Anti static measures to be taken (throughout the entire
production process!):
a) Do not touch here and there by hand at will;
b) Be sure to use anti static electric iron;
c) It’s a must for the welder to wear anti static gloves.
Please refer to the detailed list before replacing components that have special safety
requirements.
Do not change the specs and type at will.

2. Points for attention in servicing of LCD

2.1 Screens are different from one model to another and therefore not interchangeable. Be sure to
use the screen of the original model for replacement.

2.2 The operation voltage of LCD screen is 700-825V. Be sure to take proper measures in
protecting yourself and the machine when testing the system in the course of normal operation or
right after the power is switched off. Please do not touch the circuit or the metal part of the module
that is in operation mode. Relevant operation is possible only one minute after the power is
switched off.

2.3 Do not use any adapter that is not identical with the TV set. Otherwise it will cause fire or
damage to the set.

2.4 Never operate the set or do any installation work in bad environment such as wet bathroom,
laundry, kitchen, or nearby fire source, heating equipment and devices or exposure to sunlight etc.
Otherwise bad effect will result.

2.5 If any foreign substance such as water, liquid, metal slices or other matters happens to fall into
the module, be sure to cut the power off immediately and do not move anything on the module
lest it
should cause fire or electric shock due to contact with the high voltage or short circuit.

2.6 Should there be smoke, abnormal smell or sound from the module, please shut the power off
at
once. Likewise, if the screen is not working after the power is on or in the course of operation, the
power must be cut off immediately and no more operation is allowed under the same condition.

2.7 Do not pull out or plug in the connection wire when the module is in operation or just after the
power is off because in this case relatively high voltage still remains in the capacitor of the driving
circuit. Please wait at least one minute before the pulling out or plugging in the connection wire.

2.8 When operating or installing LCD please don’t subject the LCD components to bending,
twisting
or extrusion, collision lest mishap should result.

2.9 As most of the circuitry in LCD TV set is composed of CMOS integrated circuits, it’s necessary
to pay attention to anti statics. Before servicing LCD TV make sure to take anti static measure and
ensure full grounding for all the parts that have to be grounded.

2.10 There are lots of connection wires between parts behind the LCD screen. When servicing or
moving the set please take care not to touch or scratch them. Once they are damaged the screen

Attention: This service manual is only for service personnel to take reference with. Before

servicing please read the following points carefully.

2

would be unable to work and no way to get it repaired.
If the connection wires, connections or components fixed by the thermotropic glue need to

disengage when service, please soak the thermotropic glue into the alcohol and then pull them
out
in case of dagmage.

2.11 Special care must be taken in transporting or handling it. Exquisite shock vibration may lead
to
breakage of screen glass or damage to driving circuit. Therefore it must be packed in a strong
case
before the transportation or handling.

2.12 For the storage make sure to put it in a place where the environment can be controlled so as
to
prevent the temperature and humidity from exceeding the limits as specified in the manual. For
prolonged storage, it is necessary to house it in an anti-moisture bag and put them altogether in
one
place. The ambient conditions are tabulated as follows:

2.13 Display of a fixed picture for a long time may result in appearance of picture residue on the
screen, as commonly called “ghost shadow”. The extent of the residual picture varies with the
maker of LCD screen. This phenomenon doesn’t represent failure. This “ghost shadow” may
remain
in the picture for a period of time (several minutes). But when operating it please avoid displaying
still picture in high brightness for a long time.

3. Points for attention during installation

3.1 The front panel of LCD screen is of glass. When installing it please make sure to put it in
place.

3.2 For service or installation it’s necessary to use specified screw lest it should damage the
screen.

3.3 Be sure to take anti dust measures. Any foreign substance that happens to fall down between
the screen and the glass will affect the receiving and viewing effect

3.4 When dismantling or mounting the protective partition plate that is used for anti vibration and
insulation please take care to keep it in intactness so as to avoid hidden trouble.

3.5 Be sure to protect the cabinet from damage or scratch during service, dismantling or
mounting.

Alignment instructions

1. Test equipment

VG-848 (YPbPr,VGA signal generator)
VG-849 (HDMI signal generator)
CA210 (white balancer)

2. Power test

Connect power board, digital processing board, IR board and backlight board according the wiring
diagram, connect the power and press to turn on the TV.
Test the pin voltage of X401, the data is shown in table1:
Table1 voltage data of X401

X401 Pin1 2 3 4 5, 6 7, 8 9 10 11 12 13
Voltage 5V±5% 0 5V±5% 0 12V±5% 0

3. Alignment flow-chart

≤3.3V ≤5V ≤3.3V 32V±5% 0

Fig-1 adjustment flow-chart

4. Adjustment instruction

4.1 Unit adjustments

4.1.1Connect all the boards according to wiring diagram, then power on and observe the display.

4.1.2 Method for entering factory menu:
a) Press “SOURCE”, “2”, “5”, ”8” and “0” in turn to enter factory menu;
b) Press “

” and “” to move the cursor to the adjustment page of the level one factory menu,

then press ”OK” to enter;
c) Press “
d) Press “

” and “” to move the cursor up and down;
” and “” to adjust the item when the cursor move to a certain adjust item;

e) Press “MENU” to exit to the previous factory menu;
f) Press “EXIT” to exit the factory menu at any situation;
g) Press “OK” to enter the sub factory menu;
h)

ADC ADJUST, ADC correction of VGA, Component channel;

i)

W/B ADJUST, white balance adjustment;

j)

POWER MODE, set the turn-on modes. Standby---standby when power on; Mem---memory;
ForceOn---power on; ForceOn can be used for aging; set the “power mode” to “Standby” when
preset ex-factory unless the client appointed it;
k)

ISP MODE, ON---soft upgrading through VGA port with ISP instrument, OFF---DDC function of
VGA; the setting will not be memory and will be “OFF” when power on again;
l)

RESTALL, initialization of the factory and user data; after this item is confirm, the unit will restart
and display the guiding image.
m)

FACTORYDATAREST, factory data initialization (including white balance adjustment, ADC
correction and other adjusted data);
n)

FACEORY Channel PRESET, preset the factory channel; please connect to the center signal
source when operating; the present digital frequency is CH28(529.5MHz), CH33(564.5MHz) for
Australia, if the signal changes, perform “DTV manual search” in “Channel” menu and the
operation needs 15s or so.
o)

CUSTOM Channel PRESET, preset the custom ATV channel, they are CH2(66.5MHz),
CH7(184.5MHz), CH9(198.5MHz), CH10(212.5MHz), CH28(529.5MHz);
p)

MST DEBUG, the default is OFF. OFF---RS-232 should match the design criterion; ON--- it
should be convenient for using exploitation tool to adjust. The setting will not be memory and will
be “OFF” when power on again;
q)

BACKLIGHT: adjust the backlight brightness, adjust the data and test the voltage of X804 pin2
(PWM), let the voltage to be the corresponding PWM voltage which the brightness is maximum.
It will be preset and doesn’t need adjust.
r)

SSC ADJUST, adjust the frequency spectrum expand, it will be preset and doesn’t need adjust.

s)

AUDIO CURVE, adjust the sound curve, it will be preset and doesn’t need adjust.
t)

RF AGC delay Adj, adjust ATV RF AGC-take;
u) There is data in EEPROM after software upgrade, please perform REST ALL before the first
adjustment.

Preset ex-factory

5

4.1.3 ADC correction in D-SUB channel
a) Switch to D-SUB channel
b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu.
c) Move the cursor to “ADC ADJUST” and press OK to enter the sub-menu.
d) Input D-SUB signal (VG-848 Timing:856(1024x768/60Hz), Pattern:920 8step Gray). Move the
cursor to “MODE”, press

and to select “RGB”, move the cursor to “AUTO ADC” and press

OK to adjust automatically till display “success”.

4.1.4 ADC correction of Component channel
a) Switch to Component channel.
b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu.
c) Move the cursor to “ADC ADJUST” and press OK to enter the sub-menu.
d) Input Component signal (VG-848 Timing:969(PAL), Pattern:918 100% color bar). Move the
cursor to “MODE”, press

and to select “YPbPr(SD)”, move the cursor to “AUTO ADC” and

press OK to adjust automatically till display “success”.
e) Input Component signal (VG-848 Timing:972(1080i), Pattern:918 100% color bar). Move the
cursor to “MODE”, press

and to select “YPbPr(HD)”, move the cursor to “AUTO ADC” and

press OK to adjust automatically till display “success”.

4.2 White balance adjustment

The default of color temperature of COOL is 12000K and the coordinate is (272, 278); color
temperature of NORMAL is 9300K and the coordinate is (285,293), color temperature of WARM is
6500K and the coordinate is (313,329).

4.3 Adjustment steps
Before the white balance adjustment, please let the unit working at least 30 minutes and at a
stable situation, use BBY channel of the white balancer CA-210 (19” for example).
a) Switch to HDMI channel;
b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu.
c) Move the cursor to “W/B ADJUST” and press OK to enter the sub-menu.
d) Input HDMI signal (VG-848 Timing:856(1024X768/60Hz), Pattern:921 16 step Gray). Move the
cursor to “MODE”, press
press

and to select “COOL”.

and to select “HDMI”, move the cursor to “TEMPERTURE” and

e) Fix G GAIN, adjust R GAIN, B GAIN and let the color coordinate of the thirteenth scale be
(272,278).
f) Fix G OFFSET, adjust R OFFSET, B OFFSET and let the color coordinate of the forth scale be
(272,278).
g) When adjusting, please keep the color temperature of high light to be X=272±5, Y=278±15 and
the low light to be X=272±8, Y=278±30;
h) Move the cursor to “COPY ALL” and copy the data to the other channels (except DTV);
i) Check if the color temperatures of NORMAL and WARM are up to the mustard (NORMAL high
light acceptable error: x±10, y±15, NORMAL low light acceptable error: x±10, y±25; WARM high
light and low light acceptable error: x±10, y±10), if not, adjust R-GAIN/B-GAIN/R-OFF/B-OFF.
j) Check the white balance of other channels, if they are not up to the mustard then adjust and
store the data separately.
k) Select DTV channel and 16-level gray scale signal.
l) Press “SOURCE” and “2, 5, 8, 0” one by one to enter the level one factory menu.
m) Move the cursor to “W/B ADJUST” and press OK to enter the sub-menu.

6

n) Move the cursor to “MODE”, pressand to select “DTV”, move the cursor to “TEMPERTURE”
and press

and to select “COOL”.

o) Repeat the steps e)-I);
p) After adjustment, check if the pictures are normal.
q) The reference of adjustment rule is below:
B gun: lower B gun to increase X, Y coordinate data, while raise B gun to decrease the data;
R gun: raise R gun to increase X coordinate data, while lower R gun to decrease the data; (R
gun adjustment will affect X and Lv slightly)
G gun: raise G gun to increase Y coordinate data, while lower G gun to decrease the data; (G
gun adjustment will affect Y and Lv greatly)

5. Performance check

5.1 TV function
Connect RF to the center signal source, enter Channel menu
channels be skipped, check if the picture and speaker are normal.

5.2 AV terminals
Input AV signal, check if the picture and sound are normal.

5.3 Component terminal
Input Component signal (VG-848 signal generator), separately input the Component signals listed
in table2 and check if the display and sound are normal at any situation (power on, channel switch
and format switch, etc.)

→ auto search, check if there are

Table2 Component signal format

5.4 D-SUB terminal
Input D-SUB signal (VG-848 signal generator), separately input the signals listed in table3 and
check the display and sound. If the image is deflection of the Horizontal and vertical, select
Picture->Screen->Auto Adjusting to perform auto-correct.
Table3 D-SUB signal format

5.5 HDMI terminal
Input HDMI signal (VG-849 signal generator), separately input the signals listed in table2 and
table3
and check the display and sound (32KHz, 44.1KHz, 48KHz) at any situation (power on, channel
switch and format switch, etc.)

5.6 other functions check
a) Check the turn on/turn off timer, asleep timer, picture/sound mode, OSD, stereo and digital
sound port, etc.
b) Check the digital program, if Audio Only is normal.
c) Check logical channel number (LCN) for Australia.
d) Check OTA function for Australia special custom.

6. Presetting before ex-factory

Enter user menu LOCK page, select “Restore Factory Default” to preset the ex-factory.
a) Clear the program information
b) Clear VCHIP, parental control, etc.
c) Set the default data of user menu

8

d) Set Menu Language to English
e) Set Power on Mode to Off

Software instruction

17MB37 Analog Part Software Update With Bootloader Procedure

1.1 The File Types Used By The Bootloader

All file types that used by the bootloader software are listed below:

1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920 Kb.

2. The Config Binary File : It has “.cin extension and it is the config of the tv application.

Its size may be 64 Kb or a few times 64 Kb.

3. The Test Script File : It has “.txt” extension and it is the test script that is parsed and
executed by the bootloader. It don’t have to be any times of 64 Kb.

4. The Test Binary File : It has “.tin” extension and it is used and written by the test
groups. It is run to understand the problem part of the hardware.

Alltough a file that is used by the bootloader can be had any one of these extensions, its
name has to be “VESTEL_S” and it has to be located in the root directory of the usb
device.

1.2 Usage of The Bootloader

1. The starting to pass through : The chassis is only powered up.

2. The starting to download something : When chassis is powered up the menu key has to
be pushed.Before the chassis is powered up and if any usb device is plugged to the usb
port, the programme is downloaded from usb firstly.
Any usb device is plugged to usb port , user must open hyperterminal in the pc and
connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c connectors.
Serial connection settings are listed below:

- Bit per second: 115200

- Data bits: 8

- Parity: None

- Stop bits: 1

- Flow control: None

In this case the bootloader sofware puts “C” character to uart. After repeating “C”
characters are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing “

1K Xmodem” from protocol section.

Figure 1. The Sample Output Before Sending The File

EEProm update

To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:

- Bit per second: 9600

- Data bits: 8

- Parity: None

- Stop bits: 1

- Flow control: None

Programming menu item is choosed in the service menu and switch “HDCP Key Update
Mode” from off to on.

Figure 2. The Programming Service Menu

After then you must see Xmodem menu in the hyperterminal.To download hdcp key press
k or to download eeprom content press w.

Figure 3. Xmodem Menu

If the repeated “C” characters are seen you can transfer file content via select Transfer­>Send File and choose “

Xmodem” protocol and click the “Send” button.

Figure 4. The Starting To Send

17MB37 HDCP key upload procedure.

1) Turn on TV set.

2) Open a COM connection using fallowing parameters and select ISP COM Port No
Baud Rate: 9600 bps
Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None

3) Enter service menu by pressing “4” “7” “2” 5” consecutively while main menu is
open

4) Select “9. Programming”

5) Select “HDMI HDCP Update Mode” yes.

6) On Hyper Terminal Window press “k”

7) Click on send file under Transfer Tab.

8) Select Xmodem and choose the HDCP key to be uploaded.

9) Press send button

10)Restart TV set

17MB37 Digital Software Update From SCART

Adjusting DTV Download Mode:

1. Power on the TV.

2. Exit the Stby Mode.

3. Enter the “Tv Menu”.

4. Enter “4725” for jumping to “Service Settings”.

5. Select “8. Programming” step.

6. Change “6. DTV Download” to “On”.

7. Switch to the Stby mode.

Adjusting HyperTerminal:

1. Connect the “MB37 SCART Interface” to SCART1 (bottom SCART plug).

2. Also connect the “MB37 SCART Interface” to PC.

3. Open “HyperTerminal”.

4. Determine the “COM” settings listed and showed below.

 Bit per second: 115200
 Data bits: 8
 Parity: None
 Stop bits: 1

 Flow control: None

COM Properties Window

6. Click “OK”.

Software Updating Procedure

1. In the HyperTerminal Menu, click the “Connect” button.

2. Exit the Stby Mode.

3. The “Space” button on the keyboard must be pressed, when the following window can
be seen.

Selection Window

4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with
Xmodem”.

5. Repeating “C” characters are seen in the “HyperTerminal” menu.

The Sample Output Before Sending The File

6. Click the “Send” button on the HyperTerminal

7. Select the “Filename

xxxx_slot1.img” using “Browse”.

8. Choose the “1K Xmodem” from “Protocol” option.

Selection of File

File and Protocol Selection Window

Note: In the Software updating Procedure section, when the first “C” character is seen,
the filename selection process must be finished before 10 seconds. If the process can not
be finished, the file sending operation will be cancelled. The following figure shows this
situation.

Capture of Receving Data Failing

9. When sending the file the following window must be seen.

Capture of Sending Process

10. After the sending process the following HyperTerminal window must be seen.

Capture of End of The Sending Process

11. For sending second program file, the Software Updating Procedure must be repeated
from the step

X. Select the “Filename xxxx_slot2.img” using “Browse”.

12. After sending the second program file, the Software Updating Procedure will be
succesful.

Note: After the File Sending Process,

1. Upgrade Application with FUM

2. Upgrade Application with Xmodem, options must be seen.

End of The Sending Process

Checking Of The New Software

1. Turn off and on the TV.

2. Enter the “Setup” submenu in the “DTV Menu”.

3. Choose the “Configuration” option.

4. For controlling new software, check the “Receiver Upgrade” option.

17MB37 Digital Software Update From USB

Software upgrade is possible via USB disk by folowing the steps below.

1. Copy the bin file, including higher version than the software loaded in flash, into the
USB flash memory root directory. This file should be named up.bin.

2. Insert the USB disk.

3. Digital module performs version and CRC check. If version and CRC check is
successful, then a message prompt appears to notify user about new version. If the
user confirms loading of new version, upgrade.bin file is written into flash unused
slot.

4. Digital module disables the previous software in the flash and then a system reset
is performed.

5. After the reset, digital module starts with new software.

Revert operation:

With revert operation, it is possible to downgrade the software.
Revert operation is very similar to upgrade process. In the revert operation, file name
should be f_up.bin. Also user confirmation is not asked.

1. Copy the bin file into the USB flash memory root directory. This file should be
named force_upgrade.bin.

2. Insert the USB disk.

3. A lower version than the software in flash can be loaded with revert operation.
Digital module performs only CRC check. If CRC check is successful, then
force_upgrade.bin file is written into flash unused slot.

4. Digital module disables the previous software in the flash.

5. A message prompt is displayed to notify user about end of revert process.

6. Power off/on is required to start digital module with the new software.

For controlling new software, check the “Receiver Upgrade” option.

*****

****-

Block Diagram

IC Block Diagram

STI7101YWC

The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function LCD
monitor/TV with resolutions up to full HD (1920x1080). It is configured with an integrated
triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV video and audio
decoder, two video de-interlacers, two scaling engines, the MStarACE-3 color engine, an on-screen
display controller, an 8-bit MCU and a built-in output panel interface. By use of external frame
buffer, PIP/POP is provided for multimedia applications. Furthermore, 3-D video decoding and
processing are fulfilled for high-quality TV applications. To further reduce system costs, the
MST6WB7GQ-3 also integrates intelligent power management control capability for green­mode requirements and spread-spectrum support for EMI management.

Pin Description

Signal names are prefixed by NOT if they are active low; otherwise they are active high.
On the pin-out diagram, black indicates that the pin is reserved and must not be used.
The following pages give the allocation of pins to the package, shown from the top looking down
using the PCB footprint.

Table : Key to pin-out diagram

STx7101 Pin list and alternative functions

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

LMIVID

LMIVID

DAT ASTRO

A

BE[0]

LMIVID

DAT A

B

C

D

E

DATASTRO

MASK[0]

GNDE GNDE GNDE GNDE GNDE GNDE GNDE

TRIGGER

OUT

TMUCLK

DATA

MASK[2]

LMIVID

BE[2]

NOT

RESETIN

WDOG

RSTOUT

LMIVID

DATA[16]

LMIVID

DATA[17]

NOT

TRST

NOT

ASEBRK

F

G

Pin-out (R)

H

J

K

L

M

VDD VDD GND GND GND

N

VDD GND GND GND GND

P

VDD GND GND GND VDD

R

GND GND GND VDD VDD

T

GND GND GND VDD VDD

U

GND GND GND VDD VDD

V

GND GND GND VDD VDD

W

VDD GND GND GND VDD PIO5[6] PIO5[7]

Y

Confidential

VDD GND GND GND GND PIO4[7] PIO5[5]

AA

VDD VDD GN D GND GND PIO4[5] PIO4[6]

AB

AC

LMIVID

LMIVID

DATA[18]

DATA[20]

LMIVID

LMIVID

DATA[19]

DATA[21]

TCK TDI GNDE

TMS TDO GNDE

LMIVID

DATA[22]

LMIVID

DATA[23]

GNDE

GNDE

AUDSPDIF

OUT

AUDS

CLKOUT

AUDPCM

OUT0

AUDPCM

OUT1

AUDPCM

OUT2

AUDPCM

OUT3

AUDPCM

OUT4

VDDE

3V3

VDDE

3V3

VDDE

3V3

AUDPCM
CLKOUT

AUDLR

CLKOUT

AUDANA

MLEFT

OUT

AUDANA

PLEFT

OUT

AUDANA

IREF

GND_ANA

SYSBCLK

INALT

AUDANA
MRIGHT

OUT

AUDANA

PRIGHT

OUT

AUDANA

VBGFIL

AUDDIG

STRBIN

AUDDIGLR

CLKIN

NC

AUD_
VCCA

FS0_
VCCA

AUDDIG

DAT AIN

VDDE2V5_

PLL80_

ANA

AUD_

VIDANA

GNDA

REXT[0]
VIDANA

AUD_

GNDAS

REXT[0]

NC

DA_HD_0_

VDDE2V5_

VCCA

AUD_ANA

DA_SD_0_

VDDE2V5_

VCCA

FS0_ANA

GNDE_

DA_SD_0

_GNDA

FS0_

VDDD

CKGB_

CKGB_
4FS1_
VDDD

CKGB_

CKGB_
4FS0_
VDDD

DVDD

PLL80V0

PLL80V0

CKGB_

4FS1_
VCCA

CKGB_

CKGB_
4FS0_
VCCA

AVDD

DIGOUT

PLL80V0

VID

DIGOUT

DIGOUT

YC[14]

VID

DIGOUT

DIGOUT

YC[12]

VID

DIGOUT

DIGOUT

YC[10]

VID

DIGOUT

YC[8]

GNDE

3V3

TMDS

VDDE3V3

VDDC0

PIO4[3] PIO4[4]

GNDA

FS0_

GNDA

4FS_

ANA

FS0_

GNDD

4FS1_
GNDD

4FS0_
GNDD

DGND

NC

4FS0_
GNDA

VID

YC[15]

VID

YC[13]

VID

YC[11]

VID

YC[9]

GNDE

3V3

TMDS

VDD

TMDS

VIDANA
REXT[1]

VIDANA

GNDA

REXT[1]

DA_HD_0_

GNDA

AGNDPLL

80V0

GNDE_

AUD_ANA

GNDE_

FS0_

ANA

VDDE2V5

_4FS_ANA

VDDE2V5

_VID_ANA

GNDE_

VID_ANA

GNDE_
PLL80_

ANA

CKGB_

4FS1_
GNDA

GND_

ANA

TMDS
VSSD

TMDS
VSSP

TMDS
GNDE

TMDS

REF

TMDS

VSSSL

TMDS

VSSCK

TMDS

VDDCK

TMDS

VDDC1

TMDS

VDDSL

TMDS
VDDD

TMDS
VDDP

VIDANAID

VIDANAC1

UMPC1

VIDANAID

VIDANAY1

UMPY1

VIDANAID

VIDANACV

UMPCV1

1OUT

VIDANAID

VIDANAR0

UMPR0

VIDANAID

VIDANAB0

UMPB0

VIDANAID

VIDANAG0

UMPG0

VDDE

VDDE

3V3
VID

DIGOUT

DIGOUT

YC[7]

YC[6]

VID

DIGOUT

DIGOUT

YC[5]

YC[4]

VID

DIGOUT

DIGOUT

YC[3]

YC[2]

VID

DIGOUT

DIGOUT

YC[1]

YC[0]

VID

DIGOUT

DIGOUT

HSYNC

VSYNC

TMDS

TMDS

VSSC1

VSSC0

TMDS

TMDS

TX2P

TX2N

TMDS

TMDS

TX1P

TX1N

TMDS

TMDS

TX0P

TX0N

TMDS

TMDS

TXCP

TXCN

TMDS

TMDS

VSSX

VSSC2

TMDS

TMDS

VDDX

VDDC2

PIO5[4] PIO5[3]

PIO5[2] PIO5[1]

PIO5[0] PIO3[7]

PIO3[6] PIO3[5]

OUT

OUT

OUT

OUT

OUT

3V3
VID

VID

VID

VID

VID

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

EMIA

DDR[16]

EMI

ADDR[17]

VDD VDD

EMI

DATA[10]

EMI

DATA[2]

EMI

ADDR[18]

EMI

ADDR[19]

EMI

DAT A[9]

EMI

DAT A[1]

EMI

ADDR[20]

EMI

ADDR[21]

EMI

BUSREQ

EMI

DATA[8]

EMI

DATA[0]

EMI

ADDR[22]

EMI

ADDR[23]

EMI

BUSGNT

EMI

FLASHCLK

NOT

EMIBAA

EMIT

READYOR

WAIT

EMIDMA

REQ[1]

GND

EMIDMA

REQ[0]

NOT

EMILBA

VDDE3V3 VDDE3V3

USB

USB

VSSBS

VDDB3V3

USB

USB

VSSP

VDDBC

2V5

2V5

USB

USB

VSSC

VDDP

2V5

2V5

USB

USB

VSSP

VDDP

SYS

ITRQ[0]

ITRQ[1]

USB

VDDBS

VDDOSC

SATAVDD

USBREF

OSC2V5

USBDP GND

USBDM GND

SYS

SATA

SYS

ITRQ[2]

SATA

VSSOSC

SATA

VSSREF

SYSB

CLKOSC

SYSB
CLKIN

SYS

ITRQ[3]

SATA

VDDR[1]

SATA

VSSDLL

SATA

VSSR

SATA

VSST

PIO4[1] PIO4[2] PIO4[0] PIO3[4]

PIO2[7] PIO2[6] PIO3[0] PIO3[2]

VDDE

VDD

3V3

PIO2[4] PIO2[5]

PIO2[2] PIO2[3]

PIO2[0] PIO2[1]

GND GND GND

SATA

VDDDLL

SATA

VDDR[0]

SATA

VDDT[0]

SATA

VDDT[1]

SATAVDDR

GND PIO0[7] PIO1[1]

EF

ATAREF NC PIO0[0] PIO0[5]

ATATXP ATARXP GND PIO0[2]

ATATXN ATARXN GND PIO0[1]

VDDE

GNDE

GNDE

GNDE

GNDE

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

7983497A STMicroelectronics Confidential 57/1172

3V3

3V3

3V3

3V3

3V3

VDDE

3V3

GNDE

3V3

PIO1[7]

PIO1[5]

PIO1[3]

PIO3[3]

PIO3[1]

VDDE

3V3

GNDE

3V3

PIO1[6]

PIO1[4]

PIO1[2]

PIO1[0]

PIO0[6]

PIO0[4]

PIO0[3]

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

Pin list and alternative functions STx7101

7.2 Alternative functions

To impr ove flexibility and to allow the STx7101 to fit into differ ent set-top box application
architectures, the input and output signals from some of the peripherals and functions are not
directly connected to t he pi ns of the device. Instead they are assigned t o t he alternative functi on
inputs and outputs of a PIO port bit, or an I/O pi n. This scheme allows the pins to be configured
with their default function if the associated input or output is not required in that particular
application.

Some pins have several alternative functions, for inputs and/or outputs. In Table 6 to Table 11,
the different alternative functions are listed under the table headings Alt 1, Alt 2, to Alt n.

Inputs connec ted to the alternative function input are permanently connected to the input pin.
The output signa l from a peripheral is only connected when the PIO bit is configured into either
push-pull or open drain driver alternative function mode.

Some alternative function signals are available on more than one PI O port.

Figure 20: I/O port pins

Pin

Confidential

Push-pull
tri-state
open drain
weak pull-up

Alternative function

Alternative function output

1 0

Output latch

Alternative function input

Input latch

58/1172 STMicroelectroni cs Confide ntial 7983497A

TUNER

A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH).
The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info about the tuner.

1.1. General description of TDTC-G101D:

The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to

863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.

1.2. Features of TDTC-G101D:

 Digital Half-NIM tuner for COFDM
 Covers 3 Bands(From 48MHz to 862MHz for COFDM,
 From 45.25MHz to 863.25MHz for CCIR CH)
 Including IF AGC with SAW Filter
 Bandwidth Switching (7/8 MHz) possible
 DC/DC Converter built in for Tuning Voltage
 Internal(or External) RF AGC, Antenna Power Optional

1.3. Pinning:

Audio Amplifier

MAX9736(8-10WATT)

General Description

The MAX9736A/B Class D amplifiers provide high-performance,thermally efficient
amplifier solutions. The

into a 4Ω load. The MAX9736B delivers 2 x 6W into 8Ω loads or 1 x 12W into a 4Ω

These devices are pinfor pin compatible, allowing a single audio design to work across a
broad range of platforms, simplifying design efforts, and reducing PCB inventory.
Both devices operate from 8V to 28V and provide a high PSRR, eliminating the need for a
regulated power supply. The MAX9736 offers up to 88% efficiency at 12V supply.
Pin-selectable modulation schemes select between filterless modulation and classic PWM
modulation.
Filterless modulation allows the MAX9736 to pass CE EMI limits with 1m cables using
only a low-cost ferrite bead and capacitor on each output. Classic PWM modulation
is optimized for best audio performance when using a full LC filter.
A pin-selectable stereo/mono mode allows stereo operation

operation into 4Ω loads. In

spare device, allowing flexibility in system design. Comprehensive click-and-pop reduction
circuitry minimizes noise coming into and out of shutdown or mute.
Input op amps allow the user to create summing amplifiers, lowpass or highpass filters,
and select an optimal gain. The MAX9736A/B are available in 32-pin TQFN packages
and specified over the -40°C to +85°C temperature range.

MAX9736A delivers 2 x 15W into 8Ω loads, or 1 x 30W

load.

into 8Ω loads or mono

mono mode, the right input op amp becomes available as a

Features

Wide 8V to 28V Supply Voltage Range
♦ Spread-Spectrum Modulation Enables Low EMI
Solution
♦ Passes CE EMI Limits with Low-Cost Ferrite
Bead/Capacitor Filter

♦ Low BOM Cost, Pin-for-Pin Compatible Family
♦ High 67dB PSRR at 1kHz Reduces Supply Cost
♦ 88% Efficiency Eliminates Heatsink
♦ Therm
♦ < 1μA Shutdown Mode
♦ Mute Function
♦ Space

Package

al and Output Current Protection

-Saving, 7mm x 7mm x 0.8mm, 32-Pin TQFN

Applications

LCD/PDP/CRT Monitors
LCD/PDP/CRT TVs
MP3 Docking Stations
Notebook PCs
PC Speakers
All-in-One PCs

Absolute Ratings

Electrical Characteristics

Operating Specifications

Pinning

PT2333(2.5 WATT)

Description

The PT2333 is a Class-D power amplifier designed for audio equipments, maximum
output power can reach
composed of exclusively designed Class-D circuitry (patented) by PTC, along with
the most advanced semi-conductor technology. When compared to the traditional
Class-AB amplifiers, the PT2333’s has a much higher efficiency (>80%), low
heat dissipation, and produces superior audio quality. PT2333’s external circuitry is
simple and easily accessible, and consists of flawless self-protection capabilities.
The chip’s packaging is small, thus it occupies an insignificant amount of space on
the circuit board; therefore, making it the predominant choice when it comes to
audio amplifiers.

up to 2.5W (VDD=5V, RL=4Ω, THD=10%). The PT2333

Features

CMOS technology
Operating voltage range from 2.7V up to 5.5V
Differential analog input
Maximum output power 2.5W(4Ω) @ THD=10%
Output low-pass LC filter is not required.
Voltage gain determinate by the external resister
Contains shutdown function
POP noises free in shutdown and power ON/OFF

period

Built-in short circuit protection
Built-in overheat protection
High efficiency (8Ω load >85%), low heat

dissipation
Available in MSOP 10-pin and WLCSP 9-pin
miniature packages



Aplications

Cellular phone
Portable media player
GPS
LCD monitor
Small multimedia speakers
Hand-free phone
Laptop
Other audio applications

Block Diagram

POWER STAGE

The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V,
3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V stand
by voltage and 8V, 2.5V, 2,6V, 1,8V and 1V supplies for other different parts of the
chassis.

ADAPTOR USE (Optional)

The DC voltages required at various parts of the chassis and inverters are provided by an
external power supply unit or produced on the chassis if an adapter is used for the supply.
The 12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical
switch to produce the required standby voltage. Also regulators and mosfets generate

1.8V, 3.3V and 5V and 1.26V voltages for other different parts of the chassis.

MPEG-2/MPEG-4 DVB Decoder (STi7101)

1.4. General Description

The STi7101 is a new generation, high-definition IDTV / set-top box / DVD decoder chip, and
provides very high performance for low-cost HD systems. STx7101 includes an H.264 video
decoder for new, low bit rate applications. Based on the Omega2 (STBus) architecture, this
system-on-chip is a full back-end processor for digital terrestrial, satellite, cable, DSL and IP
client high-definition set-top boxes, compliant with ATSC, DVB, DIRECTV, DCII,
OpenCable and ARIB BS4 specifications. It includes all processing for DVD applications.

The STx7101 demultiplexes, decrypts and decodes HD or SD video streams with associated
multi-channel audio. Video is output to two independently formatted displays: a full resolution
display intended for a TV monitor, and a downsampled display intended for a VCR or DVD-R.
Connection to a TV or display panel can be analog through the DACs, or digital through a copy
protected DVI/HDMI. Composite outputs are provided for connection to the VCR with
Macrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface,
PCM interface, or through integrated stereo audio DACs. Digitized analog programs can also
be input to the STx7101 for reformatting and display. The STx7101 includes a graphics
rendering and display capability with a 2D graphics accelerator, three graphics planes and a
cursor plane. A dual display compositor provides mixing of graphics and video with
independent composition for each of the TV and VCR/DVD-R outputs. The STx7101 includes
a stream merger to allow seven different transport streams from different sources to be merged
and processed concurrently. Applications include DVR time-shifted viewing of a terrestrial
program, while acquiring an EPG/data stream from a satellite or cable front end.

The flexible descrambling engine is compatible with required standards including DVB, DES,
AES and Multi2. The STx7101 embeds a 266 MHz ST40-202 CPU for applications and device
control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the
video decoder the required memory bandwidth for HD H.264 and sufficient bandwidth for the
CPU and the rest of the system. A second memory bus is also provided for flash memory,
storing resident software, and for connection of peripherals. This bus also has a high speed
synchronous mode that can be used to exchange data between two STx7101 devices. This can
be used to connect a second STx7101 as a co-decoder for a dual TV STB application. A hard­disk drive (HDD) can be connected either to the serial ATA interface, or as an expansion drive
through the USB 2.0 port.

The figure below shows the architecture of the Sti7101.

6.2 Features

The STx7101 is a single-chip, high definition video decoder including:

_ H.264 support
_ Linux® and OS21 compatible ST40 CPU core: 266 MHz
_ transport filtering and descrambling
_ video decoder: H.264 (MPEG-4 part 10) and MPEG-2
_ SVP compliant
_ graphics engine and dual display: standard and highdefinition
_ audio decoder
_ DVD data retrieval and decryption

The STx7101 also features the following embedded interfaces:

_ USB 2.0 host controller/PHY interface
_ DVI/HDMI™ output
_ digital audio and video auxiliary inputs
_ low-cost modem
_ 100BT ethernet controller with integrated MAC and MII/ RMII interface for external PHY
_ serial ATA (SATA)

Processor subsystem

_ ST40 32-bit superscaler RISC CPU
_ 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU
_ 5-stage pipeline, delayed branch support
_ floating point unit, matrix operation support
_ debug port, interrupt controller

Transport subsystem

_ TS merger/router
_ 2 serial/parallel inputs
_ 1 bidirectional interface
_ merging of 3 external transport streams
_ transport streams from memory support
_ NRSS-A module interface
_ TS routing for DVB-CI and CableCARD

modules

_ Programmable transport interfaces (PTIs)
_ two programmable transport interfaces
_ two transport stream demultiplexers: DVB, DIRECTV®, ATSC, ARIB, OpenCable, DCII
_ integrated DES, AES, DVB and Multi2 descramblers
_ NDS random access scrambled stream protocol (RASP) compliant
_ NDS ICAM CA
_ support for VGS, Passage and DVS042 residue handling

Video/graphics subsystem

_ H.264(MPEG-4 part 10) main and high profile level 4.1/MPEG-2 MP@HL video decoder
_ advanced error concealment and trick mode support
_ dual MPEG-2 MP@HL decode
_ SD digital video input
_ Displays
_ one HD display multi format capable (1080I, 720P, 480P/576P, 480I/576I)

 analog HD output RGB or YPbPr
 HDMI encoded output

_ one standard-definition display

 analog SD output: YPbPr or YC and CVBS

_ Gamma 2D/3D graphics processor
_ triple source 2D gamma blitter engine
_ alpha blending and logical operations
_ color space and format conversion
_ fast color fill
_ arbitrary resizing with high quality filters
_ acceleration of direct drawing by CPU
_ Gamma compositor and video processor
_ 7-channel mixer for high definition output
_ independent 2-channel mixer for SD output
_ 3 graphic display planes
_ high-quality video scaler

_ motion and detail adaptive deinterlacer
_ linear resizing and format conversions
_ horizontal and vertical filtering
_ Copy protection
_ HDMI /HDCP copy protection hardware
_ SVP compliant
_ Macrovision® copy protection for 480I, 480P, 576I, 576P outputs
_ DTCP-IP
_ AWG-based DCS analog copy protection

Audio subsystem

_ Digital audio decoder
_ support for all the most popular audio standards including MPEG-1 layer I/II, MPEG-2 layer
II, MPEG-2 AAC, MPEG- 4 AAC LC 2-channel/5.1 channel MPEG-4 AAC+SBR 2­channel/5.1 channel, Dolby® Digital EX, Pro Logic® II, MLP™ and DTS®
_ PCM mixing with internal or external source and sample rate conversion
_ 6- to 2-channel downmixing
_ PCM audio input
_ independent multichannel PCM output, S/PDIF output and analog output
_ Stereo 24-bit audio DAC for analog output
_ IEC958/IEC1937 digital audio output interface (S/PDIF)
_ CSS/CPxM copy protection hardware Interfaces
_ External memory interface (EMI)
_ 16-bit interface supporting ROM, flash, SFlash, SRAM, peripherals
_ access in 5 banks
_ high speed synchronous mode for interconnecting two STx7101 devices
_ External microprocessor interface (EMPI)
_ 32-bit MPX satellite, target-only interface,
_ synchronous operation at MPX clock speed, capable of 100 MHz,
_ Dual local memory interface (LMI)
_ dual interface (2 x 32-bit) for DDR1 200-MHz (DDR400) memories,

supports 128-, 256- and 512-Mbit devices
_ USB 2.0 host controller/PHY interface
_ Serial ATA hard-disk drive support
_ record and playback with trick modes
_ pause and time shifting, watch and record
_ 100BT Ethernet controller, MAC and MII/RMII
_ On-chip peripherals
_ 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can be used in smartcard interfaces
_ 2 smartcard interfaces and clock generators (improved to reduce external circuitry)
_ 3 SSCs for I²C/SPI master slaves interfaces
_ serial communications interface (SCIF)
_ 2 PWM outputs
_ teletext serializer and DMA module
_ 6 banks of general purpose I/O, 3.3 V tolerant
_ SiLabs line-side (DAA) interface
_ modem analog front end (MAFE) interface
_ infrared transmitter/receiver supporting RC5, RC6 and RECS80 codes

_ UHF remote receiver input interface
_ interrupt level controller and external interrupts, 3.3 V tolerant
_ low power/RTC/watchdog controller
_ integrated VCXO
_ DiSEqC 2.0 interface
_ PWM capture/compare functions
_ Flexible multi-channel DMA Services and package
_ JTAG/TAP interface, ST40 toolset support, ST231 toolset support
_ Package
_ 35 x 35 PBGA, 580 + 100 balls (standard version)

6.3 Absolute Maximum Ratings

I/O specifications 3.3 volt pads

I/O specifications 2.5 volt pads

DVB-T DEMODULATOR – STV0362

8.1 General Description

The STv0362 is a single-chip demodulator using coded orthogonal frequency division
multiplexing (COFDM) and is intended for digital terrestrial receivers using compressed
video, sound and data services. It converts IF or baseband differential signals to MPEG-2
format by processing OFDM carriers.

The STv0362 is fully compliant with the DVB-T specification (ETS 300 744) and NorDig
Unified specification. The chip implements all the functions to convert the signals from the
IF or direct conversion tuner, to produce the MPEG-2 transport stream output; in terms of
IF tuner configuration, the chip is compatible with the popular STV0360/STV0361. The
STv0362 offers improved performance over the STV0360 with respect to:

 channel estimation and correction,

 an extended CRL frequency and TRL timing offset,

 additional features such as:

o synchronization for echo outside GI,
o impulse noise rejection,
o PLL allowing 4 MHz quartz usage.

The STv0362 processes 2, 4 and 8 K modes and integrates two A/D converters capable
of handling up to 64 QAM carriers in a direct IF or zero IF sampling architecture. This
eliminates the need for an external downconverter. A 12-bit ADC, intended for RF signal
strength indication, eliminates the need for external components when using wide-band
AGC tuners. In addition to the demodulation and forward error correction (FEC) functions
required for recovery of the QAM modulated bit streams with very low BER, the chip also
includes several features that give easy and immediate access to various quality
monitoring parameters or lock status. The STv0362 also provides delayed AGC and a
noise-free I2C bus dedicated to tuner control, which facilitate the design of high quality
integrated receiver decoders. The STv0362 outputs an error-corrected MPEG-2 transport
stream that complies with the DVB common interface format with programmable data
clock frequency.

The STv0362 features the full DVB-T and DVB-H standards framing structure, channel
coding and modulation. The symbol, timing and carrier recovery loops are fully digital and
sized with regard to the state-of-the-art RF down-converting devices.

The STv0362 is compatible with direct conversion tuners featuring two differential ADC for
I and Q channels. The tuner baseband power is controlled by a classic AGC loop, and the
radio frequency level is monitored by a dedicated single-ended 8-bit ADC. It is
recommended the RF power is left under the tuner’s control, but it can be derived from
baseband power by a dedicated power split algorithm. If required, the tuner serial I2C bus
can be isolated by the STv0362 I2C bus repeater.

The terrestrial DVB-T network can be subjected to several interference sources which are
the neighboring digital and analog channels, as well as the in-band analog channels. The
STv0362 cancels these interference sources as well removing the effects of impulse
noise. The channel equalization is capable of static and dynamic echo cancelling even in
severe urban environments. The embedded algorithms are enhanced to cope with out-of­guard interval echoes; specific channel quality monitoring is available for acquisition and
survey. The specific power handling constraints are primarily addressed by both
technology and clock rate management. The efficiency of channel acquisition and re­acquisition, minimizes power consumption.

8.2 Features

 Compatible with direct conversion (ZIF) and IF tuners

o Wide range carrier tracking loop for offset recovery

o Dual analog to digital conversion for IQ baseband interface

o Signal strength indicator dedicated ADC

o Dual ΣΔ digital split AGC for RF and BB

o Flexible clock generation to operate with 4 MHz to 27 MHz external reference

 Channel management

o NorDig Unified Specification (v1.0.2) capable

o Dynamic fading compatible

o Urban environment compatible

o Channel reception quality indicator

o Out of guard interval echoes compatible

o Impulsive noise rejection capable

o Outstanding adjacent and co-channel rejection capability with integrated

channel filters

 Digital carrier, timing and symbol recovery loops

 Decoding

o 2K, 4K, 8K FFT length

o 6, 7 and 8 MHz channels bandwidth

o 1/4, 1/8, 1/16, 1/32 guard interval length

o QPSK - 16 QAM - 64 QAM modulations

o Hierarchical capability

o TPS decoding

o Viterbi soft decoder rate 1/2

o Puncture rates are 1/2, 2/3, 3/4, 5/6, 7/8

o Outer Reed-Solomon decoder as per DVB-T system

o Energy dispersal descrambler

 Technology

o Low power CMOS process (90nm)

o Multi supply: 1.0 V core, 2.5 V analog, 3.3 V digital interface

o TQFP64 7x7x1.0 mm

o Power consumption: 350 mW (typ),

o Standby < 80 mW

 Data to transport decoder

o DVB common interface compliant

o 12-bit parallel and 5-bit serial data interface with data on D7

(packet error private line)

o Automatic regulation of the transport bit

o rate with regard to transport clock

o Up to 33 Mbit/s payload data rate

 I2C serial bus interface

o Fast I2C up to 400 kHz slave interface

o Four possible slave addresses

o Up to 400 kbit/s private repeater for tuner isolation

 GPIOs and interruption line

o Lock indicators: AGC, symbol, TPS, VITERBI-decoder and transport

synchronization

o ΣΔ analog and logical levels generation

 Monitoring through I2C serial interface

o C/N estimator

o Constellation and frequency response display

o BER and PER estimator

8.3 Absolute Maximum Rating

8.4 Pinning

DVB-C DEMODULATOR – STV0297E

7.1 General Desription

The STV0297E is a complete single-chip QAM (quadrature amplitude modulation)
demodulation and FEC (forward error correction) solution that performs sampled IF to
transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended for
the digital transmission of compressed television, sound, and data services over cable. It
is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification bitstreams (ETS
300 429, “Digital broadcasting systems for television, sound and data services – Framing
structure, channel coding and modulation - Cable Systems”). It can handle square (16,
64, 256-QAM) and non-square (32, 128-QAM) constellations. Japanese DBS systems
require a transport stream multiplex frame (TSMF) layer to carry digital signals over cable
systems. When the recovered transport stream is a multiplex frame, the STV0297E post­processes it to extract a single transport stream. Automatic detection of the TSMF layer is
provided. The chip integrates an analog-to-digital converter that delivers the required
performance to handle up to 256-QAM signals in a direct IF sampling architecture, thus
eliminating the need for external downconversion.

7.2 Features

 Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
 Processes Japanese transport stream multiplex frame (TSMF)
 High-performance integrated A/D converter suitable for direct IF architecture in all

QAM (quadrature amplitude modulation) modes

 Supports 16, 32, 64, 128 and 256 point constellations
 Small footprint package: (10 x 10 mm²)
 Very low power consumption
 Full digital demodulation
 Variable symbol rates
 Front derotator for better low symbol rate performance and relaxed tuner

constraints

 Integrated matched filtering
 Robust integrated adaptive pre and post equalizer
 On-chip FEC A/C with ability to bypass individual blocks
 10 programmable GPIO
 Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
 Integrated signal quality monitors, plus lock indicator and interrupt function mapped

to GPIO pin

 Improved signal acquisition
 System clock generated on-chip from quartz crystal
 Low frequency crystal operations 4, 16, 25 - 30 MHz
 4 I2C addresses
 Easy control and monitoring via 2-wire fast I2C bus

7.3 Absolute Maximum Ratings

7.4 Pinning

STE100P Ethernet PHY

7.5 General Description

The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet
physical layer interface for 10Base-T and 100Base-TX applications. It was designed with
advanced CMOS technology to provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for
100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3.

The STEPHY1 supports both half-duplex and fullduplex operation, at 10 and 100 Mbps
operation. Its operating mode can be set using auto-negotiation, parallel detection or
manual control. It also allows for the support of auto-negotiation functions for speed and
duplex detection.

7.6 Features

- IEEE802.3u 100Base-TX and IEEE802.3 10Base-T compliant

- Support for IEEE802.3x flow control

- IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX

- MII interface

- Standard CSMA/CD or full duplex operation supported

- Integrates the whole Physical layer functions of 100Base-TX and 10Base-T

- Provides Full-duplex operation on both 100Mbps and 10Mbps modes

- Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100
Mbps

- Provides MLT-3 transceiver with DC restoration for Base-line wander compensation

- Provides transmit wave-shaper, receive filters, and adaptive equalizer

- Provides loop-back modes for diagnostic

- Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder

- Supports external transmit transformer with turn ratio 1:1

- Supports external receive transformer with turn ratio 1:1

- Standard 64-pin QFP package pinout

7.7 Absolute Maximum Ratings

12.4 Pinning

8 SAW FILTER

8.1 IF Filter for Audio Applications – Epcos K9656M

8.1.1 Standart:

 B/G
 D/K
 I
 L/L’

8.1.2 Features:

 TV IF audio filter with two channels
 Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75

MHz (L’- NICAM)

 Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz

and 33,40 MHz

8.1.3 Pin configuration:

1 Input

2 Switching input

3 Chip carrier - ground

4 Output

5 Output

8.1.4 Frequency response:

8.2 IF Filter for Video Applications – Epcos K3958M

8.2.1 Standart:

 B/G
 D/K
 I
 L/L’

8.2.2 Features:

 TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
 Constant group delay

Pin configuration:

1 Input

2 Input - ground

3 Chip - carrier ground

4 Output

5 Output

8.2.3 Frequency response:

IC DESCRIPTIONS

8.3 LM1117

8.3.1 General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA
of load current. It has the same pin-out as National Semiconductor’s industry standard
LM317. The LM1117 is available in an adjustable version, which can set the output
voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D­tantalum capacitor is required at the output to improve the transient response and
stability.

8.3.2 Features

 Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
 Space Saving SOT-223 Package
 Current Limiting and Thermal Protection
 Output Current 800mA
 Line Regulation 0.2% (Max)
 Load Regulation 0.4% (Max)
 Temperature Range
 LM1117 0°C to 125°C
 LM1117I -40°C to 125°C

PAK packages. A minimum of 10μF

8.3.3 Applications

 2.85V Model for SCSI-2 Active Termination
 Post Regulator for Switching DC/DC Converter
 High Efficiency Linear Regulators 15
 32” TFT TV Service Manual 10/01/2005
 Battery Charger
 Battery Powered Instrumentation

8.3.4 Absolute Maximum Ratings

8.3.5 Pinning

8.4 74HCT4053

8.4.1 General Description

The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The
74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to
S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to
S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and
E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).

8.4.2 Features

 Low ON resistance:

 80 W (typical) at VCC - VEE = 4.5 V

 70 W (typical) at VCC - VEE = 6.0 V

 60 W (typical) at VCC - VEE = 9.0 V

 Logic level translation:

 To enable 5 V logic to communicate with ±5 V analog signals

 Typical ‘break before make’ built in

 Complies with JEDEC standard no. 7A

 ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-

A115-A exceeds 200 V

 Multiple package options

 Specified from -40 °C to +85 °C and from -40 °C to +125 °C

8.4.3 Applications

 Analog multiplexing and demultiplexing

 Digital multiplexing and demultiplexing

 Signal gating

8.4.4 Absolute Maximum Ratings

8.4.5 Pinning

8.5 NUP4004M5

8.5.1 General Description

This 5-Pin bi-directional transient suppressor array is designed for applications requiring
transient overvoltage protection capability. It is intended for use in transient voltage and

ESD sensitive equipment such as computers, printers, cell phones, medical equipment,
and other applications. Its integrated design provides bi-directional protection for four
separate lines using a single TSOP-5 package. This device is ideal for situations where
board space is a premium.

8.5.2 Features

 Bi-directional Protection for Four Lines in a Single TSOP-5 Package

 Low Leakage Current

 Low Capacitance

 Provides ESD Protection for JEDEC Standards JESD22

 Machine Model = Class C

 Human Body Model = Class 3B

 Provides ESD Protection for IEC 61000-4-2, 15 kV (Air), 8 kV (Contact)

 This is a Pb-Free Device

8.5.3 Absolute Maximum Ratings

8.5.4 Pinning

8.6 FDN336P

8.6.1 General Description

The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM
data clocked out from the rising edge of the signal applied on VCLK. The device will
switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power
supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages
are available.

8.6.2 Features

 1 MILLION ERASE/WRITE CYCLES

 40 YEARS DATA RETENTION

 2.5V to 5.5V SINGLE SUPPLY VOLTAGE

 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE

 TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE

 PAGE WRITE (up to 8 BYTES)

 BYTE, RANDOM and SEQUENTIAL READ MODES

 SELF TIMED PROGRAMMING CYCLE

 AUTOMATIC ADDRESS INCREMENTING

 ENHANCED ESD/LATCH UP PERFORMANCES

8.6.3 Absolute Maximum Ratings

8.6.4 Pinning

8.7 TL062 -

8.7.1 General Description

Low-power JFET-input operational amplifier

8.7.2 Features

 Very Low Power Consumption

 Typical Supply Current . . . 200 µA (Per Amplifier)

 Wide Common-Mode and Differential Voltage Ranges

 Low Input Bias and Offset Currents

 Common-Mode Input Voltage Range Includes VCC+

 Output Short-Circuit Protection

 High Input Impedance . . . JFET-Input Stage

 Internal Frequency Compensation

 Latch-Up-Free Operation

 High Slew Rate . . . 3.5 V/µs Typ

8.7.3 Absolute Maximum Ratings

8.7.4 Pinning

8.8 PI5V330

8.8.1 General Description

Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading
performance. The PI5V330 is a true bidirectional Quad 2-channel
multiplexer/demultiplexer that is recommended for both RGB and composite video
switching applications. The VideoSwitch. can be driven from a current output RAMDAC or
voltage output composite video source. Low ON-resistance and wide bandwidth make it
ideal for video and other applications. Also this device has exceptionally high current
capability which is far greater than most analog switches offered today. A single 5V
supply is all that is required for operation. The PI5V330 offers a high-performance, low­cost solution to switch between video sources. The application section describes the
PI5V330 replacing the HC4053 multiplier and buffer/amplifier.

8.8.2 Features

 High-performance, low-cost solution to switch between video sources
 Wide bandwidth: 200 MHz
 Low ON-resistance: 3Ω
 Low crosstalk at 10 MHz: .58 dB
 Ultra-low quiescent power (0.1 µA typical)
 Single supply operation: +5.0V
 Fast switching: 10 ns
 High-current output: 100 mA
 Packages available:
 16-pin 300-mil wide plastic SOIC (S)
 16-pin 150-mil wide plastic SOIC (W)
 16-pin 150-mil wide plastic QSOP (Q)

8.8.3 Absolute Maximum Ratings

8.8.4 Pinning

8.9 AZC099-04S

8.9.1 General Description

AZC099-04S is a high performance and low cost design which includes surge rated diode
arrays to protect high speed data interfaces. The AZC099-04S family has been
specifically designed to protect sensitive components, which are connected to data and
transmission lines, from over-voltage caused by Electrostatic Discharging (ESD),
Electrical Fast Transients (EFT), and Lightning.
AZC099-04S is a unique design which includes surge rated, low capacitance steering
diodes and a unique design of clamping cell which is an equivalent TVS diode in a single
package. During transient conditions, the steering diodes direct the transient to either the
power supply line or to the ground line. The internal unique design of clamping cell
prevents over-voltage on the power line, protecting any downstream components.
AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2,
Level 4 (± 15kV air, ±8kV contact discharge).

8.9.2 Features

 ESD Protect for 4 high-speed I/O channels
 Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air),

±8kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 40A for Power

IEC 61000-4-5 (Lightning) 4A (8/20

 5V operating voltage  Low capacitance : 1.0pF typical
 Fast turn-on and Low clamping voltage
 Array of surge rated diodes with internal equivalent TVS diode
 Small package saves board space
 Solid-state silicon-avalanche and active circuit triggering technology

μs)

8.9.3 Absolute Maximum Ratings

8.9.4 Pinning

8.10 TDA1308

8.10.1 General Description

The TDA1308; TDA1308A is an integrated class-AB stereo headphone driver contained in
an SO8, DIP8 or a TSSOP8 plastic package. The TDA1308AUK is available in an 8 bump
wafer level chip-size package (WLCSP8). The device is fabricated in a 1 mm
Complementary Metal Oxide Semiconductor (CMOS) process and has been primarily
developed for portable digital audio applications. The difference between the TDA1308
and the TDA1308A is that the TDA1308A can be used at low supply voltages.

8.10.2 Features

 Wide temperature range
 No switch ON/OFF clicks
 Excellent power supply ripple rejection
 Low power consumption
 Short-circuit resistant
 High performance
 High signal-to-noise ratio

 High slew rate
 Low distortion
 Large output voltage swing

8.10.3 Absolute Maximum Ratings

8.10.4 Pinning

8.11 LM358D

8.11.1 General Description

The LM158 series consists of two independent, high gain, internally frequency
compensated operational amplifiers which were designed specifically to operate from a
single power supply over a wide range of voltages. Operation from split power supplies is
also possible and the low power supply current drain is independent of the magnitude of
the power supply voltage. Application areas include transducer amplifiers, dc gain blocks
and all the conventional op amp circuits which now can be more easily implemented in
single power supply systems. For example, the LM158 series can be directly operated off
of the standard +5V power supply voltage which is used in digital systems and will easily
provide the required interface electronics without requiring the additional ±15V power
supplies. The LM358 and LM2904 are available in a chip sized package (8-Bump micro
SMD) using National’s micro SMD package technology.

8.11.2 Features

 Available in 8-Bump micro SMD chip sized package,
 Internally frequency compensated for unity gain
 Large dc voltage gain: 100 dB
 Wide bandwidth (unity gain): 1 MHz (temperature compensated)
 Wide power supply: Single supply: 3V to 32V or dual supplies: ±1.5V to ±16V

 Low supply current drain (500 µA)—essentially independent of supply voltage
 Low input offset voltage: 2 mV
 Input common-mode voltage range includes ground
 Differential input voltage range equal to the power supply voltage
 Large output voltage swing

8.11.3 Absolute Maximum Ratings

8.11.4 Pinning

8.12 74LCX244

8.12.1 General Description

The LCX244 contains eight non-inverting buffers with 3-STATE outputs. The device may
be employed as a memory address driver, clock driver and bus-oriented

transmitter/receiver. The LCX244 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal environment. The LCX244 is
fabricated with an advanced CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.

8.12.2 Features

 5V tolerant inputs and outputs
 2.3V to 3.6V VCC specifications provided
 6.5ns Tpd max. (VCC=3.3V), 10µA ICCmax.
 Power down high impedance inputs and outputs
 Supports live insertion/withdrawal
 ±24mA output drive (VCC=3.0V)
 Implements patented noise/EMI reduction circuitry
 Latch-up performance exceeds 500mA
 ESD performance:Human body model>2000V, Machine model>200V
 Leadless DQFN package

8.12.3 Absolute Maximum Ratings

8.12.4 Pinning

8.13 74LCX245

8.13.1 General Description

The LCX245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and
is intended for bus oriented applications. The device is designed for low voltage (2.5V and

3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R
input determines the direction of data flow through the device. The OE input disables both
the A and B ports by placing them in a high impedance state.
The LCX245 is fabricated with an advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipation.

8.13.2 Features

 5V tolerant inputs and outputs
 2.3V to 3.6V VCC specifications provided
 7.0ns tPDmax. (VCC=3.3V), 10µA ICCmax.
 Power down high impedance inputs and outputs
 Supports live insertion/withdrawal
 ±24mA output drive (VCC=3.0V)
 Implements patented noise/EMI reduction circuitry
 Latch-up performance exceeds 500mA
 ESD performance: Human body model>2000V, Machine model>200V
 Leadless DQFN package

8.13.3 Absolute Maximum Ratings

8.13.4 Pinning

8.14 FSA3157

8.14.1 General Description

The NC7SB3157 / FSA3157 is a high-performance, single- pole / double-throw (SPDT)
analog switch or 2:1 multiplexer/ de-multiplexer bus switch. The device is fabricated with
advanced sub-micron CMOS technology to achieve high-speed enable and disable times
and low on resistance. The break-beforemake select circuitry prevents disruption of
signals on the B Port due to both switches temporarily being enabled during select pin

switching. The device is specified to operate over the 1.65 to 5.5V VCC operating range.
The control input tolerates voltages up to 5.5V, independent of the VCC operating range.

8.14.2 Features

 Useful in both analog and digital applications
 Space-saving, SC70 6-lead surface mount package
 Ultra-small, MicroPak™ Pb-free leadless package
 Low On Resistance: <10Ω on typical at 3.3V VCC
 Broad VCC operating range: 1.65V to 5.5V
 Rail-to-rail signal handling
 Power-down, high-impedance control input
 Over-voltage tolerance of control input to 7.0V
 Break-before-make enable circuitry
 250 MHz, 3dB bandwidth

8.14.3 Absolute Maximum Ratings

8.14.4 Pinning

8.15 TSH343

8.15.1 General Description

The TSH343 is a triple single-supply video buffer featuring an internal gain of 6dB and a
large bandwidth of 280MHz. The main advantage of this circuit is that its input DC level
shifter allows for video signals on 75
tip of the video signal, while using a single 5V power supply with no input capacitor. The
DC level shifter is internally fixed and optimized to keep the output video signals between
low and high output rails in the best position for the greatest linearity. Chapter 4 of this
datasheet gives technical support when using the TSH343 as Y-Pb-Pr driver for video
DAC output on a video line (see TSH344 for RGB signals). The TSH343 is available in
the compact SO8 plastic package for optimum space-saving.

Ω video lines without damage to the synchronization

8.15.2 Features

 Bandwidth: 280MHz
 5V single-supply operation
 Internal input DC level shifter
 No input capacitor required
 Internal gain of 6dB for a matching between 3 channels
 AC or DC output-coupled
 Very low harmonic distortion
 Slew rate: 780V/μs
 Specified for 150Ω and 100Ω loads
 Tested on 5V power supply
 Data min. and max. are tested during production

8.15.3 Absolute Maximum Ratings

8.15.4 Pinning

8.16 MT48LC4M16A2TG8E

8.16.1 General Description

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
ollowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-A11 select the row).

8.16.2 Features

 PC66-, PC100- and PC133-compliant
 143 MHz, graphical 4 Meg x 16 option
 Fully synchronous; all signals registered on positive edge of system clock
 Internal pipelined operation; column address can be changed every clock cycle
 Internal banks for hiding row access/precharge
 Programmable burst lengths: 1, 2, 4, 8 or full page
 Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and AutO Refresh

Modes

 Self Refresh Modes: standard and low power
 64ms, 4,096-cycle refresh
 LVTTL-compatible inputs and outputs
 Single +3.3V ±0.3V power supply

8.16.3 Absolute Maximum Ratings

8.16.4 Pinning

8.17 MP1583

8.17.1 General Description

The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves
3A continuous output current over a wide input supply range with excellent load and line
regulation.
Current mode operation provides fast transient response and eases loop stabilization.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.
Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown mode
the regulator draws 20µA of supply current.
The MP1583 requires a minimum number of readily available external components to
complete a 3A step down DC to DC converter solution.

8.17.2 Features

 3A Output Current
 Programmable Soft-Start
 100mΩ Internal Power MOSFET Switch
 Stable with Low ESR Output Ceramic Capacitors
 Up to 95% Efficiency
 20µA Shutdown Mode
 Fixed 385KHz frequency
 Thermal Shutdown
 Cycle-by-Cycle Over Current Protection
 Wide 4.75 to 23V operating Input Range
 Output Adjustable From 1.22 to 21V
 Under Voltage Lockout
 Available in 8 pin SOIC Package
 3A Evaluation Board Available

8.17.3 Absolute Maximum Ratings

8.17.4 Pinning

8.18 MP2112

8.18.1 General Description

The MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter.
The device integrates a main switch and a synchronous rectifier for high efficiency without
an external Schottky diode. It is ideal for powering portable equipment that powered by a
single cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load current from a

2.5V to 6V input voltage. The output voltage can be regulated as low as 0.6V. The
MP2112 can also run at 100% duty cycle for low dropout applications.
The MP2112 is available in a space-saving 6-pin QFN package.

8.18.2 Features

 High Efficiency: Up to 95%
 1MHz Constant Switching Frequency
 1A Available Load Current
 2.5V to 6V Input Voltage Range
 Output Voltage as Low as 0.6V
 100% Duty Cycle in Dropout
 Current Mode Control
 Short Circuit Protection
 Thermal Fault Protection
 <0.1µA Shutdown Current
 Space Saving 3mm x 3mm QFN6 Package

8.18.3 Absolute Maximum Ratings

8.18.4 Pinning

8.19 MAX809LTR

8.19.1 General Description

The MAX809 and MAX810 are cost-effective system supervisor circuits designed to
monitor VCC in digital systems and provide a reset signal to the host processor when
necessary. No external components are required. The reset output is driven active within
~200msec of VCC falling through the reset voltage threshold. Reset is maintained active
for a timeout period which is trimmed by the factory after VCC rises above the reset
threshold. The MAX810 has an active-high RESET output while the MAX809 has an
active-low RESET output. Both devices are available in SOT-23 and SC-70 packages.
The MAX809/810 are optimized to reject fast transient glitches on the VCC line. Low
supply current of 0.5 A (VCC = 3.2 V) makes these devices suitable for battery powered
applications.

8.19.2 Features

 Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
 Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
 Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms,

100 ms, and 140 ms)

 RESET Output Guaranteed to VCC = 1.0 V.
 Low Supply Current
 Compatible with Hot Plug Applications
 VCC Transient Immunity
 No External Components
 Wide Operating Temperature: -40°C to 105°C
 Pb-Free Packages are Available

8.19.3 Absolute Maximum Ratings

8.19.4 Pinning

I2C_5V

I2C_TUN_DVB

74HCT4053

I2C & AGC

SWITCH

RF_AGC_DVB

RF_AGC_A

DVB-T COFDM

DEMOD.

STV0362

TS_T

TS_CI

RJ45

ETHERNET PHY

STE101P

BUFFERS
74LCX244

CI_BUFFERS

19 BLOCK DIAGRAMS

19.1 General Block Diagram

I2C

THOMSON

DTT75430

LG

TDTC-GXX1D

SAW

K9656M

SCART

ON/OFF

TRANSISTOR

SWITCH

I2C2/UART

RF AGC

ANALOG IF

K3958M

SAW

IF AGC

DIGITAL IF

DVB-C QAM

DEMOD.

STV0297

FSA3157

IF AGC

SWITCH

IF AGC_C

IF AGC_T

This Block does not exist,

unless PCB has enough

space

TS_C

USB HUB

USB2503

I2C_5V

DDC

TMDS DATA/CLK

MPEG4

DECODER

STi7101

I2C LEVEL

SHIFTER CIRCUIT

VIF_TUNER

SIF_TUNER

SC1 CVBS

SC1 RGB/FB

SC1 AUD_IN

SC1_CVBS_OUT

SC1_AUD_OUT

EDID

E2PROM

24C02

UART

SPDIF

I2C

2xFLASH

NOR 64Mbit (common)

NAND 2Gbit (w/ethernet)

4xDDR1

16Mx16

YPbPr

SCL/SDA

HDMI1

HDMI2

DDC

TMDS DATA/CLK

Y/C

SVHS

14.3181MHz
XTAL

RESET IC

MAX809LTR

CVBS

AUDIO L/R

FAV_Video/Audio

EEPROM

24C32

SCL/SDA2

MST6Wx7

YPbPr

AUDIO L/R

VGA/YPbPr

1MB Serial

Flash

LINE OUT

LINE OUT L/R

2MB SD

RAM

TS_CI

I/O PORTS

DVD Y/C_IN

LVDS

CONNECTOR

VCC SW

PANEL_ VCC_ ON/OFF

I/O PORTS

+3V3_STBY

+1V2_STBY

+2V6

+3V3

MAIN SPEAKER

OUT L/R

HP OUT

L/R

+5V

HP

AMPLIFIER

TDA1308T

PT2333 or MP1720

PANEL

SUPPLY

PANEL

PANEL_VCC

KEYBOARD

+12V

AUDIO AMP.

2 x 2.5W

POP NOISE

MUTE

CIRCUIT

DETACHED HP

BACKLIGHT_ON/OFF

BACKLIGHT_DIMMING

POWER_ON/OFF

StBy M TV/AV +P -P +V -V

I/O PORTS

LED1
LED2

DDC_WP

PANEL_VCC_ON/OFF

POWER ON/OFF

SCART1 PIN8

MPEG DECODER IRQ

PROTECTION

NVM_WP

Main Speaker 4R

4 Layer PCB

VESTEL ELECTRONICS R&D

GROUP

17MB37 BLOCK DIAGRAM

DATE:03.03.2009

DRAWN BY: SADIK ŞEHİT

EDID

E2PROM

24C02

HDMI_1

HDMI1

TMDS DATA/CLOCK 2

HDMI_2

PI5V330

RGB Switch

IDTV/YPbPr_SW

IDTV_YPbPr/SOY

YPbPr

DDC

DVD AUDIO_IN

IR

“”

VGA

DVD

Connector

IR ON/OFF

+24V

+12V

+5V_STBY

+5V

POWER

MODULE

+3V3_STBY

+3V3

DVD_SENSE

DVD Power

Connector

+12V

1 2 3 4 5 6 7 8

LG

AIF

A

DIF1

DIF2

IF_AGC

AS

NC

B2

SDA

SCL

TU102 TDTC-G101D

RF_AGC

B1

B

ANT_PWR

Samsung/Thomson

IFOUT-

IFOUT+

VT

IF_AGC

+5V

AIF_OUT

C

TU101

SDA

SCL

DTOS403LH172A

SAS

RF_AGC

BA

TUNER_PIN11

TUNER_PIN10

D

12

11

10

9

8

7

6

5

4

3

2

1

11

10

9

8

7

6

5

4

3

2

1

ANALOG_IF

TUNER_PIN11

TUNER_PIN10

IF_AGC_DVB_IN

ADDRESS_SEL_TUNER

5V_TUN

SDA_TUNER

SCL_TUNER

RF_AGC

33V_TUNER

ACT_ANT

21

21

1u

L116

C626

47p

33V_TUNER

IF_AGC_DVB_IN

5V_TUN

21

S308

SDA_TUNER

SCL_TUNER

RF_AGC

ADDRESS_SEL_TUNER

S104

ACT_ANT

C913

DIGITAL_IF-

1n
50V

C914

1n
50V

C1029

50V

2p2

DIGITAL_IF+

TUNER_PIN11

50V

TUNER_PIN10

ANALOG_IF

21

ACTIVE ANTENNA

OVER_CUR_DETECT

TP151

1

ACT_ANT

RF_AGC_A

SCL_TUNER

SDA_TUNER

5V_TUN

R502

10k

N.C.

R482

21

4R7
2R1

21

21

21

3

2

21

R504

10k

5V_TUN

21

10k

R501

1

T_AGC

R622

1k

BC848B

Q115

21

3

2

1

IF_AGC_DVB_IN

R503

10k

21

10V

100n

C136

ANT_CTRL

R505

1

2

10k

21

IF_AGC_DVB

TH101

21

330R

2 1

F234

Q102

FDN336P

C359

2

10u

1

10V

D121

1N4148

R111

12k

1

C448
47u

2

16V

This part must be placed near the tuner

R126

21

2

1

2

1

C586
47p
50V

C587
47p
50V

47R

R127

47R

SCL_TUN

21

SDA_TUN

5V_TUN

5V_TUN

TUNER SUPPLY OPSION

U123

LM1117

3 2

GND

OUTIN

VOUT

4

1

21

R408

1k

8V_VCC

F116
330R

21

1

C600
47u

2

16V

!!!En az 1.8 cm2 altta ve üstte soðutma alaný býrakýlmalý.

AGC AND I2C SWITCH PART

33V_TUNER

C532

1u
50V

SCL_TUN

SDA_TUN_DVB
SDA

R254

21

4k7

3

R595

2

1

22k

21

RF_AGC

10V

100n

C137

NEAR THE TUNER

1

2

SCL_TUN_DVB

SCL

RF_AGC_DVB

RF_AGC_A

U115

74HCT4053

1

2Y1

2

2Y0

3

3Y1

4

3Z

5

3Y0

6

E

7

VEE
GND S3

VCC

1Y1
1Y0

2Z
1Z

S1
S2

100n

5V_VCC

C128

21

10V

16
15
14
13
12
11
10

98

Q116

BC848B

330R

R460
330R

1K

2

1

5V_VCC

IDTV_SW

21

R624

2 1

S105

1k

SDA_TUN

2

1

C360
10u
10V

21

F159
330R

2

1

C134
100n
10V

21

C1158
220u

6V3

Near Tuner
supply pin

5V_TUN

A

5V_TUN

B

C

D

2

21

C129

100n

10V

C611
220u

1

6V3

21

C364

21

21

21

6k8

3k3

R473

R231

2

Q140

BSN20

Z101

IN1 OUT1

K9656M

IN2

OUT2

GND

3

Z102

IN1 OUT1

K3958M

IN2

2

GND

3

OUT2

41

5

SIFP

SIFM

VIFM

21

41

5

L104

2u2

N.C.

C546

21

C547

10n

16V

21

5V_TUN

6k8

R474

22k

R594

2 1

21

10n

16V

21

SIF_CTL

R483

1k2

2

OPTIONAL COIL

1u

1u

L101

2 1

2 1

21

3

Q144
BF799

1

21

10R

R384

L114

680R

2 1

R735

R125

47R

L111

1u

R1300

220R

21

1

2

C545

10n

16V

C520
47u
16V

21

R680

56R

21

21

R252

21

R623

4k7

1k

5V_TUN

E

ANALOG_IF

R38

220R

C135

2

100n

10V

1

R209
100k

BA782

2 1

D145

21

21

100k

R210

1

N.C.

2

3

WARNING!!! This part must be close to chip

C363

21

10u

10V

3V3_VCC

WARNING!!! Saw filter outputs must be close the chip

VIFP

C131

100n

5V_TUN

10V

10u

21

10V

21

C467

C132

21

100n

10V

21

3V3_STBY

3V3_VCC

F187
330R

F184
330R

C361

21

F186
330R

10u

10V

21

C510

2

100n

1

10V

4k7

R253

F185
330R

21

WARNING!!! This part must be close to chip

F

C636

2

220n

1

10V

10V

21

C130

21

10u

C597
220p
50V

10V

100n
SIFP

SIFM

VIFM

VIFP

21

C620

50V

U138

100p

MST6WB7GQ-3

62

AVDD_MPLL

63

VR27

64

VR12

65

AVDD_RXS

66

GND_RXS

67

SIFP

68

SIFM

69

VIFM

70

VIFP

71

GND_RXV

72

AVDD_RXV

73

TAGC

4

E

T_AGC

F

V-1 e gecerken yapilan updateler

Video SAW filitre cikislari caprazlandý

VESTEL

SCH NAME :
DRAWN BY :

ANALOG IF
SADIK SEHIT

PROJECT NAME :

17mb37

SHEET:

14-10-2009_09:09

87654321

OF:

A3

181

AX M

1 2 3 4 5 6 7 8

5V_VCC

21

1

TP101

C138

2

100n

1

10V

1

2

3

VGA_VSNC

VGA_HSNC

50V

VGA_B

VGA_G

VGA_R

D104

5

4

NUP4004M5

TP284

21

50V

27p

C441

F216

2 1

600R

F211
600R

TP297
TP298

F212
600R

TP296

21

D185

C5V6

PROJECT NAME :

A/V INTERFACE
SADIK SEHIT

50V

27p

2 1

C442

75R

R637

75R

R638

R639

75R

C440

2 1

27p

50V

21

3

D146

BAV70

VGA_DDC_5V

A

1

1

TP104

TP103

1

TP102

8

7

6

5 4

A0

VCC

U112

A1

WP

ST24LC21

A2

SCL

GNDSDA

1

2

3

1

TP105

B

VGA INPUT

10V

5V_VCC33k

21

R683

21

R682

RCA_Y

33k

21

TP294

21

21

21

RCA_PR

TP293

RCA_PB

C365

10u

TP292

50V
1n

2 1

C473

21

50V
1n

2 1

C474

SAV_AUD_R_IN

SAV_AUD_L_IN

SAV_CVBS

50V

2 1

C113

220p

C

D

E

F

OF:

A3

182

AX M

17mb37

SHEET:

14-10-2009_09:10

87654321

220p

C103

TP356

SC1_R

TP355
TP351

TP354

TP360

TP352

50V
1n

C477

21

C475

1n
50V

50V

2 1

21

21

21

D112

2 1

C5V6
C106

21

220p

50V

TP346

D111

2 1

C5V6

47R

2 1

R128

R255

4k7

SC1_CVBS_OUT

SC1_FB

SC1_PIN8

21

C140

2 1

100n

10V

F198

21

21

SC1_AUD_L_IN

R219

21

100R

C484

1n
50V

600R
F197

600R

SC1_AUD_R_IN

SC1_AUD_R_OUT

IPOD INTERFACE

TP15

POP_MUTE

IPOD_Y_IN

TP8

R120

21

10k

D115

2 1

75R

2 1

R644

75k

2 1

R641

50V

220p

2 1

C107

75R

2 1

R643

C5V6

D117

2 1

C5V6

D116

2 1

PROG_EN

TX/SDA_SC

SC1_G

RX/SCL_SC

C5V6

SC1_AUD_L_OUT

21

TP18

CN141

12V_IPOD

12V_IPOD 12V_IPOD

21

43

65

87

109

1211

SPDIF_OUT_COAXIAL

5V_VCC

S_VIDEO_C_IN

S-VIDEO IN

SPDIF OUTPUT INTERFACE

12V_IPOD

TP16

TP9

1413

TP11 TP5

IPOD_R IPOD_L

TP22

MAIN_R MAIN_L

C1059
100n

2 1

10V

IPOD_GPIO2

IPOD_GPIO3

C1060

2 1

100n

10V

RX/SCL TX/SDA

DVD_IPOD_SW

DVD_Y_IN

IPOD_Y_IN

SW_Y_IN

IPOD_C_IN

SW_C_IN

TP24

TP19

TP17

R1250

21

47R

TP14 TP13

C1049
100n

10V

21

R1261

1k

2 1

S293

R1326

S277

DVD_C_IN

S292

R1328

S278

R1325

R1327

75R

75R

75R

75R

1615

1817

TP21

2019

2221

2423

IPOD_GPIO1

TP20

2625

2827

1

IN

2

S1A

3

S2A

4

DA

5

S1B

6

S2B

7

DB

8

GND

R1251

47R

U194

PI5V330

VCC

S1D
S2D

S1C
S2C

21

C1044

100n

EN

DD

DC

3029

21

21

21

21

SW_R_IN

2 1

10V

16
15
14
13
12
11
10

9

C1061

F293
600R

AMP_MUTE

IPOD_C_IN

2 1

21

TP2

5V_VCC

F118
330R

50V

220p

R400

1k

C229

100n

10V

100n

C1139

27p

2 1

21

21

10V

21

50V

5V_VCC

TP287

21

A

20

321

4

NUP4004M5

D106

21

5

C105

50V

220p

SC1_CVBS_IN

TP361

19

18

75R

17

R640

21

16

15

14

50V

220p

2 1

C104

13

12

B

SC101

C

SCART1

F207

2 1

600R

D

JK111

4

RED

3

2

WHT

1

11

SCART LT1

10

9

8

7

6

5

4

3

2

1

TP348

TP334

TP347

21

C5V6

D183

C5V6

21

F196

F204
600R

D184

F205
600R

21

600R

21

R596

22k

D140

2 1

C15V

SC1_B

50V

220p

2 1

TP358

TP359

C108

TP363TP357
TP336

C478

R217
100R

TP362

50V
1n

C488

21

TP335

F195
600R

21

LINE_R_OUT

1n
50V

21

F194

21

600R

R213

21

100R

C489

21

1n

R216
100R

50V

21

LINE_L_OUT

21

AUDIO LINE OUT

E

JK104

BLK

RED

WHT

TP301

6

TP289

5

4

TP300

3

TP299

2
1

21

600R

F215

F

TP302

50V

220p

C115

S217

F208
600R

F209
600R

21

SPDIF_OUT_COAXIAL

21

C479

21

C480

1n
50V

1n
50V

21

21

YPBPR_AUD_R_IN

YPBPR_AUD_L_IN

COAXIAL SPDIF OUTPUT
YPBPR/PC LINE INPUT

21

21

C366

21

C5V6

C111

5V_SPDIF

IR_IN

21

10k

R1236

10k

R1235

10k

R1238

10k

R1239

10k

R1229

10k

R1228

10k

R1231

10k

R1230

D172

C5V1

10V

10u

D113

Q117

BC848B

S192

21

21

21

21

21

21

21

JK102

4 3

5

3

1

21

5V_VCC

5V_VCC

S281

5V_VCC

21

2

S282

C1007
100n
10V

5V_SPDIF

TP282

21

4k7

R752

C602

21

100n

10V

4k7

R242

S276

S294

SW_L_IN

21

C5V6

21

10k

R1234

C1143

1u
6V3

10k
R1237
C1144

1u

6V3

R1232

C1141

R1233

C1142

D114

50V

CN143

10k

1u
6V3

10k

1u
6V3

TP291TP290

50V

220p

2 1

220p

12

11

10

9

8

7

6

5

4

3

2

1

21

21

21

21

2 1

R464
100R

C116

C112

S_VIDEO_Y_IN

21

SPDIF_OUT

C1090
220n

C1121

25V

C15V

D194

F289

TP7

600R

TP6

F290

21

600R

F288

TP1

600R

F291

TP12

600R

F292

TP10

600R

R1254

47R

TP4

C1113

R1286

22k

50V
1n

C1119
R1288

22k

50V

C1118
R1287

C1120
R1284

50V
1n

1n

22k
50V

1n

22k

50V

21

21

21

21

21

21

21

21

TP382

21

1

25V

10u

21

21

C1135

27p

C1136

50V

21

21

27p

50V

C1140

27p

50V

21

C1137

21

C1138

27p

21

220p

50V

27p

50V

2 1

C1075

DVD_AUD_L_IN

IPOD_L

DVD_AUD_R_IN

IPOD_R

!

FS1

4A/24VDC

TP3

21

21

21

21

75R

R1329

2 1

15
14
13
12
11
10

9
8

VGA_DDC_5V

TP304

7
6
5
4

VGA CONNECTOR

3

TP288

2
1

CN118

DVD CONNECTION

D187

C18V

21

12V_VCC

R1240

21

R1285

22k

DVD_C_IN

DVD_Y_IN

DVD_IR

DVD_AUD_L_IN

DVD_SPDIF

10k

21

DVD_AUD_R_IN

R1267

4k7

C1050

100n

2 1

10V

321

4

321

NUP4004M5

3V3_VCC

DVD_SENSE

21

NUP4004M5

2k2

2k2

R712

2 1

21

C439

5

D101

21

4

2 1

27p

D102

5

R711

50V

C437

TP305

TP303

21

10k

R506

27p

TP306

JK101

RED

BLU

GRN

YPBPR INPUT

TP295

JK106

RED

WHT

YLW

TP283

SIDE AV INPUT

VESTEL

SCH NAME :
DRAWN BY :

R349

50V

21

R507

100R

C438

6
5

4
3

2
1

6
5

4
3

2
1

10k

R511

8

7

6

5 4

21

21

21

10k

R584
100R

R1

R2

R3

R4

27p

321

1 2 3 4 5 6 7 8

Place 75R termination resistors
close to Paulo reference GNDs

A

SW_C_IN 47R

SW_Y_IN

S_VIDEO_C_IN

B

SC1_CVBS_IN

SAV_CVBS

DVB_CVBS

C

75R

R651
R650

75R

R653

75R

R652

75R

R654

75R

R649

2 1

75R

R664

2 1

75R

R665

2 1

75R

21

21

21

21

21

SC1_B

SC1_G

R667

2 1

75R

R666

2 1

75R

SC1_R

D

SW_PB

R656

2 1

75R

SW_Y RCA_PB

R657

2 1

75R

R655

2 1

SW_PR RIN2P

75R

E

R659

2 1

VGA_B

VGA_G

F

VGA_R

75R

R658

2 1

75R

R660

2 1

75R

R143

R142

47R

R141

47R

R140

47R

R137

47R

R138

47R

R139

47R

R149

47R

R148

47R

R403
470R

R147

47R

R829

47R

R831

47R

R404
470R

R830

47R

47R

R145

R144

47R

47R

R146

R773
470R

U138

MST6WB7GQ-3

C150

100n

10V

C420

47n

16V

21

C425

47n
C416

47n

F119
330R

17

HSYNC1

18

VSYNC1

19

VCLAMP

20

REFP

21

REFM

21

22

BIN1P

23

SOGIN1

24

GIN1P

25

RIN1P

26

BIN0M

21

27

BIN0P

28

GIN0M

29

GIN0P

30

SOGIN0

31

RIN0P

32

AVDD_33_3

33

GND3

34

HSYNC0

35

VSYNC0

21

36

VSYNC2

37

BIN2P

38

SOGIN2

39

GIN2P

40

RIN2P

41

C1

42

Y1

43

C0

44

Y0

45

CVBS3

46

CVBS2

47

CVBS1

48

VCOM1

21

49

CVBS0

50

VCOM0

21

51

AVDD_33_4

52

CVBSOUT1

53

CVBSOUT0

54

GND4

AVDD_AU_1

2

AVDD_AU_2

LINE_IN_0L

LINE_IN_0R

LINE_IN_1L

LINE_IN_1R

LINE_IN_2L

LINE_IN_2R

LINE_IN_3L

LINE_IN_3R

LINE_IN_MONO

LINE_OUT_3L

LINE_OUT_3R

LINE_OUT_2L

LINE_OUT_2R

LINE_OUT_1L

LINE_OUT_1R

LINE_OUT_0L

LINE_OUT_0R

SCART VIDEO OUTPUT AMPLIFIERS

21

Q119

BC848B

21

21

R777

2

1

3

R402

75R

Q154
2N7002

BC858B

R646

75R

Q146

21

R753

4k7

1

3

2

R620
300R

21

VGA_HSNC

16V

47n

21

21

C0

C432

C434

21

47n

47n

21

C423

C422

21

47n

C424

21

47n

C612

21

16V
16V

16V

16V

Y0

21

BIN1P

SOGIN1

GIN1P

21

C1

Y1S_VIDEO_Y_IN

21

RIN1P

BIN0P

GIN0P

CVBS1

21

RIN0P

SOGIN0

21

AVDD_33

1n

50V

C433

21

47n
C435

21

47n

C421

21

47n

C418

21

47n

16V

16V

16V

16V

CVBS2

21

CVBS3

21

BIN0P

21

GIN0P

21

C152

100n

10V

21

VGA_VSNC

C151

100n

10V

R133

47R

R134

47R

C143

100n

SC1_FB

BIN2P

SOGIN2

GIN2P

RIN2P

21

21

21

SOGIN0

21

10V

C1

Y1

C0

C419

47n

16V

R687

33k

Y0

C417

21

47n

C428

21

47n

C426

21

47n

C490

21

C427

21

47n

C429

47n

C431

47n

C491

21

C430

47n

16V

16V

16V

1n
50V

16V

16V

16V

1n
50V

16V

RIN0P

21

BIN2P

21

GIN2P

21

SOGIN2

21

AVDD_33

CVBS0_OUT

21

BIN1P

21

GIN1P

21

SOGIN1

21

RIN1P

21

CVBS3

CVBS2

CVBS1

R859

10k

C144

2 1

100n

10V

R351
100R

5V_VCC

SC1_CVBS_OUT

21

GAIN_SW1

GND5

AUVRM

AUVRP

AUVAG

AUCOM

21

470R

3

1

100R

2 1

2

R221

21

R674

21

R467

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

39k

15k

C378

2 1

10u

10V

C148

2 1

100n

AVDD_AU

AVDD_AU

10V

10V

10u

2 1

C368

10V

10u

2 1

C369

C659

100n

16V

LINE_IN_0L

LINE_IN_0R

16V

10V

10u

2 1

C375

R739

C121

21

220p

50V

R678

82k

21

R692

2 1

33k

21

1

OUT1

2

IN1-

3

V+

IN1+

VSS IN2+

LINE_IN_1L

LINE_IN_1R

C149

S106

21

LINE_IN_2L

100n

10V

21

LINE_IN_2R

LINE_IN_3L

LINE_IN_3R LINE_IN_2L

R686

21

33k

SC1_AUD_R_OUT

C649

SC_1_R 20k

100n

U118

TL062

VDD

OUT2

IN2-

C631

100n

16V

F217

2 1

600R

8

7

6

54

V+

R691

C120

220p

50V

R677

82k

33k

21

8V_VCC

21

21

10V

10u

2 1

C374

R738

20k

SC1_AUD_L_OUT

C650

21

100n

16V

SC1_L

DSP_CH2_L

DSP_CH2_R

DSP_CH4_L

DSP_CH4_R

DSP_CH1_L

LINE_R_OUT

DSP_CH1_R

DSP_CH3_L

DSP_CH3_R

AVDD_AU

Pin79

C142

100n

10V

2

1

Pin74

10V

100n

C145

2

1

21

330R

F120

AVDD_AU DECOUPLING CAPACITORS

3V3_VCC

POP_MUTE

R751

3k3

LINE_OUT_R

V+

C646
100n
16V

AUDIO PREAMPLIFIERS
Place close to Paulo

C666
1u
16V

CVBS0_OUT

R522

10k

C367

21

100n

2 1

21

C662

16V

10u

10V

R690

10V

10u

2 1

C372

3

BC848B

2

Q121

1

R737

20k

33k

R685

21

33k

R684

R155

47R
50V

220p

21

C119
R676

82k

21

V+

21

8V_VCC

2 1

33k

21

8V_VCC

21

1

OUT1

U117

2

IN1-

TL062

3

IN1+

VSS IN2+

DSP_CH4_L

C630

100n

16V

VDD

OUT2

IN2-

DVB_PR

DVB_Y

R662

75R

DSP_CH2_R

F219
600R

R689

33k

8

7

6

54

21

21

C443

2 1

27p

50V

R661

75R

SW_PR

C444

2 1

27p

50V

R224
100R

21

V+

R153

47R

50V

220p

C118
R675

82k

DVB/YPBPR_SW

21

R228
100R

R229
100R

21

10V

10u

2 1

21

C371

BC848B

21

Q120

21

R736

20k

RCA_PR

RCA_Y

21

3

1

100n

2

C663

16V

R627

1k

LINE_L_OUT

R521

2 1

10k

3k3

2 1

R750

LINE_OUT_L

21

1
2
3
4
5
6
7
8

U129

PI5V330

IN
S1A
S2A
DA
S1B
S2B
DB
GND

SW_Y

21

C555

21

C554

2 1

2 1

10n

10n

C550

2 1

10n

16V

16V

16V

22k

R419

22k

R420

22k

R415

HP_LDSP_CH2_L

21

HP_R

21

LINE_OUT_L

21

Place close to Paulo

R225

DSP_CH4_R

AUDIO OUTPUT FILTERS

100R

21

C551

2 1

10n

16V

LINE_OUT_R 100R

22k

21

R416

VESTEL

SCH NAME :
DRAWN BY :

AUDIO INPUT VOLTAGE DIVISION AND DC BLOCK
Place close to PauloVIDEO TERMINATIONS AND DIFFERENTIAL TRACING

LINE_IN_0L

LINE_IN_0R

LINE_IN_1L

LINE_IN_1R

LINE_IN_2R

LINE_IN_3L

POP_MUTE

LINE_IN_3R

100n

16

VCC

15

S1D
S2D

S1C
S2C

EN

DD

DC

C1006

14
13
12
11
10

9

DSP_CH1_L

DSP_CH1_R

<DRAWING NAME HERE>
<YOUR NAME HERE>

C656

100n

16V

R513

21

10k

C655

100n

16V

R514

21

10k

C645

100n

16V

R515

21

10k

C644

100n

16V

R516

21

10k

C642

100n

16V

R517

21

10k

C643

100n

16V

R518

21

10k

C660

100n

16V

R519

21

10k

C661

100n

16V

R520

21

10k

10V

2 1

C147

10u

D167

F151
330R

10V

R227
100R

R226
100R

DSP_CH3_L

DSP_CH3_R

PROJECT NAME :

R607

21

22k

C493

21

1n

R606

50V

22k

21

C492

21

1n

R605

50V

22k

21

C495

21

1n

R603

50V

22k

21

C494

21

1n

R601

50V

22k

21

C497

21

1n

R600

50V

22k

21

C496

21

1n

R599

50V

22k

21

C498

21

1n

R598

50V

22k

21

C499

21

1n
50V

DVB/YPBPR SWITCH

C5V1

21

5V_VCC

DVB_PB

R663

2 1

75R

SW_PB

21

16V

2 1

C553

10n

21

16V

2 1

10n

C552

R223

21

100R

2 1

C549

R222

21

2 1

C548

17mb37

14-10-2009_09:10

SC1_AUD_L_IN

SC1_AUD_R_IN

SW_L_IN

SW_R_IN

YPBPR_AUD_L_IN

YPBPR_AUD_R_IN

SAV_AUD_L_IN

SAV_AUD_R_IN

27p

21

C445

R418

22k

22k

R417

16V

10n

16V

10n

SHEET:

87654321

MAIN_L

21

MAIN_R

21

SC1_L

22k

R414

SC_1_R

22k

R413

OF:

21

21

A3

A

B

C

D

E

F

183

AX M

1 2 3 4 5 6 7 8

A

CN121

21
20

1
2
3
4
5
6
7
8

9
10
11
12

HDMI1

13
14

B

15
16
17
18
19

CEC

21

R491

47k

R492

C

D

CN122

21
20

1
2
3
4
5
6

E

F

7
8

HDMI2

9
10
11
12
13
14
15
16
17
18
19

CEC

HDMIA_5V

21

1k

R632

21

R493

47k

21

47k

HDMI Receiver In_B

R386

21

10R

R388

21

10R

2 1

R389

21

10R

R391

21

10R

R392

21

10R

10R

21

R396

21

47k

HDMI Receiver In_A

R10
10R

21

R15
10R

21

R13
10R

21

R18
10R

21

R12
10R

21

R14
10R

21

R9

10R

21

R8

10R

21

R17
10R

21

R16
10R

21

R11
10R

21

R494

R385

10R

10R

R387

10R

R394

10R

R390

10R

R393

21

HDMIB_2-

21

HDMIB_1+

HDMIB_1­HDMIB_0+

HDMIB_0-

21

HDMIB_C+

HDMIB_C-

HDMIB_SCL

21

HDMIB_SDA

HDMIB_5V
HDMIB_HPD

HDMIA_2+

HDMIA_2-

HDMIA_1+

HDMIA_1-

HDMIA_0+

HDMIA_0-

HDMIA_C+

HDMIA_C-

HDMIA_SCL

HDMIA_SDA

HDMIA_HPD

HDMIB_2+

1

2

3

4

TP134

A0

U110

A1

24LC02

A2

VSS

1

A0

2

A1

24LC02

3

A2

4

VSS

VCC

SCL

SDA

TP411

U193

5V_VCC

1

WP

5V_VCC

VCC

WP

SCL

SDA

BAV70

D147

2 1

3

C153

2

100n

1

1

TP133

TP412

1

1

TP410

HDMIB_SCL

HDMIB_SDA

BAV70

D193

2 1

HDMIA_SCL

HDMIA_SDA

1

TP409

10V

3

2

1

C1069
100n
10V

TP106

8

1

7

6

5

1

TP132

1

8

7

6

5

21

4k7

HDMIB_5V

R257

HDMI_WP1

21

4k7

R1282

VDDP

AVDD_33

HDMIA_5V

HDMI_WP2

2

1

100n
10V

1

100n
10V

C156

C155

2

Pin6 Pin13 Pin285

C159

C158

2

F124
330R

2

1

21

100n
10V

2

1

100n

1

10V

C173
100n
10V

HDMIA_C-

HDMIA_C+

HDMIA_0-

HDMIA_0+

AVDD_33

HDMIA_HPD

Q179

BC848B

HDMIA_5V

21

1k

R1263

3

1

R1264

2

21

1k

AVDD_33

4k7

R1281

2 1

HDMIA_2-

HDMIA_2+

HDMIA_1-

HDMIA_1+

R412
390R

HDMIA_SDA

Pin236Pin216Pin196

C157

2

100n

1

10V

3V3_HDMI

HDMIB_C-

C154

100n

10V

HDMIA_SCL

21

VDDC

HDMIB_C+

2

1

C160
100n
10V

HDMIB_0-

AVDD_33

HDMIB_0+

HDMIB_1-

HDMIB_1+

AVDD_USB3V3_VCC

HDMIB_HPD

BC848B

Q123

HDMIB_5V

21

1k

R629

3

1

2

HDMIB_2-

HDMIB_2+

R630

21

1k

R258

2 1

HDMIB_SDA

HDMIB_SCL

4k7

1

RXACKN

2

RXACKP

3

GND1

4

RXA0N

5

RXA0P

6

AVDD_33_1

7

RXA1N

8

RXA1P

9

GND2

10

RXA2N

11

RXA2P

12

HPLUGA

13

AVDD_33_2

21

14

REXT

15

DDCDA_SDA

16

DDCDA_SCL

282

VDDC5

283

RXBCKN

284

RXBCKP

285

AVDD_33_5

286

RXB0N

287

RXB0P

288

GND

289

RXB1N

290

RXB1P

291

GND18

292

RXB2N

293

RXB2P

294

HPLUGB

295

DDCDB_SDA

296

DDCDB_SCL

3V3_HDMI

U138

MST6WB7GQ-3

USB20_REXT

1

AVDD_USB

USB20_DM

USB20_DP

USB_VBUS

USB_DM

USB_DP

USB_CID

GND11

VDDP2

GND12

VDDP3

ICLK

DI[0]

DI[1]

DI[2]

DI[3]

VDDP5

DI[4]

DI[5]

DI[6]

DI[7]

DI[8]

DI[9]

191

192

193

194

195

196

197

216

217

218

219

220

231

232

233

234

235

236

237

238

239

240

241

242

R119

21

910R

AVDD_USB

USB_DM_A

USB_DP_A

VDDP

VDDP

I2S_WS_DVB

I2S_CLK_DVB

I2S_DATA_DVB

VDDP

A

B

C

D

E

F

VESTEL

SCH NAME :
DRAWN BY :

HDMI&USB
SADIK SEHIT

PROJECT NAME :

17mb37

14-10-2009_09:10

87654321

SHEET:

OF:

A3

184

AX M

1 2 3 4 5 6 7 8

R277

CN106

1

10

5V_STBY

LED1

LED2

3V3_STBY

3V3_STBY

9

8

7

6

5

4

3

2

2 1

4k7

R276

2 1

4k7

56

57

A

D130

2 1

C5V6

D149

2 1

C5V6

LED&VFD

5

4

3

2

CN119

1

S119

S118

21

R43

220R

B

R421

10k

3

2

21

1

Q130
BC848B

21

10k

R528

BC858B

LED2

3V3_STBY

5V_STBY

S117

S125

21

21

F225

21

600R

3

2

Q148

1

21

R382

220R

3

Q149

1

220R

KEYBOARD & TOUCHPAD

C

DVD_IR

BC848B

IR_IN

D

1

2

21

47k

R1330

Q178

R1269

2 1

3

4k7

21

N.C.

S299

4k7

R1268

2 1

3V3_VCC

BC858B

21

R381

21

21

IR_IN

2

3V3_STBY

5V_STBY

21

10k

R531

C608

27p

50V

Q131

BC848B

R552

2 1

2 1

F229
600R

2 1

2 1

21

3

2

1

MECH_SWITCH

R527

10k

21

R526

10k

D148

C5V6

F228
600R

F230
600R

R422

10k

3V3_STBY10k

21

VFD_CSB

3V3_STBY

VFD_CLK_STBY

21

3V3_STBY

21

LED1

MECH_ONBOARD

D150

21

C5V6

F231

21

600R

VFD_DATA_STBY

STBY_ON/OFF_NOT

VDDP VDDC

C598

21

50V

CN114

C5V6

1

220p

D152

2 1

3

2

3V3_STBY

R608

22k

C177
100n
10V

2

1

2

C176
100n
10V

2

1

C175
100n
10V

2 1

2

1

PIN272 PIN226PIN108 PIN110

KEYBOARD_ONBOARD

R167

47R

21

F188
600R

F280

C1037

4

4u7

C1036

100n

VFD_CLK_STBY
VFD_DATA_STBY

21

4k7

R265

3

Q125
BC848B

1

C174

2

100n

1

10V

21

3V3_STBY

1

TP383

STBY_ON/OFF

C178

2

100n

1

10V

KEYBOARD_STBY

TK_SUPPLY

DVD_IR_ON/OFF

6

5

4

3

2

1

CN130

CN142

MECH_ONBOARD

21

43

KEYBOARD_ONBOARD

TK_SUPPLY

C447

21

27p

50V

X104

C446

21

27p

50V

DVB/YPBPR_SW

IDTV_SW

PROTECT

NVM_WP

VFD_CLK_STBY

HDMI_WP2

HDMI_WP1

VFD_DATA_STBY

HDMIB_5V

HDMIA_5V

PROTECT_PANEL

ANT_CTRL

VFD_CSB

DVD_IPOD_SW

IPOD_GPIO3

IPOD_GPIO2

21

21

1M

R110

14.31818MHZ

DVB_IRQ

3V3_STBY

3V3_STBY

3V3_VCC

3V3_STBY

3V3_STBY

SIF_CTL

STBY_ON/OFF_NOT

R748

21

47R

3V3_VCC

DVB_RESET

GAIN_SW1

3V3_VCC

3V3_VCC

3V3_VCC

3V3_VCC

DVD_IR_ON/OFF

R840

4k7

R858

3V3_STBY

3V3_VCC

R1266

2 1

4k7

2 1

2 1

4k7

R1277

3V3_STBY

R274

4k7

2 1

2 1

R269

2 1

4k7

R270

2 1

4k7

4k7

2 1

R271

2 1

2 1

R1278

4k7

R288

4k7

R268

4k7

R283

4k7

R264

4k7

21

R395

1k

USB_OCD

S193

R757

4k7

5V_TOLERANT

5V_TOLERANT

21

R8574k7

R267

21

2 1

4k7

PROG_EN

21

VDDP

VDDC

5V_TOLERANT

1k

5V_TOLERANT

58

59

60

61

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

149

150

151

152

153

154

155

156

157

158

159

U138

MST6WB7GQ-3

GPIOL[0] SAR0

GPIOL[1]

GPIOL[2]

GPIOL[3]

GPIOL[4]

XOUT

XIN

GPIOD[0]

GPIOD[1]

GPIOD[2]

GPIOD[3]

GPIOD[4]

GPIOD[5]

GPIOD[6]

GPIOD[7]

GPIOD[8]

GPIOD[9]

VDDP1

GND6

VDDC1

GPIOD[10]

GPIOD[11]

GPIOD[12]

GPIOD[13]

GPIOD[14]

GPIOD[15]

GPIOD[16]

GPIOD[17]

GPIOR[0]

GPIOR[1]

GPIOR[2]

GPIOR[3]

GPIOR[4]

3

SAR1

SAR2

SAR3

PWM0

PWM1

DDCR_SDA

DDCR_SCL

DDCA_SDA

DDCA_SCL

INT

IRIN

GPIOB[0]

GPIOB[1]

PWM2

PWM3

GND14

VDDP4

GPIOT[0]

GPIOT[1]

GPIOT[2]

GPIOT[3]

HWRESET

VDDP7

GND17

GPIOE[3]

GPIOE[2]

GPIOE[1]

GPIOE[0]

GPIOM[0]

GPIOM[1]

GPIOM[2]

GPIOM[3]

GPIOR[5]

GPIOR[6]

GPIOR[7]

GPIOR[8]

GPIOR[9]

GPIOR[10]

20455

205

206

207

208

209

210

211

212

213

214

215

221

222

223

224

225

226

227

228

229

230

243

272

273

274

275

276

277

278

279

280

281

PUSH V+ AND V- AT THE SAME TIME FOR MENU

N.C.

E

5V_STBY

RX/SCL

TX/SDA

S120

R164

47R

R163

47R

DEBUG SOCKET

PROG_EN

5V_STBY

CN145

21

1

2

21

3

21

4

3

SW5

1

21

R1332

4

2

270R

SW4

R1331

3

1

21

470R

4

3

4

SW1

2

1

2

21

1k2

R1289

3

SW6

1

21

R1333

VOL-TV/AVVOL+P-P+

4

2

2k7

3

SW3

1

21

R1305

3k9

STBY

4

3

4

SW2

2

1

2

5k1

R1292

C180

21

4k7

1

R280

2

Q128

BC848B

3

R282

2 1

4k7

F

4k7

R281

2 1

RX/SCL_SC

RX/SCL

UART_RXD

U127

M74HC4052

1

2Y0

2

2Y2

3

2Z

4

2Y3

5

2Y1

6

E

7

VEE
GND S1

VCC
1Y2
1Y1

1Y0
1Y3

16
15
14
13

1Z

12
11
10

S0

98

21

100n

10V

TX/SDA
TX/SDA_SC
UART_TXD

4k7

R284

5V_STBY

SW_UPDATE_SELECT

21

5V_STBY

PROG_EN

0

SW_UPDATE_SELECT

0
1

HC4052 DISABLE
HC4052 ENABLE1

DVB_SW_UPDATE
ANALOG_SW_UPDATE

KEYBOARD_ONBOARD

PDP_IRQ

BACKLIGHT_DIM

21

S196

S195

S194

21

21

MEGA_DCR

R232

4k7

C529

220p

50V

R1345

2

21

4k7

21

2

1

1

C1163
100n
10V

2

21

R745

3

1

1k

Q126
BC848B

S18

S121

21

3V3_VCC

21

5V_VCC

21

S123

21

1

Q147

2

BC858B

3

R352

21

100R

3

1

Q127
BC848B

R353
100R

R354
100R
R355
100R

21

21

21

21

10V

10u

C383

21

2

R233

4k7

C530

220p

50V

R234

4k7

C531

220p

50V

21

21

N.C.

4k7

2 1

R293

3V3_STBY

KEYBOARD_STBY

SC1_PIN8

DVD_SENSE

For Internal CPU Selection

R524

2 1

10k

R1280

2 1

4k7

For Internal CPU Selection

3V3_STBY

4k7

2 1

R287

4k7

2 1

R286

4k7

2 1

R289

4k7

2 1

R290

4k7

2 1

R294

4k7

2 1

R278

VDDP

OPTION2

R291

R161

47R

R162

47R

2 1

4k7

21

21

R292

2 1

4k7

VDDP

R1248

21

47R

4k7

R31
47R

21

21

HP_DETECT

R261

2 1

4k7

R262

2 1

4k7

USB_ENA_A

5V_VCC

AMP_SHDN

47R

R964

R1036

2 1

DIMMING

VESTEL

SCH NAME :
DRAWN BY :

R742

2 1

20k

4k7

2 1

R279

3V3_STBY

3V3_STBY

3V3_STBY

3V3_STBY

3V3_STBY

3V3_STBY

AMP_MUTE

3V3_VCC

3V3_VCC

3V3_STBY

3V3_STBY

1
2
3

1

CONTROLLER
SADIK SEHIT

OVER_CUR_DETECT

BACKLIGHT_DIM

3V3_STBY

3V3_STBY

SDA_NVM

SCL_NVM

U103

24C32

E0

VCC

E1

WC

E2

SCL

VSS SDA

TP111

TP350
TP353
TP307

PROJECT NAME :

SDA

SCL

TX/SDA

RX/SCL

IR_IN

SW_UPDATE_SELECT

R1283

21

22k

4k7

2 1

R1279

DVB_RXD

DVB_TXD

R356

2 1

100R

3V3_STBY

C181

2 1

100n

10V

8
7
6
54

1

1

1

1

PROG_EN
SW_UPDATE_SELECT
RESET_7101

A

C5V6

D174

B

IPOD_GPIO1

10V

1

100k

R724

100n

2

2 1

C182

C

1

TP159

R1265

1k

Reset IC supplyi 3V3 stbyden alindi

21

GND RST

VCC
3

100n

21

D155

MAX810

MAX809LTR
U130

10V

21

C183

1N4148

C1129
22u
25V

D

3V3_STBY

NVM_WP
SCL_NVM
SDA_NVM

TP110
TP109
TP108
TP112

E

F

OF:

A3

185

AX M

17mb37-1

SHEET:

14-10-2009_16:25

87654321

A

SCZ

3V3_STBY

SERIAL FLASH

B

MEMORY

C

D

E

1 2 3 4 5 6 7 8

U138

SDO

TP113

TP1151TP114

1

1

21

100R

R365

MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]

MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]

MADR[0]
MADR[1]
MADR[2]
MADR[3]

TP119

1

U132

MX25L512

1

CS#

2

SO

3

WP#
GND SI

LDM

WEZ

CASZ

RASZ

BADR[0]

BADR[1]

VCC

HOLD#

SCLK

3
2
1

100R

R1310

3
2
1

100R

R1312

1
2
3

R4
R3
R2
R1

R4
R3
R2
R1

R1315

100R

R1
R2
R3
R4

8
7
6
54

54
6
7
8

54
6
7
8

R1324

100R

R1338

22R

R1337

22R

R1336

22R

R1335

22R

R1334

22R

8
7
6
54

TP118

TP117

1

1

VDD_DMC

VDD_DMQ

VDD_DMQ

VDD_DMC

21

21

21

21

21

21

VDD_DMC

TP116

1

C184

2

100n

1

4k7

R761

2 1

10V

SDI

1

TP160

8MB SDRAM

MT48LC4M16A2TG8E

1

VDD1

2

DQ0

3

VDDQ1

4

DQ1

5

DQ2

6

VSSQ1

7

DQ3

8

DQ4

9

VDDQ2

10

DQ5

11

DQ6

12

VSSQ2

13

DQ7

14

VDD2

15

DQML

16

WE#

17

CAS#

18

RAS#

19

CS#

20

BA0

21

BA1

22

A10

23

A0

24

A1

25

A2

26

A3

27

VDD3

D169

C5V1

SCK

C605

2

10u

1

10V

U195

F150
330R

VSS3

DQ15

VSSQ4

DQ14

DQ13

VDDQ4

DQ12

DQ11

VSSQ3

DQ10

DQ9

VDDQ3

DQ8

VSS2

NC2

DQMH

CLK

CKE

NC1

A11

VSS1

MST6WB7GQ-3

DVB_SPDIF

SPDIF_OUT

3V3_VCC

3V3_VCC

R296

4k7

R295

4k7

DVD_SPDIF

21

21

VDDM

S220
R357

100R

BADR1

BADR0

RASZ

VDDC

CASZ

21

3V3_STBY

F125
330R

VDDC

PIN129 PIN203

2

1

21

C194
100n
10V

2

1

C469
10u
10V

2

1

C201
100n
10V

2

1

C202
100n
10V

2

1

C200
100n
10V

2

1

100n
10V

2

1

100n
10V

C198

C199

PIN131 PIN147 PIN162 PIN168 PIN173 PIN179 PIN184

C195

2

100n

1

10V

2

1

100n
10V

1

100n
10V

C196

C197

2

BACKLIGHT_ON/OFF

BC848B

VDDM3V3_VCC

Q157

BKL_ON/OFF

PANEL_VCC_ON/OFF

S216
R795

10k

R794

10k

C1145

BKL_ON/OFF

3V3_VCC

BKL_ON/OFF

6V3

1u

WEZ

MADR[11]

MADR[10]

MADR[9]

54

53

52

51

50

49

VDD_DMQ

48

3
2
1

100R

R1309

R4
R3
R2
R1

54
6
7
8

MDATA[15]
MDATA[14]
MDATA[13]
MDATA[12]

47

46

45

44

43

VDD_DMQ

3
2
1

R1311

R4
R3
R2
R1

100R

54
6
7
8

MDATA[11]
MDATA[10]
MDATA[9]
MDATA[8]

3V3_VCC

42

MADR[8]

MADR[7]

MADR[6]

MADR[5]

MADR[4]

MADR[3]

MADR[2]

MADR[1]

MADR[0]

VDDM

F157
330R

21

2

1

41

40

R1323

100R

MCLK

21

R1314

1
2
3

R1313

1
2
3

100R

R1
R2
R3
R4

100R

R1
R2
R3
R4

UDM

Place MCLKE Clock resistor close to MSTAR Pin

R1322

21

MCLKE100R

8

MADR[11]

7

MADR[10]

6

MADR[9]

54

MADR[8]

8

MADR[7]

7

MADR[6]

6

MADR[5]

54

MADR[4]

VDDM

F287

60R

21

1

C1077
220u

2

6V3

PIN1 PIN14

C1066

2

2

100n

1

1

10V

C1067
100n
10V

PIN27

2

1

C1068
100n
10V

VDD_DMC

39

38

37

36

35

34

A9

33

A8

32

A7

31

A6

30

A5

29

A4

28

AD[0] DQM0

120

AD[1]

121

AD[2]

122

AD[3]

123

WRZ

124

RDZ

21

125

ALE

126

BADR[1]

127

BADR[0]

128

RASZ

129

VDDC2

130

GND7

131

AVDD_MI_1

132

CASZ

133

WEZ

134

WADR[11]

135

WADR[10]

136

WADR[9]

137

WADR[8]

138

WADR[7]

139

WADR[6]

140

WADR[5]

141

WADR[4]

142

WADR[3]

143

WADR[2]

144

WADR[1]

145

WADR[0]

146

GND8

147

AVDD_MI_2

148

AVDD_MIPLL

C213
100n
10V

5

AVDD_MI_3

MDATA[0]

MDATA[1]

MDATA[2]

MDATA[3]

AVDD_MI_4

MDATA[4]

MDATA[5]

MDATA[6]

MDATA[7]

AVDD_MI_5

MDATA[8]

MDATA[9]

MDATA[10]

MDATA[11]

AVDD_MI_6

MDATA[12]

MDATA[13]

MDATA[14]

MDATA[15]

AVDD_MI_7

SPI_SCK

SPI_SDI

SPI_SCZ

SPI_SDO

DQS0

GND9

GND10

DQS1

DQM1

MCLKZ

MCLK

MCLKE

MVREF

GND13

VDDC3

160119

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

198

199

200

201

202

203

LDM

VDDM

MDATA[0]

MDATA[1]

MDATA[2]

MDATA[3]

VDDM

MDATA[4]

MDATA[5]

MDATA[6]

MDATA[7]

VDDM

MDATA[8]

MDATA[9]

MDATA[10]

MDATA[11]

VDDM

MDATA[12]

MDATA[13]

MDATA[14]

MDATA[15]

VDDM

UDM

R499

MCLKE

R1316

100R

8

R1

7

R2

6

R3

5 4

R4

VDDC

21

1

2

3

2

1

MCLK100R

SCK

SDI

SCZ

SDO

C1112
1n
50V

21

R536

10k

21

R535

VDDM

10k

2

1

C501
1n
50V

2

1

A

B

C

D

C193
100n
10V

E

1

2

C1076
220u
6V3

PIN3

2

1

C1065
100n
10V

2

1

C1063
100n
10V

F286

VDDM

C1045

2

100n

1

F

10V

21

60R

2

1

C1062
100n
10V

PIN49PIN43PIN9

2

1

C1064
100n
10V

VDD_DMQ

F

WARNING!!!DON'T USE VIA FOR MCLK AND DATA SIGNALS

VESTEL

SCH NAME :
DRAWN BY :

MEMORY INTERFACE
ÖNDER GENÇ

PROJECT NAME :

17mb37

SHEET:

14-10-2009_09:10

87654321

OF:

A3

186

AX M

1 2 3 4 5 6 7 8

S128

S127

S126

2

21

21

21

16V

100u

2 1

C453

BC858B

R542

2 1

10k

Q150

1N4148

2 1

21

10k

R546

1

3

D124

2

21

R729

21

10k

100k

R1241

1N4148

2 1

21

10k

R541

A

D127

B

HEADPHONE AMPLIFIER

HP_DETECT

POP NOISE CIRCUIT

12V_VCC

5V_VCC

3V3_VCC

A

C503

1n
50V

C632

HP_R

C537

2

2n2

50V

220n

10V

1

B

C541

2 1

21

R423

4k7

100u

16V

21

21

R237

C665

1u
16V

20k

R211
100k

C122

21

21

50V

220p

1

OUTA

U128

2

INAN

TDA1308T

3

INAP

VSS INBP

VDD

OUTB

INBN

21

8

100k

R212

7

6

R238

54

1N4148

2 1

D126

C386

2

10u

1

10V

21

21

20k

C123

C540

100u

50V

220p

4k7

R424

16V

1N4148

2 1

D125

C502

21

C633

21

220n

10V

50V
1n

R800

1

2

22R

2

1

C538
2n2
50V

MUTE_HP_R

8V_VCC

R801

22R

HP_L

50V

2n2

C625

2

1

F191

MUTE_HP_L

C624

9

2

1

2n2
50V

6

8

5

7

4

3

JK110

2
1

5k1

3k3

R1291

R1290

VDD_AUDIO

5V_VDD_AUDIO

21

21

15k

15k

R123

R1223

21

S296

HP_DETECT

AMP_EN

21

600R

8V_VCC

AMP_MUTE

R722

10k

3

BC848B

2

21

Q133

1

21

3k9

R236

C668
100n
50V

BC848B

Q132

3

1

MUTE_HP_R

2.5 WATT OPTION

GNDA

INP

A1

A2

A3

MAIN_L_AUDIO

C

L_AUDIO_N

C4

10V

2u2

50V

R39

150k

D

AUDIO INPUTS

5V_VDD_AUDIO

3

BC848B

S12

2

Q2

R20

1

100R

16V

1u

R1320

150k

15K

C1131

MAIN_L_AUDIO

MAIN_L

E

5V_VDD_AUDIO

3

BC848B

S11

2

Q1

R19

1

100R

16V

1u

C1130

R1318

150k

15K

MAIN_R_AUDIO

MAIN_R

F

L2

47u

F7

60R

1n

C1117

5V_VDD_AUDIO

VDDA

OUTN

B1

L_OUT_N

2

1

PT2333U192

GNDB

VDD1

B2

B3

C1056

2

100n

1

10V

R1319

C1042
10u
10V

5V_VDD_AUDIO

C1

INN

15K

150k

C1132
1u
16V

SDB

C2

AMP_EN

OUTP

C3

L_OUT_P

AMP_EN

60R

F4

L3

47u

50V

C1115

R24
10k

5V_VDD_AUDIO

1n

5V_VCC

150k

L_AUDIO_P

C5

10V

R41

2u2

AMP_SHDN

R27

10k
R25
10k

S14

16V

1u

C11

S15

MAIN_R_AUDIO

MAIN_R_AUDIO

R_AUDIO_N

C3

16V

1u

C10

C9
1u
16V

10V

2u2

R40

150k

MAIN_L_AUDIO

MUTE

9

SHDN

10

REGEN

11

COM

12

AGND1

13

AGND2

14

REG

15

VS

16

INP

A1

A2

L1

47u

60R

F6

1n

50V

C1116

5V_VDD_AUDIO

8

NC2

NC3

17

5V_VDD_AUDIO

VDDA

OUTN

GNDA

A3

B1

R_OUT_N

2

1

R30

20k

7

6

FBL

INL

NC1

MAX9736B

U1

MOD

FBR

INR

18

19

R29

20k

10k

R26

C1043
10u
10V

R28

5

20

S13

PT2333U191

VDD1

B2

C1057

2

100n

1

10V

10k

4

MONO

C1N

21

C14

100n

50V

GNDB

B3

BOOT

C1P

3

22

C13

1u
25V

C1

INN

C2

150k

R1317

15K

C1133
1u
16V

2

OUTL-1

OUTR-1

23

SDB

C3

AMP_EN

1

OUTL+2

OUTL-2

OUTL+1

PVDD2

PGND2

PGND1

PVDD1

OUTR+2

OUTR+1

OUTR-2

24

OUTP

L4

47u

F5

60R

R_OUT_P

S17

S16

32

31

30

29

28

27

26

25

C1114

50V 1n

VDD_AUDIO

R_OUT_N

10V

2u2

R42

150k

L_OUT_N

L_OUT_P

C15

R_OUT_P

R_AUDIO_P

C6

50V

100n

C16

100n

VDD_AUDIO

50V

5V_VCC

5V_Audio

24V_VCC

12V_VCC

18V_VCC

S298

S279

SCH NAME :
DRAWN BY :

MUTE_HP_L

S22

S20

S23

21

F3

60R

21

R_AUDIO_P

R_AUDIO_N

L_AUDIO_P

L_AUDIO_N

R_AUDIO_P

R_AUDIO_N

L_AUDIO_P

L_AUDIO_N

VESTEL

AUDIO
SADIK SEHIT

3

BC848B

Q134

BC848B

Q135

2

1

3

2

1

D1

SK24

47k

R44

21

10V
220u
C1134

C19

2

100n 10V

1

C18

2

10V100n

1

OPTIONAL

PROJECT NAME :

R544

2 1

10k

R545

2 1

10k

CN115

CN3

C12
330u
35V

D2

1

2

3

4

1

2

3

4

5

6

17mb37

C385

5V_VCC

21

10u

10V

POP_MUTE

VDD_AUDIO

21

1N4148

5V_VDD_AUDIO

SHEET:

15-10-2009_16:06

87654321

OF:

C

D

E

F

A3

187

AX M

A

B

1V0D_FE1

C

1V0D_FE1

D

E

F

3V3D_FE

1V0D_FE1

3V3D_FE

3V3D_FE

DIGITAL_IF-

DIGITAL_IF+

1 2 3 4 5 6 7 8

U174

TS431AIL

1 5

A

C908

2

1

21

C1161

6V3

2V5_QAM

C937C941

100n

C723
100n
10V

100n

16V

2
3 4

RC

C945

1n
50V

Q176
BC846B

50V

33p

FE1_SCL

FE1_SDA

50V

33p

SDA_TUN_DVB

SCL_TUN_DVB

RF_AGC_DVB

16V

IF_AGC_T

C700

2

100n

1

10V

C223

2

100n

1

10V

BCP56-16
Q175

2V5_QAM

C699

2

100n

1

10V

C207

2

100n

1

10V

R928

10k

R1209

1k

BA159

BC817-25

Q103

2

C227

Q171

BC847B

Q170

BC847B

3V3D_FE

2

1

D166

2V5_QAM

1

10V

100n

C206
100n
10V

3V3_VCC

1V_QAM

3

1

1

IF_AGC_T

IF_AGC_C

3V3_QAM

C1157
220u

3V3_VCC

2

R117
150R

1V_QAM

R1018

4k7

2 1

R803

4k7

2 1

6V3

2

F264

1k

C304

33p

50V

C305

33p

50V

R407

2 1

C830

C849

100n

100n

21

X101

21

1k

C905

IDTV_SW

IDTV_SW

1V0_FE

C930

27MHZ

21

2V5_QAM

2V5_QAM

C228

100n

10V

1V_QAM

100n

3V3_QAM

16V

10u

2

1

1V0_FE

1V0_FE

1V_QAM

C658

100n

C657

100n

DIGITAL_IF-

DIGITAL_IF+

C929

2V5_QAM

49

GNDD_AD12

50

VCCD_AD12

51

GNDA_PLL

52

VCCA_PLL

53

GNDD_PLL

54

VCCD_PLL

55

ZO

56

VCCA_OSC

57

A

58

GNDA_OSC

59

VBASE

60

VDD10REG

61

VDD4

62

GND4

63

VDD_IO_3V3_4

64

CLK_TST

F255
220R

F256
220R

TP161

1

C217

2

100n

1

10V

16V

10u

2

1

C224

48

VCCA_AD12

GPIO9

1

R31421100R

C750

2

100n

1

10V

C216
100n
10V

16V

10n

2 1

C384
C356

10n

16V

21

IF_M

R1061

1k

R1060 IF_CM

1k

C928

IF_P

IF_P

10V

1

2

100n

47

46

REFP

GNDA_AD12

45

REFM

IF_CM

44

INCM

C935

2V5_QAM

4p7

50V

42

43

INP

VCCAISO_D

41

INM

DVB-C

DEMODULATOR

U109

STV0297E

GPIO8

TDI

TDO

TRST

TCK

TMS

GPIO7/AUX_CLK

8

7

6

5

4

3

2

21

100R

R313

21

2

1

1V0D_FE1

C220

2

100n

1

10V

21

33R

R1098

C_RESET

4k7

R239

3V3_QAM

SCL_TUN_DVB

SDA_TUN_DVB

1V0A_FE1

C749

2

100n

1

10V

C215

2

100n

1

10V

C1041
100n

2

1

C214

2

100n

1

10V

10V

C748
100n
10V

16V

10u

C904

100n

IF_M

3V3_QAM

38

39

40

GNDAS_AD

VDD_IO_3V3_3

N_RESET

VDD1

9

11

10

1V_QAM

21

33R

R171

RESET_DVB

IF_AGC_C

IF_AGC_T

IF_AGC_C

IF_AGC_T

VESTEL

SCH NAME :
DRAWN BY :

16V

1V_QAM

35

36

37

GND3

VDD3

GPIO0/AGC2

GPIO1/AGC1

GND1

VDD_IO_3V3_1

GPIO6/CS0

GPIO5/CS1

14

13

12

S235

S234

21

4k7

R463

3V3_QAM

3V3_QAM

1

B1

2

GND

FSA3157

B0 A

S240

S239

DVB COFDM & QAM
ERTUG BAL

21

10k

R331

33

34

GPIO4/SDAT

GPIO2

TS_DATA[7]

GPIO3/SCLT

TS_DATA[6]

TS_DATA[5]

TS_DATA[4]

VDD_IO_3V3_2

TS_DATA[3]

TS_DATA[2]

TS_DATA[1]

TS_DATA[0]

SDA

SCL

16

15

21

100R

100R

R311

2 1

FE1_SDA

FE1_SCL

S

U182

VCC

PROJECT NAME :

C1020C1024

C1026

C1021

C1032

1u
6V3

C1031

1u
6V3

16V

100n

16V

100n

16V

100n

16V

100n

C1022

16V

10n

2 1

C757

C756

10n

16V

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

100n

21

1V0D_FE1

GPIO1

VDD_3V3_5

VDD_1V_6

GPIO8

GPIO7

GPIO6

VDD_1V_7

VDD_3V3_6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO9

VDD_1V_8

VDD_3V3_7

TEST

16V

C695

R1063

1k

R1062

1k

33R

R1341

R1153

10V

10u

IM_1

IP_1

8

1

48

1

TSPKTERR_1

TSVALID_1

7

6

R2

3

2

46

47

ERROR

D/NOT_P

RF_LEVEL

VDDA_2V5_1QPQM

3

2

C911

30k

100n

REFP_1

REFM_1

C927

10u

3V3_VCC

TSPKTCLK_1

TSBYTECLK_1

TS_DATA7_1

TS_DATA6_1

TS_DATA5_1

TS_DATA4_1

3p9

C916

54

R3R1R4

45

STR_OUT

VDD_1V_5

R1116

43

44

CLK_OUT

33R

D7

8

1

42

D6

7

R2

2

3V3D_FE

41

VDD_3V3_4

6

R3R1R4

3

40

D5

54

R1117

1V0D_FE1

38

39

D4

VDD_1V_4

DVB-T

DEMODULATOR

U152

STV0362

VDDA_ISO

VDDA_2V5_2

REFP

REFM

INCMIMIP

9

8

7

6

5

4

16V

2V5A_FE

16V

C912

C946

100n

6V3

1n

16V

220u

50V

C758

C1159

REFP_1

2 1

10n

F237
330R

REFM_1

INCM_1

16V

INCM_1

IM_1

21

C1160

22u

6V3

10

C936

4p7

50V

11

C799

100p

50V

C1023

100n

16V

IP_1

TS_DATA3_1

TS_DATA2_1

8

7

R2

33R

2

1

36

37

D3

D2

VDDA_1V

VDDA_2V5_3

13

12

2V5A_FE

1V0A_FE1

C1028

BA159

BA159

C721

2

100n

1

10V

TS_DATA1_1

6

R3R1R4

3

35

D1

XTAL_O

14

X108

27MHz

50V

33p

2V5A_FE

D165

D164

TS_DATA0_1

54

3V3D_FE

33

34

D0

NOT_RESET

VDD_3V3_3

VDD_3V3_2

VDD_3V3_1

XTAL_I

VDDA_2V5_4

16

15

C910

100n

16V

2V5A_FE

C1027

2V5A_FE

VDD_1V_3

SCL

SDA

GPIO0

CS1

CS0

VDD_1V_2

AUX_CLK

SDAT

SCLT

VDD_1V_1

AGC_RF

AGC_IF

50V

33p

F127
330R

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

3V3_VCC

3V3_VCC

21

2

1

C283
10u
10V

3V3_VCC 220R

R1141

47k

S267

S266

1V0D_FE1

R1077

100R

R1078

100R

3V3D_FE

16V16V

C1019

100n

100n

C1025

1V0D_FE1

R1042

R1043

4k7

1V0D_FE1

R911

R910

R908

10k

R909

10k

4k7

10k

10k

C907

F238
330R

6V3

100u

C221

2

100n

1

10V

R1059

RESET_DVB

RESET_T

3V3D_FE

R1083

100R

R1084

100R

3V3D_FE

R1168

180R

16V

C909

100n

3V3D_FE

R1167

180R

16V

C906

100n

21

C1162

22u

6V3

F128
330R

22u

C1151

C725

2

100n

1

10V

place this cap close to pin#56

IF_AGC_C

100n

C225

2

1

R332

10k

4k7

2 1

R298

GND2

VDD2

M_ERR

M_VALID

M_SYNC

M_CKOUT

R312

21

4k7

R469

3V3_QAM

6

5

43

IF_AGC_DVB

10V

21

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

4k7

R1038

4k7

R1037

17mb37

3V3_QAM

R427

33R

1

R1

2

R2

3

R3

R4

3V3_QAM

1V_QAM

R426

1

R1

2

R2

3

R3

R4

R1342

1

R1

2

R2

3

R3

R4

AGC_S1

S256

10V

C743

100n

C1033

14-10-2009_09:10

87654321

8

7

6

54

8

7

6

54

8

7

6

54

10V

100n

SHEET:

C_D7

C_D6

C_D5

C_D4

C_D3

C_D2

C_D1

C_D0

C_ERR

C_VAL

C_STRT

C_CLK

C188

2

15p

1

50V

5V_VCC

IF_AGC_DVB

A3

OF:

A

B

C

D

E

F

188

AX M

A

B

C

D

E

F

VDD_S_LMI_2V6

S_LMIDATA[0]

VDD_S_LMI_2V6

S_LMIDATA[1]

S_LMIDATA[2]

S_LMIDATA[3]

S_LMIDATA[4]

VDD_S_LMI_2V6

S_LMIDATA[5]

S_LMIDATA[6]

S_LMIDATA[7]

VDD_S_LMI_2V6

S_LDQS[0]

VDD_S_LMI_2V6

S_LDQM[0]

S_LWE

S_LCAS

S_LRAS

S_LCS

S_LBANK[0]

S_LBANK[1]

S_LMI_AD[10]

S_LMI_AD[0]

S_LMI_AD[1]

S_LMI_AD[2]

S_LMI_AD[3]

VDD_S_LMI_2V6

S_LMI_DATA0
S_LMI_DATA1
S_LMI_DATA2
S_LMI_DATA3

S_LMI_DATA4
S_LMI_DATA5
S_LMI_DATA6
S_LMI_DATA7

S_LMI_DATA8

S_LMI_DATA9
S_LMI_DATA10
S_LMI_DATA11

S_LMI_DATA12
S_LMI_DATA13
S_LMI_DATA14
S_LMI_DATA15

S_NOTLCLK

S_LMI_CLK

S_LMI_NOTCLK

S_LMI_CKEN

1k

R10011kR1003

C249

2

100n

1

10V

1 2 3 4 5 6 7 8

LMI SYSTEM DDR LMI SYSTEM DDR LMI VIDEO DDR LMI VIDEO DDR

2

1

3
2
1

3
2
1

3
2
1

3
2
1

C248
100n
10V

1

VDD1

2

DQ0

3

VDDQ1

4

DQ1

5

DQ2

6

VSSQ1

7

DQ3

8

DQ4

9

VDDQ2

10

DQ5

11

DQ6

12

VSSQ2

13

DQ7

14

NC1

15

VDDQ3

16

LDQS

HY5DU561622D

17

NC2

18

VDD2

19

NC3

20

LDM

21

WE#

22

CAS#

23

RAS#

24

CS#

25

NC4

26

BA0

27

BA1

28

A10/AP

29

A0

30

A1

31

A2

32

A3

33

VDD3

33R

R4

54

R3

6

R2

7

R1

8

R442

33R

R4

54

R3

6

R2

7

R1

8

R441

33R

R4

54

R3

6

R2

7

R1

8

R439

33R

R4

54

R3

6

R2

7

R1

8

R438
R315

21

100R
R193

33R

21

R186

33R

21

R188

21

33R

C250

2

100n

1

10V

C289

2

10u

1

10V

U156

S_LMIDATA[0]
S_LMIDATA[1]
S_LMIDATA[2]
S_LMIDATA[3]

S_LMIDATA[4]
S_LMIDATA[5]
S_LMIDATA[6]
S_LMIDATA[7]

S_LMIDATA[8]
S_LMIDATA[9]
S_LMIDATA[10]
S_LMIDATA[11]

S_LMIDATA[12]
S_LMIDATA[13]
S_LMIDATA[14]
S_LMIDATA[15]

S_LCLK

S_LCLK

S_NOTLCLK

S_LCKEN

S_LMI_VREF

C676
10u
10V

VDD_S_LMI_2V6

66

VSS3

65

DQ15

VSSQ5

DQ14

DQ13

VDDQ5

DQ12

DQ11

VSSQ4

DQ10

DQ9

VDDQ4

DQ8

NC7

VSSQ3

UDQS

NC6

VREF

VSS2

UDM

CLK#

CLK

CKE

NC5

A12

A11

A9

A8

A7

A6

A5

A4

VSS1

S_LMIDATA[23]

64

63

S_LMIDATA[22]

62

S_LMIDATA[21]

61

VDD_S_LMI_2V6

60

S_LMIDATA[20]

59

S_LMIDATA[19]

58

57

S_LMIDATA[18]

56

S_LMIDATA[17]

55

VDD_S_LMI_2V6

54

S_LMIDATA[16]

53

52

51

S_LDQS[2]

50

49

S_LMI_VREF

48

47

S_LDQM[2]

46

S_NOTLCLK

45

S_LCLK

44

S_LCKEN

43

42

S_LMI_AD[12]

41

S_LMI_AD[11]

40

S_LMI_AD[9]

39

S_LMI_AD[8]

38

S_LMI_AD[7]

37

S_LMI_AD[6]

36

S_LMI_AD[5]

35

S_LMI_AD[4]

34

S_LMI_DATA16
S_LMI_DATA17
S_LMI_DATA18
S_LMI_DATA19

S_LMI_DATA20
S_LMI_DATA21
S_LMI_DATA22
S_LMI_DATA23

S_LMI_DATA24
S_LMI_DATA25
S_LMI_DATA26
S_LMI_DATA27

S_LMI_DATA28
S_LMI_DATA29
S_LMI_DATA30
S_LMI_DATA31

R315 DDR IC'LERE YAKIN OLMALI
C288 & C289 DDR PIN33'LERE YAKIN OLMALI
C??? DDR IC'LERE YAKIN OLMALI
C254 STi7101'E YAKIN OLMALI
C277 VE R? BIRBIRINE YAKIN OLMALI

S_LMI_AD[3]

33R

R4
R3

3

R2

2

R1

1

R452

33R

R4
R3

3

R2

2

R1

1

R451

33R

R4
R3

3

R2

2

R1

1

R443

33R

R4
R3

3

R2

2

R1

1

R445

VDD_S_LMI_2V6

S_LMIDATA[8]

VDD_S_LMI_2V6

S_LMIDATA[9]

S_LMIDATA[10]

S_LMIDATA[11]

S_LMIDATA[12]

VDD_S_LMI_2V6

S_LMIDATA[13]

S_LMIDATA[14]

S_LMIDATA[15]

VDD_S_LMI_2V6

S_LDQS[1]

VDD_S_LMI_2V6

S_LDQM[1]

S_LBANK[0]

S_LBANK[1]

S_LMI_AD[10]

S_LMI_AD[0]

S_LMI_AD[1]

S_LMI_AD[2]

VDD_S_LMI_2V6

S_LMIDATA[16]

54

S_LMIDATA[17]

6

S_LMIDATA[18]

7

S_LMIDATA[19]

8

S_LMIDATA[20]

54

S_LMIDATA[21]

6

S_LMIDATA[22]

7

S_LMIDATA[23]

8

S_LMIDATA[24]

54

S_LMIDATA[25]

6

S_LMIDATA[26]

7

S_LMIDATA[27]

8

S_LMIDATA[28]

54

S_LMIDATA[29]

6

S_LMIDATA[30]

7

S_LMIDATA[31]

8

S_LWE

S_LCAS

S_LRAS

S_LCS

1

VDD1

2

DQ0

3

VDDQ1

4

DQ1

5

DQ2

6

VSSQ1

7

DQ3

8

DQ4

9

VDDQ2

10

DQ5

11

DQ6

12

VSSQ2

13

DQ7

14

NC1

15

VDDQ3

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

S_LMI_NOTBANK1

S_LMI_NOTBANK0

S_LMI_RDNOTWR

U154

LDQS

HY5DU561622D

NC2

VDD2

NC3

LDM

WE#

CAS#

RAS#

CS#

NC4

BA0

BA1

A10/AP

A0

A1

A2

A3

VDD3

S_LMI_ADDR0

S_LMI_NOTCS0

S_LMI_ADDR10

S_LMI_ADDR3
S_LMI_ADDR2
S_LMI_ADDR1

S_LMI_ADDR4

S_LMI_ADDR9
S_LMI_ADDR12
S_LMI_ADDR11

S_LMI_ADDR7

S_LMI_ADDR8

S_LMI_ADDR5

S_LMI_ADDR6

S_LMI_NOTRAS
S_LMI_NOTCAS

S_LMI_DQS0
S_LMI_DQM0
S_LMI_DQM2
S_LMI_DQS2

S_LMI_DQS1
S_LMI_DQM1
S_LMI_DQM3
S_LMI_DQS3

VSS3

DQ15

VSSQ5

DQ14

DQ13

VDDQ5

DQ12

DQ11

VSSQ4

DQ10

DQ9

VDDQ4

DQ8

NC7

VSSQ3

UDQS

NC6

VREF

VSS2

UDM

CLK#

CLK

CKE

NC5

A12

A11

VSS1

3
2
1

3
2
1

3
2
1

3
2
1

3
2
1

3
2
1

3
2
1

A9

A8

A7

A6

A5

A4

33R

R4
R3
R2
R1

R450

33R

R4
R3
R2
R1

R444

33R

R4
R3
R2
R1

R446

33R

R4
R3
R2
R1

R437

33R

R4
R3
R2
R1

R183

33R

R4
R3
R2
R1

R434

33R

R4
R3
R2
R1

R435

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

S_LMIDATA[31]

S_LMIDATA[30]

S_LMIDATA[29]

VDD_S_LMI_2V6

S_LMIDATA[28]

S_LMIDATA[27]

S_LMIDATA[26]

S_LMIDATA[25]

VDD_S_LMI_2V6

S_LMIDATA[24]

S_LDQS[3]

S_LMI_VREF

S_LDQM[3]

S_NOTLCLK

S_LCLK

S_LCKEN

S_LMI_AD[12]

S_LMI_AD[11]

S_LMI_AD[9]

S_LMI_AD[8]

S_LMI_AD[7]

S_LMI_AD[6]

S_LMI_AD[5]

S_LMI_AD[4]

S_LMI_AD[0]
S_LCS

S_LBANK[1]

S_LMI_AD[10]
S_LMI_AD[3]
S_LMI_AD[2]
S_LMI_AD[1]

S_LMI_AD[4]
S_LMI_AD[9]
S_LMI_AD[12]
S_LMI_AD[11]

S_LMI_AD[7]
S_LMI_AD[8]
S_LMI_AD[5]
S_LMI_AD[6]

S_LBANK[0]
S_LRAS
S_LCAS
S_LWE

S_LDQS[0]
S_LDQM[0]
S_LDQM[2]
S_LDQS[2]

S_LDQS[1]
S_LDQM[1]
S_LDQM[3]
S_LDQS[3]

V_LMI_ADDR0

V_LMI_NOTCS0

V_LMI_CKEN

V_LMI_ADDR11

V_LMI_ADDR3
V_LMI_ADDR2
V_LMI_ADDR1

V_LMI_ADDR4

V_LMI_ADDR12

V_LMI_ADDR9

V_LMI_ADDR10

V_LMI_ADDR8
V_LMI_ADDR7
V_LMI_ADDR6
V_LMI_ADDR5

V_LMI_NOTBANK1
V_LMI_NOTBANK0

V_LMI_NOTRAS
V_LMI_NOTCAS

V_LMI_DQS2
V_LMI_DQM2
V_LMI_DQM0
V_LMI_DQS0

V_LMI_DQS3
V_LMI_DQM3
V_LMI_DQM1
V_LMI_DQS1

3
2
1

R1105

3
2
1

R1115

3
2
1

R1107

3
2
1

R1104

3
2
1

R1106

3
2
1

R1112

3
2
1

R1114

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

33R

R4
R3
R2
R1

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

54
6
7
8

V_LMI_AD[0]
V_LCS

V_LCKEN

V_LMI_AD[11]
V_LMI_AD[3]
V_LMI_AD[2]
V_LMI_AD[1]

V_LMI_AD[4]
V_LMI_AD[12]
V_LMI_AD[9]
V_LMI_AD[10]

V_LMI_AD[8]
V_LMI_AD[7]
V_LMI_AD[6]
V_LMI_AD[5]

V_LBANK[1]
V_LBANK[0]
V_LRAS
V_LCAS

V_LDQS[2]
V_LDQM[2]
V_LDQM[0]
V_LDQS[0]

V_LDQS[3]
V_LDQM[3]
V_LDQM[1]
V_LDQS[1]

VDD_V_LMI_2V6

V_LMIDATA[23]

VDD_V_LMI_2V6

V_LMIDATA[22]

V_LMIDATA[21]

V_LMIDATA[20]

V_LMIDATA[19]

VDD_V_LMI_2V6

V_LMIDATA[18]

V_LMIDATA[17]

V_LMIDATA[16]

VDD_V_LMI_2V6

V_LDQS[2]

VDD_V_LMI_2V6

V_LDQM[2]

V_LWE

V_LCAS

V_LRAS

V_LCS

V_LBANK[0]

V_LBANK[1]

V_LMI_AD[10]

V_LMI_AD[0]

V_LMI_AD[1]

V_LMI_AD[2]

V_LMI_AD[3]

VDD_V_LMI_2V6

V_NOTLCLK

V_LMI_CLK

V_LMI_NOTCLK

V_LMI_RDNOTWR

R318 DDR IC'LERE YAKIN OLMALI
C289 DDR PIN33'E YAKIN OLMALI
C??? DDR IC'LERE YAKIN OLMALI
C260 STi7101'E YAKIN OLMALI
C278 VE R? BIRBIRINE YAKIN OLMALI

1

VDD1

2

DQ0

3

VDDQ1

4

DQ1

5

DQ2

6

VSSQ1

7

DQ3

8

DQ4

9

VDDQ2

10

DQ5

11

DQ6

12

VSSQ2

13

DQ7

14

NC1

15

VDDQ3

16

LDQS

HY5DU561622D

17

NC2

18

VDD2

19

NC3

20

LDM

21

WE#

22

CAS#

23

RAS#

24

CS#

25

NC4

26

BA0

27

BA1

28

A10/AP

29

A0

30

A1

31

A2

32

A3

33

VDD3

R318

21

100R
R182

33R

21

R189

21

33R

R190

21

33R

U153

VSS3

DQ15

VSSQ5

DQ14

DQ13

VDDQ5

DQ12

DQ11

VSSQ4

DQ10

DQ9

VDDQ4

DQ8

NC7

VSSQ3

UDQS

NC6

VREF

VSS2

UDM

CLK#

CLK

CKE

NC5

A12

A11

A9

A8

A7

A6

A5

A4

VSS1

V_LCLK

V_LCLK

V_NOTLCLK

V_LWE

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

V_LMI_DATA10
V_LMI_DATA11

V_LMI_DATA12
V_LMI_DATA13
V_LMI_DATA14
V_LMI_DATA15

R1004

V_LMIDATA[0]

V_LMIDATA[1]

V_LMIDATA[2]

VDD_V_LMI_2V6

V_LMIDATA[3]

V_LMIDATA[4]

V_LMIDATA[5]

V_LMIDATA[6]

VDD_V_LMI_2V6

V_LMIDATA[7]

V_LDQS[0]

V_LMI_VREF

V_LDQM[0]

V_NOTLCLK

V_LCLK

V_LCKEN

V_LMI_AD[12]

V_LMI_AD[11]

V_LMI_AD[9]

V_LMI_AD[8]

V_LMI_AD[7]

V_LMI_AD[6]

V_LMI_AD[5]

V_LMI_AD[4]

V_LMI_DATA0
V_LMI_DATA1
V_LMI_DATA2
V_LMI_DATA3

V_LMI_DATA4
V_LMI_DATA5
V_LMI_DATA6
V_LMI_DATA7

V_LMI_DATA8
V_LMI_DATA9

1k

1k

R1002

C273

2

2

100n

1

1

10V

2

1

C247
100n
10V

1
2
3

1
2
3

1
2
3

1
2
3

C266
100n
10V

R453

33R

R432

33R

R448

33R

R449

33R

C677
10u
10V

VDD_V_LMI_2V6

V_LMIDATA[31]

VDD_V_LMI_2V6

V_LMIDATA[30]

V_LMIDATA[29]

V_LMIDATA[28]

V_LMIDATA[27]

VDD_V_LMI_2V6

V_LMIDATA[26]

V_LMIDATA[25]

V_LMIDATA[24]

VDD_V_LMI_2V6

V_LDQS[3]

VDD_V_LMI_2V6

V_LDQM[3]

V_LWE

V_LCAS

V_LRAS

V_LCS

V_LBANK[0]

V_LBANK[1]

V_LMI_AD[10]

V_LMI_AD[0]

V_LMI_AD[1]

V_LMI_AD[2]

V_LMI_AD[3]

VDD_V_LMI_2V6

8

R1
R2
R3
R4

R1
R2
R3
R4

R1
R2
R3
R4

R1
R2
R3
R4

7
6
54

8
7
6
54

8
7
6
54

8
7
6
54

V_LMI_VREF

C675
10u
10V

VDD_V_LMI_2V6

V_LMIDATA[0]
V_LMIDATA[1]
V_LMIDATA[2]
V_LMIDATA[3]

V_LMIDATA[4]
V_LMIDATA[5]
V_LMIDATA[6]
V_LMIDATA[7]

V_LMIDATA[8]
V_LMIDATA[9]
V_LMIDATA[10]
V_LMIDATA[11]

V_LMIDATA[12]
V_LMIDATA[13]
V_LMIDATA[14]
V_LMIDATA[15]

VESTEL

SCH NAME :
DRAWN BY :

1

VDD1

2

DQ0

3

VDDQ1

4

DQ1

5

DQ2

6

VSSQ1

7

DQ3

8

DQ4

9

VDDQ2

10

DQ5

11

DQ6

12

VSSQ2

13

DQ7

14

NC1

15

VDDQ3

16

LDQS

HY5DU561622D

17

NC2

18

VDD2

19

NC3

20

LDM

21

WE#

22

CAS#

23

RAS#

24

CS#

25

NC4

26

BA0

27

BA1

28

A10/AP

29

A0

30

A1

31

A2

32

A3

33

VDD3

V_LMI_DATA16
V_LMI_DATA17
V_LMI_DATA18
V_LMI_DATA19

V_LMI_DATA20
V_LMI_DATA21
V_LMI_DATA22
V_LMI_DATA23

V_LMI_DATA24
V_LMI_DATA25
V_LMI_DATA26
V_LMI_DATA27

V_LMI_DATA28
V_LMI_DATA29
V_LMI_DATA30
V_LMI_DATA31

U155

VSS3

DQ15

VSSQ5

DQ14

DQ13

VDDQ5

DQ12

DQ11

VSSQ4

DQ10

DQ9

VDDQ4

DQ8

NC7

VSSQ3

UDQS

NC6

VREF

VSS2

UDM

CLK#

CLK

CKE

NC5

A12

A11

A9

A8

A7

A6

A5

A4

VSS1

PROJECT NAME :

DDR RAM FOR STi7101
HUSEYIN E. CETIN

1
2
3

1
2
3

1
2
3

1
2
3

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

R436

33R

R1
R2
R3
R4

R433

33R

R1
R2
R3
R4

R440

33R

R1
R2
R3
R4

R447

33R

R1
R2
R3
R4

V_LMIDATA[8]

V_LMIDATA[9]

V_LMIDATA[10]

VDD_V_LMI_2V6

V_LMIDATA[11]

V_LMIDATA[12]

V_LMIDATA[13]

V_LMIDATA[14]

VDD_V_LMI_2V6

V_LMIDATA[15]

V_LDQS[1]

V_LMI_VREF

V_LDQM[1]

V_NOTLCLK

V_LCLK

V_LCKEN

V_LMI_AD[12]

V_LMI_AD[11]

V_LMI_AD[9]

V_LMI_AD[8]

V_LMI_AD[7]

V_LMI_AD[6]

V_LMI_AD[5]

V_LMI_AD[4]

8

V_LMIDATA[16]

7

V_LMIDATA[17]

6

V_LMIDATA[18]

54

V_LMIDATA[19]

8

V_LMIDATA[20]

7

V_LMIDATA[21]

6

V_LMIDATA[22]

54

V_LMIDATA[23]

8

V_LMIDATA[24]

7

V_LMIDATA[25]

6

V_LMIDATA[26]

54

V_LMIDATA[27]

8

V_LMIDATA[28]

7

V_LMIDATA[29]

6

V_LMIDATA[30]

54

V_LMIDATA[31]

17mb37

SHEET:

14-10-2009_09:10

87654321

OF:

A

B

C

D

E

F

A3

189

AX M

1 2 3 4 5 6 7 8

17PW26 CONNECTOR

A

B

C

D

E

F

KEYBOARD_ONBOARD

C7

47u

16V

5V_VCC

1

TP31

12V_STBY

18V_VCC

12V_VCC

TP26

5V_PW

5V_PW

12V_STBY

18V_VCC

12V_VCC

1

TP23

12V_STBY

MOSFET_CONTROL

24V_VCC

5V_PW

FS6

7A/32VDC

!

TP33

17IPS17 CONNECTOR

1

20 19

18 17

16 15

14 13

12 11

10 9

CN137

S303

5V_STBY

21

1

8 7

6 5

4 3

2 1

TP29

1

21

C1086
220n
25V

21

C1085

R1276

2 1

4k7

C1055
100n

10V

CN4

3V3_VCC

1

1

1

12V_VCC

C1102

22u

16V

25V

220n

2

2

1

21

43

65

87

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

TP25

TP28

TP27

2

1

33k

R1296

2 1

33k

R1297

2 1

3

1

A/D DIMMING SELECTION

R22
4k7
R21
4k7
R23
4k7

12V_STBY

3V3_VCC

12V_STBY

5V_STBY

C5V6

D182

2 1

21

D180

C5V6

C1071

2

10n

1

16V

C1103

2

22u

1

16V

D188

21

SS33

43

R1253

21

47R

Q181
BC848B

21

21

21

6V3

220u

C8

3V3_VCC

5V_STBY

12V_VCC

C5V6

2 1

1

BS

2

IN

3

SW

4

GND

L122

10u

5

2

5V_VCC

3V3_VCC

24V_VCC

1

TP30

S19

21

PIN 13-14 OF CN4 ARE 3V3

D181

U187

MP1583

COMP

21

SS
EN

FB

2

1

8
7
6
5

C1098
22u
16V

C1097

22u

21

1k

R1257

21

30k

R1306

16V

R1270

4k7

R1271

4k7

R1275

4k7

R1272

4k7

MECH_SWITCH

C1122

21

5n6

C1080

50V

100n

TP380

1

2

1

21

R1301

NC

21

16V

5V_STBY

!

FS3

6

FDC642P

1

Q183

TP387

7A/32VDC

3V3_STBY12V_STBY

21

DIMMING

21

BACKLIGHT_ON/OFF

21

STBY_ON/OFF

21

STBY_ON/OFF_NOT

10V
100n
C1046

21

3k9

R1245

10k

3V3_STBY

MOSFET_CONTROL

21

5V_VCC

PAULO DECOUPLING

3V3_STBY

1V26_STBY

3V3_STBY

12V_VCC

STBY_ON/OFF

STBY_ON/OFF_NOT

12V_STBY

F146
330R

F147
330R

F145
330R

F279
330R

10V

10V

10V

S305

C1088
220n
25V

ADAPTER OPTIONS

21

S21

21

C1092

R1274

2 1

4k7

C1054
100n

10V

5

4

JK109

3

2

1

21

10u

21

10u

21

10u

21

1

2

21

220n

2

1

2 1

2 1

2 1

S289

S280

25V

2

C408

C410

C409

C470
47u
16V

C1110

22u

R1299

2 1

R1298

2 1

3

1

7A/32VDC

7A/32VDC

VDDP

C307

2

100n

1

10V

VDDC

C308

2

100n

1

10V

AVDD_33

C306

2

100n

1

10V

U122

LM1117

3 2

GND

OUTIN

VOUT

4

1

MOSFET_CONTROL

C1074

10n

C1111

2

2

22u

1

1

16V

16V

D190

SS33

33k

R1252

21

47R

33k

Q177
BC848B

!

FS5

21

!

FS4

21

16V

21

43

5V_STBY

12V_STBY

12V_PSU

12V_INV

3V3_STBY

S210

21

6V3

2 1

220u

NC NC

C464

2

1

C578
22u
16V

R702

33k

2

1

C576
22u
16V

21

MP2112

VINA

U144

EN

SWVINB

GND

FB

4 3

5

6

C535

21

L110

10u

21

C575

2

R249

200k

1

R818
180k

22u
16V

2

1

1V26_STBY

C579

2

22u

1

16V

NC

2 1

S134

D177

D176

1V0_ST

2V5_ST

A

1n

D161

C812

C816

C876

22u

100n

12V_VCC

F8

21

330R

C20

100n

MOSFET_CONTROL

S302

21

25V

C1084

220n

21

33k

R1295

3

Q180
BC848B

1

12V_STBY

12V_VCC

21

33k

R1294

2 1

C1079
4u7
16V

R1249

47R

S306

S307

2V5_ST

21

21

21

C1093
220n
25V

43

D186

5

2

12V_IPOD

C18V

6

1

12V_STBY

Q184

FDC642P

1V0_ST

12V_VCC

2V5_ST

12V_VCC

1

BACKLIGHT_ON/OFF

TP377

DIMMING

TP384

5V_VCC

12V_VCC

C1051
100n

3k9

12V_PSU

21

R1242

10k

10V

S269

21

21

2

2

1

8V_VCC

R378

10k

U190

21

COMP

2

1

C452

21

SS
EN

FB

C1108
22u
16V

21

8
7
6
5

C1109

10u

R476

R1262

R1308

22u

16V

25V

1k

21

21

1k

30k

1

2

1

21

2k

R411

2

MP1583

1

1

BS

2

IN

3

SW

4

GND

L124

10u

MOSFET_CONTROL

D179

3V3_VCC

C5V6

1

6

5

TP381

Q182

FDC642P

2

1

21

C1124

C1083

100n

TP388

21

3k9

R1339

100n

10V

C1058

21

5n6

50V

16V

12V_STBY

5V_Audio

2V6_ST

21

NC

21

2 1

R1340

R1303

3k9

R1273

4k7

C1053
100n

C1047

3V3_VCC

21

S301

S300

C1089
220n
25V

21

100n

10V

C1125

R1304

21

3k9

21

5n6

C1081

50V

100n

16V

NC

2k

R1246

21

10k

1
2
3
4

U189

MP1583

BS
IN
SW
GND

COMP

8

SS

7

EN

6
5

FB

21

21

21

C1105

22u

16V

C1072

2

10n

1

16V

C1104

2

2

22u

1

1

16V

R1321

21

F244

C972
220u
25V

C875

100n

F243

TP386

1

2

1

10V

11

F170

60R

F171

60R

F172

60R

F285

60R

PANEL_VCC_ON/OFF

R931

10k

R1074

10k 2k7

C815
22u

R930

10k

R1075

10k

10

21

21

21

21

8

7

6

5 4

8

7

6

5 4

1

C1052

9

8

C618

R575

2 1

10k

C309

100n

10V

2

VCC

GND

L5985

FSW

VCC

GND

L5985

FSW

1

10V

100n

7

25V

220n

21

2

1

U183

U184

C1

220n

TP378

15k

D191

SS33

21

L125

10u

C1100
22u
16V

21

2

1

R1293

C1099

22u

16V

1

3V3_STBY

2

1

NC

D178

C5V6

VESTEL

SCH NAME :
DRAWN BY :

SK24

1

OUT

2

SYNCH

3

INH

COMPFB

D162

SK24

1

OUT

2

SYNCH

3

INH

COMPFB

INVERTER SOCKET

6

5

4

3

21

21

25V

33k

R700

R205

21

47R

10k

R566

2 1

3

2

Q139
BC848B

1

PROJECT NAME :

POWER
SADIK SEHIT

L120

10u

C920

C761

10n

R1142

10p

L121

10u

C759

R929

10k

C918

10n

10p

1

TP385

C1091
220n

2

2

1

43

C2
22u
16V

25V

1

CN144

6

5

Q104

FDC642P

2

1

C17

2

22u

1

16V

PANEL SUPPLY SWITCH

17mb37

C764

22u

10n

16V

16V

C754
47u
16V

390R

R1139

6k8

R1064

C814

C779

22u

10n

16V

16V

C753
47u
16V

2k

R1176

30k

R1152

12V_INV

C1078
4u7
16V

TP149

1

PANEL_VCC

SHEET:

15-10-2009_15:59

87654321

1V0_ST

2V5_ST

OF:

B

C

D

E

F

A3

1810

AX M

MST6WB7GQ-3

A

B

C

6

U138

GND15

VDDC4

LVA4P

LVA4M

LVA3P

LVA3M

LVACKP

LVACKM

LVA2P

LVA2M

LVA1P

LVA1M

LVA0P

LVA0M

VDDP6

GND16

LVB4P

LVB4M

LVB3P

LVB3M

LVBCKP

LVBCKM

LVB2P

LVB2M

LVB1P

LVB1M

LVB0P

LVB0M

1 2 3 4 5 6 7 8

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

VDDC

RX_A_3_P

RX_A_3_N

RX_A_CLK_P

RX_A_CLK_N

RX_A_2_P

RX_A_2_N

RX_A_1_P

RX_A_1_N

RX_A_0_P

RX_A_0_N

VDDP

RX_B_3_P

RX_B_3_N

RX_B_CLK_P

RX_B_CLK_N

RX_B_2_P

RX_B_2_N

RX_B_1_P

RX_B_1_N

RX_B_0_P

RX_B_0_N

2

C311

1

10V

100n

19" TO 22" FFC OPTIONS

2 1

PANEL_VCC

PANEL_VCC = 5V

S295

RX_B_0_N

RX_B_0_P

RX_B_1_N

RX_B_1_P

RX_B_2_N

RX_B_2_P

RX_B_CLK_N

RX_B_CLK_P

RX_B_3_N

RX_B_3_P

RX_A_0_N

RX_A_0_P

RX_A_1_N

RX_A_1_P

RX_A_2_N

RX_A_2_P

RX_A_CLK_N

RX_A_CLK_P

RX_A_3_N

RX_A_3_P

2 1

S290

2 1

S291

PANEL_VCC

CN138

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

LVDS CABLE

RX_B_3_P

RX_A_0_N

RX_A_0_P

RX_A_1_N

RX_A_1_P

RX_A_2_N

RX_A_2_P

RX_A_CLK_N

RX_A_CLK_P

RX_A_3_N

RX_A_3_P

S283

2 1

CN140

PANEL_VCC

21

43

65

87

109

1211

BACKLIGHT_ON/OFF

1413

1615

1817

RX_A_CLK_N

2019

2221

2423

2625

2827

3029

RX_A_2_P

OPTION1

OPTION2

OPTION3

TP405

TP406

RX_B_0_N

RX_B_0_P

RX_B_1_N

RX_B_1_P

RX_B_2_N

RX_B_2_P

RX_B_CLK_N

RX_B_CLK_P

RX_B_3_N

RX_B_3_P

RX_A_0_N

RX_A_0_P

TP395

RX_A_1_N

RX_A_1_P

TP400

1

1

RX_A_2_N

RX_A_CLK_P

RX_A_3_N

RX_A_3_P

MEGA_DCR

TP396

TP392

TP404

TP390

TP408

TP407

TP389

TP403

TP391

TP401

TP394

TP398

TP397

TP399

TP393

TP402

CN139

1

1

1

1

1

1

21

43

65

87

109

1211

1

1

1

1

1

1

1

1413

1615

1817

2019

2221

2423

2625

2827

PANEL_VCC

S285

10k

2 1

R1244

2 1

R1243

21

3V3_VCC

10k

3029

3231

1

1

3433

3635

S288

BACKLIGHT_ON/OFF

S286

21

3837

4039

1

1

1

4241

4443

4645

OPTION1

OPTION2

OPTION3

4847

5049

3V3_VCC

21

PDP_IRQ

21

S284

21

S287

A

B

C

D

D

SHORT CCT PROTECTION

R706

2 1

5V_TUN

3V3_VCC

5V_VCC

S228

33k

10k

R569

21

3

PROTECT_PANEL

MEGA_DCR

21

S6

OPTION2

3V3_VCC

10k

2 1

R1

3V3_VCC

21

21

S8

10k

2 1

R2

S5

E

21S121

PANEL VCC = 5V/12V

PANEL_VCC

30

29

28

27

26

25

21

S3

S4

24

23

22

21

20

19

OPTION1

RX_A_3_P

RX_A_3_N

18

17

PDP_IRQ

21

S9

16

RX_A_CLK_N

RX_A_CLK_P

15

14

13

RX_A_2_N

RX_A_2_P

12

11

10

RX_A_1_P

RX_A_1_N

9

8

7

RX_A_0_P

RX_A_0_N

6

5

PANEL_VCC

R3

S2

10k

2 1

4

21

3

3V3_VCC

R4

10k

2 1

2

R5

10k

2 1

1

PANEL_VCC

F1

330R

2 1

CN2

OPTION3

3V3_VCC

10k

2 1

PANEL_VCC

10k

2 1

F2

R6

330R

2 1

R7

PANEL_VCC

PANEL_VCC = 5V/12V

9

8

7

6

5

4

3

2

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

1

CN1

Q137

3

2

1

BC848B

PROTECT

3

1

BC848B

F

Q136

2

TP150

1

BC858B

R708

2 1

33k

10k

R571

3V3_STBY

Q151

R563

10k

1

3

21

21

R562

21

10k

PANEL_VCC

2 1

2

R565

10k

R564

10k

21

D135

BAW56

21

3

D136

BAW56

21

3

D137

BAW56

21

3

D3

BAW56

21

R705

2 1

33k

10k

R568

R37

2 1

33k

10k
R32

8V_VCC

12V_VCC

21

24V_VCC

21

LOWER_SUP

Q163

BC848B

LOWER_SUP

3V3_VCC

Q162

BC848B

R912

10k

R914

R1000

10k

1k

R913

10k

21

3

D159

BAW56

21

3

D158

BAW56

1V0_FE

1k

1k

R1259

R1256

1V0_ST

LOWER SUPPLY SHORT CCT PROTECTION

1k

R1260

1k

R1255

2V6_ST

E

2V5_ST

F

VESTEL

SCH NAME :
DRAWN BY :

LVDS INTERFACE
SADIK SEHIT

PROJECT NAME :

17mb37

14-10-2009_09:09

87654321

SHEET:

OF:

A3

1811

AX M

1 2 3 4 5 6 7 8

3V3D_USB

A

USB_OC_1

10k

R893

35

36

TEST1

CLKIN_EN

VDDA33_1

USBDP0

2

1

34

OCS1_N

USBDN0

3

USB_RESET

3V3D_USB

3V3D_USB

3V3D_USB

16V

100n

R889

10k

1V8_D

R1212

12k

37

RESET_N

38

VSS_5

39

VDD33CR

40

VDD18_3

41

VSS_6

42

XTAL2

43

XTAL1/CLKIN

44

VDDA18PLL

45

VDDA33PLL

46

ATEST/REG_EN

47

RBIAS

48

VSS_7

3V3D_USB

B

C925

22p

C926

22p

X109

C818

24MHz

16V

22u

1M

R1144

C896

C

C931

3V3A_USB

w/o USB Hub Opsiyonu 1

USB_DP

USB_DN

S236

S233

USB_DP_1

USB_DN_1

1p

USB_DP

USB_DN

S250

R1160

470k

1V8_D

USB_OC_2

USB_PWR_EN_1

31

32

33

OCS2_N

PRTPWR1

VDD18_2

U177

USB2503

VSS_1

USBDN1

USBDP1

6

5

4

1p

USB_DN_1

C1030

1u
6V3

30

VSS_4

VDDA33_2

7

3V3A_USB

USB_DP_1

28

29

VBUS_DET

USBDP2

9

8

C933C934

1p

USB_DP_2

3V3D_USB

26

27

SELF_PWR

CFG_SEL1

SCL/SMBCLK/CFG_SEL0

USBDN2

VSS_2

USBDN3

11

10

USB_DN_2

R1031

4k7

R1032

4k7

R1016

25

SDA/SMBDATA

GR1/NON_REM0

GR2/NON_REM1

PRTPWR_POL

GR3/PRTDIS0

USBDP3

12

3V3D_USB

4k7

R950

47R

R939

47R

TEST0

VDD18_1

VSS_3

GANG_EN

PRTPWR2

OCS3_N

PRTPWER3

VDDA33_3

FE1_SCL

FE1_SDA

24

23

22

21

20

19

18

17

16

15

14

13

1V8_D

R890

10k

R892

10k

3V3D_USB

R891

10k

USB_PWR_EN_2

3V3A_USB

3V3_VCC 4k7

5V_USB

R1222

R1221

4k7

R1220

4k7

S259

5V_VCC

3V3_VCC

S257

F236
330R

C811

C1035
10u
10V

22u

16V

C900

C836

16V

100n

16V

100n

5V_USB

3V3D_USB

Should be close to Pin#45

C819

F248
330R

22u

16V

C898

C1034
10u
10V

100n

16V

C893

C899

16V

100n

16V

100n

C895

C897

16V

C894

100n

16V

100n

16V

100n

3V3_VCC 3V3A_USB

1V8_D

Should be close to Pin#40

1

OUT

U166

2

GND

R1035

8
7
6
54

4k7

STMP2161

FAULT EN

5V_USB

USB_OC_1
USB_PWR_1
USB_PWR_2
USB_OC_2

USB_OC_1

USB_OC_1

USB_OC_25V_USB

USB_OCD

R1069

100k

5V_USB
USB_PWR_EN_1
USB_PWR_EN_2

R1140

47k

U165

ST2052

1

GND

2

IN

3

EN1
EN2 OC2

OC1
OUT1
OUT2

A

B

5

IN

5V_USBUSB_PWR_A

43

USB_ENA_A

C

w/o USB Hub Opsiyonu 2

D

USB_DP

USB_DN

E

F

S10

S7

USB_DP_2

USB_DN_2

USB_DM_A

USB_DP_A

R1058

10R

R1057

10R

DEFAULT USB

USB_PWR_A

1

IO1

U167

2

GND

AZ099-04S

IO2 IO3

IO4

VDD

6

5

43

OPTIONAL USB

10V

10u

10V

10u

F250
330R

USB_DN_1

USB_DP_1

F249
330R

USB_DN_2

USB_DP_2

C1128

10V

10u

USB_PWR_1

USB_PWR_2

F251
330R

SERVICE USB

C1126

C1127

D

CN131

1

2

3

4

E

CN132

1

2

3

4

5

6

7

8

F

VESTEL

SCH NAME :
DRAWN BY :

USB
SADIK SEHIT

PROJECT NAME :

17mb37

SHEET:

14-10-2009_09:09

87654321

OF:

A3

1812

AX M

1 2 3 4 5 6 7 8

16V

C829

100n

1

A

R1173

8

1

2

3

R1174

1

2

3

R1172

1

2

3

R1

R2

10R

R3

R4

R1

R2

10R

R3

R4

R1

R2

10R

R3

R4

C_D7

C_D6

C_D5

C_D4

C_D3

C_D2

B

C_D1

C_D0

C_ERR

C_VAL

C_STRT

C_CLK

7

6

54

8

7

6

54

8

7

6

54

TS_DATA7_1

TS_DATA6_1

TS_DATA5_1

TS_DATA4_1

TS_DATA3_1

TS_DATA2_1

TS_DATA1_1

TS_DATA0_1

TSPKTERR_1

TSVALID_1

TSPKTCLK_1

TSBYTECLK_1

C

D

FLASH_NOTCSD

FLASH_ADDR0

BUFADDR_4

FLASH_ADDR1

BUFADDR_5

FLASH_ADDR2

BUFADDR_6

FLASH_ADDR3

BUFADDR_7

FLASH_NOTCSD

FLASH_ADDR8

BUFADDR_12

FLASH_ADDR9

BUFADDR_13

FLASH_ADDR10

BUFADDR_14

FLASH_ADDR11

CI_DATA_DIR

BUFDATA_0

BUFDATA_1

BUFDATA_2

BUFDATA_3

BUFDATA_4

BUFDATA_5

BUFDATA_6

BUFDATA_7

1OE-

2

1A1

3

2Y4

4

1A2

5

2Y3

74LCX244

6

1A3

7

2Y2

8

1A4

9

2Y1

GND 2A1

1

1OE-

2

1A1

3

2Y4

4

1A2

5

2Y3

74LCX244

6

1A3

7

2Y2

8

1A4

9

2Y1

GND 2A1

1

DIR

2

A1

3

A2

4

A3

5

A4

74LCX245

6

A5

7

A6

8

A7

9

A8

GND B8

U163

U162

U164

E

1

FLASH_NOTCSD

3V3_CI

4k7

R1025

EMI_BE0

CI_IORD

CI_WE

CI_OE

F

1OE-

2

1A1

3

2Y4

4

1A2

5

2Y3

74LCX244

6

1A3

7

2Y2

8

1A4

9

2Y1

GND 2A1

U161

VCC

2OE-

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

VCC

2OE-

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

VCC

OE-

VCC

2OE-

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

20

19

18

17

16

15

14

13

12

1110

20

19

18

17

16

15

14

13

12

1110

20

19

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

1110

20

19

18

17

16

15

14

13

12

1110

FLASH_NOTCSD

BUFADDR_0

FLASH_ADDR4

BUFADDR_1

FLASH_ADDR5

BUFADDR_2

FLASH_ADDR6

BUFADDR_3

FLASH_ADDR7

C832

100n

FLASH_NOTCSD

BUFADDR_8

FLASH_ADDR12

BUFADDR_9

FLASH_ADDR13

BUFADDR_10

FLASH_ADDR14

BUFADDR_11

C831

100n

FLASH_NOTCSD

FLASH_DATA0

FLASH_DATA1

FLASH_DATA2

FLASH_DATA3

FLASH_DATA4

FLASH_DATA5

FLASH_DATA6

FLASH_DATA7

C834

100n

FLASH_NOTCSD

CI_IOWR

EMI_NBAA

FLASH_NOTOE

3V3_CI

16V

3V3_CI

16V

3V3_CI

16V

3V3_CI

FLASH_NOTWE

R1050

4k7

3V3_CI

L118
22u

16V

C846

100n

C845

100n

TS_DATA3_3

54

R4

CD1

36

37

2

3

BUFDATA_3

BUFDATA_4

CD2

CD1

CI_IRQ

CI_WAIT

CI_OE

CI_WE

CI_IOWR

CI_IORD

S258

16V

C1094

TS_DATA5_3

TS_DATA4_3

7

6

R2R3R1

47R

3

2

38

39

4

5

BUFDATA_6

BUFDATA_5

R1053

R1052

R1023

R1049

R1044

C957

2p2

5V_VCC 5V_CI

35

1

CN116

CI_RESET

C1095

10u

TS_DATA6_3

8

R323

21

1

40

6

BUFDATA_7

21

4k7

21

4k7

21

4k7

21

4k7

21

4k7

50V

R34

21

4k7
R36

21

4k7
R33

21

4k7
R35

21

4k7

3V3_CI3V3_VCC

16V

10u

16V

TS_DATA7_3

3V3_CI

47R

4k7

R200

2 1

41

42

7

8

BUFADDR_10

FLASH_NOTCSD

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

R241

43

9

CI_OE

CI_IOWR

CI_IORD

44

45

10

11

BUFADDR_9

BUFADDR_11

TSPKTCLK_1

TS_DATA0_1

46

47

12

13

BUFADDR_8

BUFADDR_13

TSBYTECLK_3

TS_DATA1_1

TS_DATA2_1

48

49

14

15

CI_WE

C903

BUFADDR_14

100n

16V

CI_CLK

3V3_CI

3V3_CI

2 1

3V3_CI

21

5V_CI

TS_DATA3_1

4k7

R471

50

51

52

16

17

18

4k7

R472

2 1

CI_IRQ

3V3_CI

5V_CI

5V_CI line should be thick !

C967

2p2

50V

C958

2p2

50V

R1021

4k7

FLASH_NOTOE

EMI_NBAA

R1045

4k7

R963

47R

TS_DATA4_1

TS_DATA5_1

53

54

55

19

20

21

CI_CLK

TSVALID_1

CD1

CD2

TSPKTERR_1TSPKTERR_3

TS_DATA6_1

TS_DATA7_1

56

22

BUFADDR_7

BUFADDR_12

VESTEL

SCH NAME :
DRAWN BY :

STi7101 NOR FLASH & CI
ERTUG BAL

U171

74V1G08

1

A

2

B
GND Y

1

B

U157

2

A

74LVC1G32

GND Y

TSBYTECLK_3

CI_RESET

CI_WAIT

33R

R1093

57

58

59

23

24

25

BUFADDR_4

BUFADDR_6

BUFADDR_5

CI_WE

PROJECT NAME :

VCC

VCC

60

26

BUFADDR_3

C968

2p2

C841

5

43

C844

5

43

CI_REG

R199

61

27

BUFADDR_2

50V

16V

100n

3V3_CI

R956

47R

R1022

4k7

16V

100n

3V3_CI

S249

TSVALID_3

TSPKTCLK_3

21

8

47R

1

62

63

28

29

BUFADDR_1

BUFADDR_0

17mb37

CI_DATA_DIR

3V3_CI

CI_DETECT

TS_DATA0_3

TS_DATA1_3

TS_DATA2_3

7

6

54

R2

R3R1R4

47R

R324

3

2

64

65

66

30

31

32

BUFDATA_2

BUFDATA_0

BUFDATA_1

SHEET:

14-10-2009_09:10

87654321

R333

CD2

67

33

10k

2 1

3V3_CI

OF:

68

34

A

B

C

D

E

F

A3

1813

AX M

1 2 3 4 5 6 7 8

A

FLASH_ADDR16

FLASH_ADDR15

FLASH_ADDR14

FLASH_ADDR13

FLASH_ADDR12

FLASH_ADDR11

FLASH_ADDR10

FLASH_ADDR9

B

C

FLASH_ADDR20

FLASH_ADDR21

FLASH_ADDR22

VCC_F

FLASH_WP

VCC_F

FLASH_ADDR19

FLASH_ADDR18

FLASH_WE

RESET_7101

S243
S242

S241

FLASH_ADDR8

FLASH_ADDR7

FLASH_ADDR6

FLASH_ADDR5

FLASH_ADDR4

FLASH_ADDR3

FLASH_ADDR2

NOR FLASH

1

A15

2

A14

3

A13

4

A12

5

A11

6

A10

7

A9

8

A8

9

A19

10

A20

11

W

12

RP

M29W640

13

NC

14

VPP/WP

15

RB

16

A18

17

A17

18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

A1 A0

DQ15A-1

U172

A16

BYTE

VSS2

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

VSS1

E

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

2524

FLASH_ADDR17

VCC_F

FLASH_DATA15

FLASH_DATA7

FLASH_DATA14

FLASH_DATA6

FLASH_DATA13

FLASH_DATA5

FLASH_DATA12

FLASH_DATA4

VCC_F

FLASH_DATA11

FLASH_DATA3

FLASH_DATA10

FLASH_DATA2

FLASH_DATA9

FLASH_DATA1

FLASH_DATA8

FLASH_DATA0

FLASH_NOTOE

FLASH_NOTCSA

FLASH_ADDR1

R1055

4k7

FF_OE_NOT

NAND_E_NOT

FLASH_ADDR1

FLASH_ADDR2

NAND_AL

NAND_CL

FLASH_ADDR3

FLASH_RDNOTWR

NAND_OR_OUT_2

F253

60R

1

OE

2

Q0

3

D0

4

D1

5

Q1

74LCX374

6

Q2

7

D2

8

D3

9

Q3

GND CK

1

B

2

A

74LVC1G32

GND Y

C826

U168

U158

VCC

VCC

Q7

D7

D6

Q6

Q5

D5

D4

Q4

16V

100u

20

19

18

17

16

15

14

13

12

1110

5

43

C828

C842

C840

100n

100n

FF_CLK

16V

100n

VCC_F

FF_CLK

VCC_F3V3_VCC

16V

16V

VCC_F

VCC_F

NAND_WP_NOT

NAND_R_NOT

NAND_E_NOT

VCC_F

VCC_F

R894

10k

R941

47R

R948

47R

R943

47R

C843

NAND_CL

NAND_AL

NAND_W_NOT

R896

10k

R895

10k

NC

NAND FLASH

1

NC1

2

NC2

3

NC3

4

NC4

5

NC5

6

NC6

7

RB

8

R

9

E

10

NC7

11

NC8

12

VDD1

16V

100n

NAND512-A

13

VSS1

14

NC9

15

NC10

16

CL

17

AL

18

W

19

WP

20

NC11

21

NC12

22

NC13

23

NC14

NC15 NC16

U169

NC29

NC28

NC27

NC26

I/O7

I/O6

I/O5

I/O4

NC25

NC24

NC23

VDD2

VSS2

NC22

NC21

NC20

I/O3

I/O2

I/O1

I/O0

NC19

NC18

NC17

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

2524

FLASH_DATA7

FLASH_DATA6

FLASH_DATA5

FLASH_DATA4

16V

C850

100n

FLASH_DATA3

FLASH_DATA2

FLASH_DATA1

FLASH_DATA0

VCC_F

EEPROM

U151

24C32

1

E0

2
3

VCC
E1
E2

SCL
VSS SDA

WC

TP376
TP375

8
7
6
54

C892

16V

F254

100n

60R

FE1_SCL
FE1_SDA

FE1_SCL
FE1_SDA

A

5V_VCC

B

C

FLASH_ADDR15

D

E

FLASH_ADDR14

FLASH_ADDR13

FLASH_ADDR12

FLASH_ADDR10

FLASH_ADDR9

FLASH_ADDR8

FLASH_ADDR7

FLASH_ADDR6

FLASH_ADDR5

FLASH_ADDR4

FLASH_ADDR3

FLASH_ADDR2

Boot Straps For NOR Flash

FLASH_ADDR1 10k

FLASH_NOTCSA 10k

F

R916

10k

R918

10k

R917

10k

R915

10k

R899

10k

R897

10k

R898

10k

R921

10k

R920

10k

R919

10k

R922

10k

R924

10k

R925

10k

R903

10k

R902

10k

R907

10k

R906

10k

R905

R904

10k

R923

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

3V3_CI

VCC_F

FLASH_NOTCSB

FLASH_ADDR4

NAND_OR_OUT_1

FLASH_NOTCSB

F_ADDR4_INV

NAND_OR_OUT_2

FLASH_ADDR4

R1013

4k7

1

NC

2

A

74LVC1G04

GND Y

1

1A

2

1B

3

1Y

4

2A

74LVC32

5

2B

6

2Y

7

GND

U178

U175

VCC

VCC

16V

C851

100n

5

VCC_F

43

F_ADDR4_INV

FAST FLASHPROGRAMMING

U170

D

16V

C853

100n

14

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

VCC_F

FLASH_NOTOE

NAND_OR_OUT_1

NAND_R_NOT

FLASH_RDNOTWR

NAND_OR_OUT_1

NAND_W_NOT

VCC_F

FLASH_RDNOTWR

R1051

4k7

74V1G08

1

A

2

B
GND Y

VCC

5

43

C852

16V

100n

VCC_F

FLASH_WE

E

F

VESTEL

SCH NAME :
DRAWN BY :

STi7101 FLASH & EEPROM
ERTUG BAL

PROJECT NAME :

17mb37

87654321

A3

SHEET:

14-10-2009_09:10

OF:

1814

AX M

1 2 3 4 5 6 7 8

LMI SYSTEM MISCELLANEOUSLMI VIDEO

S245

S238

2k2

R1129

V1

V2

W1

W2

Y1

Y2

AA1

AA2

E2

E1

F2

F1

G2

G1

H2

H1

AD1

AD2

AE1

AE2

AF1

AF2

AG1

AG2

L2

L1

M2

M1

N2

N1

P2

P1

R2

Q168
BC847B

TXD_CON

RXD_CON

S_LMI_DATA0

S_LMI_DATA1

S_LMI_DATA2

S_LMI_DATA3

S_LMI_DATA4

S_LMI_DATA5

S_LMI_DATA6

S_LMI_DATA7

S_LMI_DATA8

S_LMI_DATA9

S_LMI_DATA10

S_LMI_DATA11

S_LMI_DATA12

S_LMI_DATA13

S_LMI_DATA14

S_LMI_DATA15

S_LMI_DATA16

S_LMI_DATA17

S_LMI_DATA18

S_LMI_DATA19

S_LMI_DATA20

S_LMI_DATA21

S_LMI_DATA22

S_LMI_DATA23

S_LMI_DATA24

S_LMI_DATA25

S_LMI_DATA26

S_LMI_DATA27

S_LMI_DATA28

S_LMI_DATA29

S_LMI_DATA30

S_LMI_DATA31

TP366

CN135

1

2

3

TP365

U180

SYSB_CLKIN120R

VCC

A14

V_LMI_DATA0

B14

V_LMI_DATA1

A15

V_LMI_DATA2

B15

V_LMI_DATA3

A16

V_LMI_DATA4

B16

V_LMI_DATA5

A17

V_LMI_DATA6

B17

V_LMI_DATA7

A1

V_LMI_DATA8

B2

V_LMI_DATA9

A2

V_LMI_DATA10

B3

V_LMI_DATA11

A3

V_LMI_DATA12

B4

V_LMI_DATA13

A4

V_LMI_DATA14

B5

V_LMI_DATA15

A20

V_LMI_DATA16

B20

V_LMI_DATA17

A21

V_LMI_DATA18

B21

V_LMI_DATA19

A22

V_LMI_DATA20

B22

V_LMI_DATA21

A23

V_LMI_DATA22

B23

V_LMI_DATA23

A7

V_LMI_DATA24

B8

V_LMI_DATA25

A8

V_LMI_DATA26

B9

V_LMI_DATA27

A9

V_LMI_DATA28

B10

V_LMI_DATA29

A10

V_LMI_DATA30

A11

V_LMI_DATA31

B11

C992

C739

10u

100n
10V

14

13

6A

6Y

5A

5Y

4A

4Y

XTAL1

12

XTAL2

11

XTAL2

R966

10

47R

9

8

XTAL1

F274

1k

SYSB_CLKIN_ALT

R1143

1M

X106

30MHz
C923
22p
50V

2V5_ST

XTAL2

C924
22p
50V

DCUTRIGGEROUT

V_LMI_ADDR0

V_LMI_ADDR1

V_LMI_ADDR2

V_LMI_ADDR3

V_LMI_ADDR4

V_LMI_ADDR5

V_LMI_ADDR6

V_LMI_ADDR7

V_LMI_ADDR8

V_LMI_ADDR9

V_LMI_ADDR10

V_LMI_ADDR11

V_LMI_ADDR12

V_LMI_DQM0

V_LMI_DQM1

V_LMI_DQM2

V_LMI_DQM3

V_LMI_DQS0

V_LMI_DQS1

V_LMI_DQS2

V_LMI_DQS3

V_LMI_NOTBANK0

V_LMI_NOTBANK1

V_LMI_CLK

V_LMI_CKEN

R1151

120k

V_LMI_VREF

V_LMI_NOTCAS

V_LMI_NOTCLK

V_LMI_NOTCS0

TP250

V_LMI_NOTRAS

SYSB_CLKOSC

E10

LMIVIDADD[0]

D10

LMIVIDADD[1]

E9

LMIVIDADD[2]

D9

LMIVIDADD[3]

D6

LMIVIDADD[4]

E6

LMIVIDADD[5]

D5

LMIVIDADD[6]

E5

LMIVIDADD[7]

D4

LMIVIDADD[8]

E7

LMIVIDADD[9]

D8

LMIVIDADD[10]

E8

LMIVIDADD[11]

D7

LMIVIDADD[12]

B18

LMIV_DMASK0

B6

LMIV_DMASK1

A19

LMIV_DMASK2

A6

LMIV_DMASK3

A18

LMIV_DSTROBE0

A5

LMIV_DSTROBE1

B19

LMIV_DSTROBE2

B7

LMIV_DSTROBE3

D14

LMIVIDBKSEL[0]

E13

LMIVIDBKSEL[1]

A13

LMIVIDCLK

D13

LMIVIDCLKEN

B12

LMIVIDREF

C11

LMIVIDVREF

D15

NOTLMIVIDCAS

B13

NOTLMIVIDCLK

D11

NOTLMIVIDCS[0]

E11

NOTLMIVIDCS[1]

E14

NOTLMIVIDRAS

E15

NOTLMIVIDWE

SYSA_CLKIN

STI7101YWC

XTAL1

XTAL2

XTAL2

R965

47R

X107

30MHz
C921
22p
50V

LMIVIDDATA[0]

LMIVIDDATA[1]

LMIVIDDATA[2]

LMIVIDDATA[3]

LMIVIDDATA[4]

LMIVIDDATA[5]

LMIVIDDATA[6]

LMIVIDDATA[7]

LMIVIDDATA[8]

LMIVIDDATA[9]

LMIVIDDATA[10]

LMIVIDDATA[11]

LMIVIDDATA[12]

LMIVIDDATA[13]

LMIVIDDATA[14]

4

LMIVIDDATA[15]

U160

LMIVIDDATA[16]

LMIVIDDATA[17]

LMIVIDDATA[18]

LMIVIDDATA[19]

LMIVIDDATA[20]

LMIVIDDATA[21]

LMIVIDDATA[22]

LMIVIDDATA[23]

LMIVIDDATA[24]

LMIVIDDATA[25]

LMIVIDDATA[26]

LMIVIDDATA[27]

LMIVIDDATA[28]

LMIVIDDATA[29]

LMIVIDDATA[30]

LMIVIDDATA[31]

LMIV_GNDCOMP

1

2

3

4

5

6

7

R1169

C922
22p
50V

1A

1Y

2A

2Y

74HCU04

3A

3Y

GND

CLOCKS RESET

S_LMI_ADDR0

S_LMI_ADDR1

A

B

C

D

S_LMI_ADDR2

S_LMI_ADDR3

S_LMI_ADDR4

S_LMI_ADDR5

S_LMI_ADDR6

S_LMI_ADDR7

S_LMI_ADDR8

S_LMI_ADDR9

S_LMI_ADDR10

S_LMI_ADDR11

S_LMI_ADDR12

S_LMI_DQM0

S_LMI_DQM1

S_LMI_DQM2

S_LMI_DQM3

S_LMI_DQS0

S_LMI_DQS1

S_LMI_DQS2

S_LMI_DQS3

S_LMI_NOTBANK0

S_LMI_NOTBANK1

S_LMI_CLK

S_LMI_CKEN

R1150

120k

S_LMI_VREF

S_LMI_NOTCAS

S_LMI_NOTCLK

S_LMI_NOTCS0

TP251

S_LMI_NOTRAS

S_LMI_RDNOTWR V_LMI_RDNOTWR

M4

LMISYSADD[0]

N5

LMISYSADD[1]

N4

LMISYSADD[2]

P5

LMISYSADD[3]

U4

LMISYSADD[4]

V5

LMISYSADD[5]

V4

LMISYSADD[6]

W5

LMISYSADD[7]

W4

LMISYSADD[8]

U5

LMISYSADD[9]

P4

LMISYSADD[10]

T5

LMISYSADD[11]

T4

LMISYSADD[12]

AB2

LMIS_DMASK0

J1

LMIS_DMASK1

AC1

LMIS_DMASK2

K2

LMIS_DMASK3

AB1

LMIS_DSTROBE0

J2

LMIS_DSTROBE1

AC2

LMIS_DSTROBE2

K1

LMIS_DSTROBE3

K4

LMISYSBKSEL[0]

L5

LMISYSBKSEL[1]

U1

LMISYSCLK

Y5

LMISYSCLKEN

R1

LMISYSREF

H5

LMISYSVREF

J4

NOTLMISYSCAS

U2

NOTLMISYSCLK

L4

NOTLMISYSCS[0]

M5

NOTLMISYSCS[1]

K5

NOTLMISYSRAS

J5

NOTLMISYSWE

12V_VCC

LMISYSDATA[10]

LMISYSDATA[11]

LMISYSDATA[12]

LMISYSDATA[13]

LMISYSDATA[14]

3

LMISYSDATA[15]

U160

16V

LMISYSDATA[16]

LMISYSDATA[17]

LMISYSDATA[18]

LMISYSDATA[19]

LMISYSDATA[20]

LMISYSDATA[21]

LMISYSDATA[22]

LMISYSDATA[23]

LMISYSDATA[24]

LMISYSDATA[25]

LMISYSDATA[26]

LMISYSDATA[27]

LMISYSDATA[28]

LMISYSDATA[29]

LMISYSDATA[30]

LMISYSDATA[31]

R1067

STI7101YWC

C854

100n

R1033

4k7UART_TXD

LMISYSDATA[0]

LMISYSDATA[1]

LMISYSDATA[2]

LMISYSDATA[3]

LMISYSDATA[4]

LMISYSDATA[5]

LMISYSDATA[6]

LMISYSDATA[7]

LMISYSDATA[8]

LMISYSDATA[9]

LMIS_GNDCOMP

R1119

75R

3k3

Q167
BC847B

E

UART_RXD

Q165

BC847B

F

UART DEBUG

R1066

3k3 3V3_VCC

R970

1k

C940
33p
50V

27k

R1072

UART_RXD

RXD_CON

TXD_CON

UART_TXD

R1130

470R
R886

10k

R880

10k

R888

10k

R885

10k

TP262

TP261

R883

10k

NOTRST

NOTASEBRK

RESET_7101

R881

10k

DCUTRIGGERIN

R878

10k

JTAG_PIN1

NOTASEBRK

NOTJTAGRST

AM30

AP31

AN31

AP30

AN30

AN5

AP5

AN22

AL22

G5

AL6

AM5

AN9

AP9

A29

C30

L31

AM31

E16

D20

E20

D19

D16

D17

D18

E19

S231

S232

TSBYTECLK_1

CI_CLK

RESET_DVB

3V3_VCC

U159

GND

LM809

ATAREF

ATARXN

ATARXP

ATATXN

ATATXP

DAA_C1A

DAA_C2A

EMIDMAREQ[0]

EMIDMAREQ[1]

NC1

NC2

NC3

NC4

NC5

STI7101YWC

NC6

NC7

NC8

NC9

NMI

NOT_TRST

NOTASEBRK

NOTRESETIN

RTCCLKIN

TRIGGERIN

TRIGGEROUT

WDOGRSTOUT

1

2

3

4

5

6

7

PONRST

R870

R998

1k

VCC

RST

231

R1071

3V3_VCC

DVB_RESET

U160

1A

1Y

2A

2Y

74HCU04

3A

3Y

GND

10k

C738
100n
10V

3k9

PONRST

SYSACLKIN

SYSBCLKIN

SYSBCLKINALT

SYSBCLKOSC

SYSCLKOUT

SYSITRQ[0]

SYSITRQ[1]

SYSITRQ[2]

SYSITRQ[3]

5

TMDSREF

TMDSTX0N

TMDSTX0P

TMDSTX1N

TMDSTX1P

TMDSTX2N

TMDSTX2P

TMDSTXCN

TMDSTXCP

TMUCLK

USBREF

100n

VCC

6A

6Y

U181

5A

5Y

4A

4Y

R1068

3k3

R1065

3k3

Q169
BC847B

F247

C821
100u
16V

3V3_VCC

R375

21

10k

R185

33R

2 1

TCK

TDI

TDO

TMS

USBDM

USBDP

C742

14

13

12

11

10

9

8

2

1

C1

AP27

E27

AN27

E17

AK25

AK26

AK27

AK28

D21

D22

E22

T32

T34

T33

R34

R33

P34

P33

U34

U33

E21

E18

AP25

AN25

AM25

C737
100n
10V

RESET_7101

Q166
BC847B

21

RESET_DVB

C251
100n
10V

SYSA_CLKIN

SYSB_CLKIN

SYSB_CLKIN_ALT

SYSB_CLKOSC

R887

10k

R1076

100R
R957

47R

R879

10k

R882

10k

TCK

TDI

TDO

R1124

75R

TMDSTX0N

TMDSTX0P

TMDSTX1N

TMDSTX1P

TMDSTX2N

TMDSTX2P

TMDSTXCN

TMDSTXCP

TMS

R884

10k

USB_DN

USB_DP

R1005

12k

F258

1k

CI_WAIT

FLASH_WAIT

FLASH_ADDR18

CI_REG

3V3_VCC

DVB_IRQ

CI_IRQ

3V3_VCC

VESTEL

SCH NAME :
DRAWN BY :

STi7101 LMI, MISC
HUSEYIN E. CETIN

R1155

8

TMS

TCK

TDI

TDO

R1020

4k7

R1054

4k7

R1048

4k7

R871

10k

R901

10k

R900

10k

R875

10k

R877

10k

R873

10k

R872

10k

R876

10k

R874

10k

1

2

3

R1154

1

2

3

10k

10k

R1

R2

R3

R4

R1

R2

R3

R4

CN136

7

6

54

8

7

6

54

FLASH_WAIT

CI_REG

NOTASEBRK

JTAG_PIN1

NOTRST

TDI

TCK

TMS

DCUTRIGGERIN

DCUTRIGGEROUT

21

43

65

87

109

1211

1413

1615

1817

2019

17mb37

TMDSTX2N

TMDSTX2P

TMDSTX1N

TMDSTX1P

TMDSTX0N

TMDSTX0P

TMDSTXCN

TMDSTXCP

3V3_VCC

3V3_VCC FLASH_ADDR18

3V3_VCC

3V3_VCC NOTJTAGRST

3V3_VCC

3V3_VCC

JTAG

JTAG_PIN1

DCUTRIGGERIN

DCUTRIGGEROUT

NOTASEBRK

NOTJTAGRST

NOTRST

PROJECT NAME :

SHEET:

14-10-2009_09:10

87654321

OF:

A

B

C

D

E

F

A3

1815

AX M

1 2 3 4 5 6 7 8

A

I2S_WS_DVB

B

C

1

2

3

I2S_DATA_DVB

R4

54

10k

R3

6

3

R1344

R2

7

2

R1

8

1

I2S_CLK_DVB

DVB_SPDIF

VID_OUT_GREEN

R1159

560R

C693

10u

R1343

10k

8

R1

7

R2

6

R3

54

R4

R1089

33R

R1091

33R

R1090

33R

R1079

100R

VID_OUT_BLUE

VID_OUT_CVBS

AUDIO & VIDEO EMI PIO

C27

AUDANAIREF

A27

AUDANAMLOUT

A28

AUDANAMROUT

B27

AUDANAPLOUT

B28

AUDANAPROUT

C28

AUDANAVBGFIL

D29

AUDDIGDATAIN

E28

AUDDIGLRCLKIN

D28

AUDDIGSTRBIN

E26

AUDLRCLKOUT

D26

AUDPCMCLKOUT

A25

AUDPCMOUT0

B25

AUDPCMOUT1

C25

AUDPCMOUT2

D25

AUDPCMOUT3

E25

AUDPCMOUT4

E24

AUDSCLKOUT

D24

AUDSPDIFOUT

E34

VIDANAB0OUT

A34

VIDANAC1OUT

C34

VIDANACV1OUT

F34

VIDANAG0OUT

B31

VIDANAGREXT0

B32

VIDANAGREXT1

E33

VIDANAIDUMPB0

A33

VIDANAIDUMPC1

VIDDIGOUT0

VIDDIGOUT1

VIDDIGOUT2

VIDDIGOUT3

VIDDIGOUT4

VIDDIGOUT5

VIDDIGOUT6

VIDDIGOUT7

VIDDIGOUT8

VIDDIGOUT9

VIDDIGOUT10

VIDDIGOUT11

1

VIDDIGOUT12

U160

STI7101YWC

VIDDIGOUT13

VIDDIGOUT14

VIDDIGOUT15

VIDDIGOUTHS

VIDDIGOUTVS

VIDANAIDUMPCV1

VIDANAIDUMPG0

VIDANAIDUMPR0

VIDANAIDUMPY1

VIDANAR0OUT

VIDANAREXT0

VIDANAREXT1

VIDANAY1OUT

L34

L33

K34

K33

J34

J33

H34

H33

U30

T31

T30

R31

R30

P31

P30

N31

M33

M34

C33

F33

D33

B33

D34

A31

A32

B34

MII_TXD0

MII_TXD1

MII_TXD2

MII_TXD3

MII_TX_EN

MII_MDIO

MII_MDC

MII_RX_CLK

MII_RXD0

MII_RXD1

MII_RXD2

MII_RXD3

MII_TX_CLK

MII_COL

MII_CRS

MII_MDINT

MII_RX_DV

MII_RX_ER

VID_OUT_RED

R1163

7k5

R1162

7k5

FLASH_ADDR1

FLASH_ADDR2

FLASH_ADDR3

FLASH_ADDR4

FLASH_ADDR5

FLASH_ADDR6

FLASH_ADDR7

FLASH_ADDR8

FLASH_ADDR9

FLASH_ADDR10

FLASH_ADDR11

FLASH_ADDR12

FLASH_ADDR13

FLASH_ADDR14

FLASH_ADDR15

FLASH_ADDR16

FLASH_ADDR17

FLASH_ADDR18

FLASH_ADDR19

FLASH_ADDR20

FLASH_ADDR21

FLASH_ADDR22

VDD_3V3

FLASH_RDNOTWR

R4

R3

3

33R

R2

2

R1

1

R1113

R4

R3

3

33R

R2

2

R1

1

R1109

R4

R3

3

33R

R2

2

R1

1

R1118

R4

R3

3

33R

R2

2

R1

1

R1108

R4

R3

3

33R

R2

2

R1

1

R1110

R944

47R

R945

47R

TP281

EMIBUSGNT

R1008

4k7

R968

47R

FLASH_WAIT

AL9

AK10

AL10

AK11

AL11

AK12

AL12

AK13

AL13

AK14

AL14

AK15

AL15

AK17

AL17

AK18

AL18

AK19

AL19

AK20

AL20

AK21

AL21

AM21

AM20

AN10

AK22

EMIADDR[1]

EMIADDR[2]

EMIADDR[3]

EMIADDR[4]

EMIADDR[5]

EMIADDR[6]

EMIADDR[7]

EMIADDR[8]

EMIADDR[9]

EMIADDR[10]

EMIADDR[11]

EMIADDR[12]

EMIADDR[13]

EMIADDR[14]

STI7101YWC

EMIADDR[15]

EMIADDR[16]

EMIADDR[17]

EMIADDR[18]

EMIADDR[19]

EMIADDR[20]

EMIADDR[21]

EMIADDR[22]

EMIADDR[23]

EMIBUSGNT

EMIBUSREQ

EMIRDNOTWR

EMITRDY/WAIT

54

6

7

8

54

6

7

8

54

6

7

8

54

6

7

8

54

6

7

8

EMIDATA[10]

EMIDATA[11]

2

EMIDATA[12]

U160

EMIDATA[13]

EMIDATA[14]

EMIDATA[15]

EMIFLASHCLK

NOTEMIBE[0]

NOTEMIBE[1]

EMIDATA[0]

EMIDATA[1]

EMIDATA[2]

EMIDATA[3]

EMIDATA[4]

EMIDATA[5]

EMIDATA[6]

EMIDATA[7]

EMIDATA[8]

EMIDATA[9]

NOTEMIBAA

NOTEMICSA

NOTEMICSB

NOTEMICSC

NOTEMICSD

NOTEMICSE

NOTEMILBA

NOTEMIOE

AP20

AP19

AP18

AP17

AP15

AP14

AP13

AP12

AN20

AN19

AN18

AN17

AN15

AN14

AN13

AN12

AN21

AP21

AP11

AN11

AK9

AL8

AM8

AP8

AK8

AP22

AP10

FL_DATA0

FL_DATA1

FL_DATA2

FL_DATA3

FL_DATA4

FL_DATA5

FL_DATA6

FL_DATA7

FL_DATA8

FL_DATA9

FL_DATA10

FL_DATA11

FL_DATA12

FL_DATA13

FL_DATA14

FL_DATA15

TP280

R967

47R EMI_NBAA

R959

47R

R969

47R FLASH_ADDR0

R934

47R

R936

47R

R958

47R

R1007

4k7

R1009

4k7

R946

47R

R955

47R FLASH_NOTOE

EMI_BE0

FLASH_NOTCSA

FLASH_NOTCSB

FLASH_NOTCSD

VDD_3V3

VDD_3V3

FLASH_NOTWE

C_RESET

AGC_S1

FF_OE_NOT

NAND_WP_NOT

FLASH_WP

USB_RESET

FE1_SCL

FE1_SDA

DVB_RXD

DVB_TXD

R1099

33R

R1082

100R

R1100

33R

R1092

33R

R1095

33R

R1085

33R

R952

47R

R953

47R

AM32

AP33

AN33

AP34

AN34

AM33

AM34

AL32

AL34

AL33

AK34

AK33

AJ34

AJ33

AH34

AH33

AJ30

AJ31

AH30

AH31

AG30

AG31

AE31

AE30

PIO0[0]

PIO0[1]

PIO0[2]

PIO0[3]

PIO0[4]

PIO0[5]

PIO0[6]

PIO0[7]

PIO1[0]

PIO1[1]

PIO1[2]

PIO1[3]

PIO1[4]

STI7101YWC

PIO1[5]

PIO1[6]

PIO1[7]

PIO2[0]

PIO2[1]

PIO2[2]

PIO2[3]

PIO2[4]

PIO2[5]

PIO2[6]

PIO2[7]

6

U160

PIO3[0]

PIO3[1]

PIO3[2]

PIO3[3]

PIO3[4]

PIO3[5]

PIO3[6]

PIO3[7]

PIO4[0]

PIO4[1]

PIO4[2]

PIO4[3]

PIO4[4]

PIO4[5]

PIO4[6]

PIO4[7]

PIO5[0]

PIO5[1]

PIO5[2]

PIO5[3]

PIO5[4]

PIO5[5]

PIO5[6]

PIO5[7]

AE32

AE34

AE33

AD34

AD33

AC34

AC33

AB34

AD32

AD30

AD31

AC30

AC31

AB30

AB31

AA30

AB33

AA34

AA33

Y34

Y33

AA31

Y30

Y31

R942

47R

R937

47R

R940

47R

R938

47R

R949

47R

R951

47R

R954

47R

CI_DETECT

R1210

47R

R1211

47R

A

IR_7101

CI_RESET

UART_RXD

UART_TXD

B

ETH_RESET

DVB_IRQ

RESET_T

C

USB_OC_1

USB_PWR_EN_1

D

E

5V_AV

F

VID_OUT_CVBS

R1146

150R

R1147

150R

R1149

150R

R1148

150R

VID_OUT_RED

VID_OUT_BLUE

VID_OUT_GREEN

VID_OUT_RED

VID_OUT_BLUE

VID_OUT_GREEN

16V

10u

C1149

VID_OUT_CVBS

VID_OUT_RED

VID_OUT_GREEN

VID_OUT_BLUE

1
2
3
4

C810

5V_VCC

C917

10p
L119

1u2

C994
150p
50V

S271

S275

S270

U173

TSH343

IN1
IN2
IN3
+VCC

10V

should be close to U129

220n

L117
22u

OUT1
OUT2
OUT3

GND

C995
150p
50V

S265

8
7
6
5

C736
100n
10V

R1164

should be close to U129should be close to ST7101

R1224

150R

R1226

150R

R1227

150R

R1225

150R

220R

220R

R1165

R1157

R1158

R1156

VID_OUT_CVBS

VID_OUT_RED

VID_OUT_GREEN

VID_OUT_BLUE

75R

75R

75R

220R

R1166

Q172
BC857B

S244

PR_OUT

PB_OUT

Y_OUT

DVB_CVBS

C752
47p
50V

PR_OUT

PB_OUT

Y_OUT

C988
68p
50V

C990
68p
50V

C991
68p
50V

F259

1k

F260

1k

F261

1k

C987
68p
50V

C989
68p
50V

C986
68p
50V

D170

5V_VCC 5V_AV

DVB_PR

DVB_PB

DVB_Y

F257

1k

VDD_3V3 4k7

FL_DATA0
FL_DATA8
FL_DATA1
FL_DATA9

FL_DATA2

FL_DATA10

FL_DATA3

FL_DATA11

FL_DATA4

FL_DATA12

FL_DATA5

FL_DATA13

FL_DATA6

FL_DATA14

FL_DATA7

FL_DATA15

R927

R926

R1019

R1039

R1012

R1024

R1102

1
2
3

R1111

1
2
3

R1101

1
2
3

R1103

1
2
3

10k

10k

4k7

4k7

4k7VDD_3V3

R1
R2
R3
R4

33R

R1
R2
R3
R4

33R

R1
R2
R3
R4

33R

R1
R2
R3
R4

33R

C5V1

8
7
6
54

8
7
6
54

8
7
6
54

8
7
6
54

C789
100p
50V

EMIBUSGNTVDD_3V3

FLASH_WAIT

FLASH_NOTCSAVDD_3V3

FLASH_NOTCSB

FLASH_NOTCSD

FLASH_DATA0
FLASH_DATA8
FLASH_DATA1
FLASH_DATA9

FLASH_DATA2
FLASH_DATA10
FLASH_DATA3
FLASH_DATA11

FLASH_DATA4
FLASH_DATA12
FLASH_DATA5
FLASH_DATA13

FLASH_DATA6
FLASH_DATA14
FLASH_DATA7
FLASH_DATA15

R1015

3V3_VCC FE1_SCL

3V3_VCC

3V3_VCC RESET_T4k7

3V3_VCC

3V3_VCC

3V3_STBY

4k7

R1047

4k7 FE1_SDA

R1056

R1046

4k7

R1034

R1014

4k7 ETH_RESET

R1217

4k73V3_VCC

R792

10k

R793

10k

IR_IN

UART_RXD3V3_VCC

UART_TXD4k7

USB_PWR_EN_1

TSBYTECLK_3

C751
47p
50V

IR_7101

Q158
BC848B

TS_DATA0_1

TS_DATA1_1

TS_DATA2_1

TS_DATA3_1

TS_DATA4_1

TS_DATA5_1

TS_DATA6_1

TS_DATA7_1

C_D0

C_D1

C_D2

C_D3

C_D4

C_D5

C_D6

C_D7

TSBYTECLK_1

TSVALID_1

TRANSPORT STREAM

AH5

TSIN0DATA[0]

AG4

TSIN0DATA[1]

AK1

TSIN0DATA[2]

AK2

TSIN0DATA[3]

AJ1

TSIN0DATA[4]

AJ2

TSIN0DATA[5]

AH1

TSIN0DATA[6]

AH2

TSIN0DATA[7]

AE5

TSIN1DATA[0]

AD4

TSIN1DATA[1]

AD5

TSIN1DATA[2]

AC4

TSIN1DATA[3]

AC5

TSIN1DATA[4]

AB4

TSIN1DATA[5]

AB5

TSIN1DATA[6]

AA4

TSIN1DATA[7]

AK6

TSIN0BYTECLK

AJ5

TSIN0BYTECLKVALID

VESTEL

SCH NAME :
DRAWN BY :

STi7101 A/V, PIO, EMI, TS
HUSEYIN E. CETIN

7

U160

STI7101YWC

TSIN0PACKETCLK

TSIN1PACKETCLK

TSIN2PACKETCLK

TSIN1BYTECLKVALID

TSIN2BYTECLKVALID

PROJECT NAME :

TSIN2DATA[0]

TSIN2DATA[1]

TSIN2DATA[2]

TSIN2DATA[3]

TSIN2DATA[4]

TSIN2DATA[5]

TSIN2DATA[6]

TSIN2DATA[7]

TSIN0ERROR

TSIN1ERROR

TSIN2ERROR

TSIN1BYTECLK

TSIN2BYTECLK

AP1

AN2

AN1

AM2

AM1

AL2

AL1

AL3

AH4

AE4

AP2

AJ4

AF4

AP3

AG5

AM3

AF5

AN3

17mb37

14-10-2009_09:10

87654321

TS_DATA0_3

TS_DATA1_3

TS_DATA2_3

TS_DATA3_3

TS_DATA4_3

TS_DATA5_3

TS_DATA6_3

TS_DATA7_3

TSPKTERR_1

C_ERR

TSPKTERR_3

TSPKTCLK_1

C_STRT

TSPKTCLK_3

C_CLK

TSBYTECLK_3

C_VAL

TSVALID_3

SHEET:

OF:

D

E

F

A3

1816

AX M

1 2 3 4 5 6 7 8

A

VDD_3V3

VDD_1V0

B

VDD_1V0

1V0_ST

2V5_ST

C

1V0_ST

2V5_ST

2V5_ST

1V0_ST

D

2V5_ST

2V6_ST

2V6_ST

E

2V5_ST

1V0_ST

1V0_ST

F

3V3_VCC

F266

1k

F265

1k

F246
330R

F270

1k

F269

1k

F268

1k

F267

1k

F273

1k

F262

1k

F239
330R

F240
330R

F276

1k

F277

1k

F252

60R

F242
330R

C1156

C728
100n
10V

C729
100n
10V

C981
1u
6V3

10u

C978
1u
6V3

C977
1u
6V3

C976
1u
6V3

C993
10u
10V

C1154
10u
10V

C974
470u
6V3

C973
470u
6V3

C1153
10u
10V

C1152
10u
10V

C782
220u
6V3

S_LMI_DLL_VDD

C791
100p
50V

V_LMI_DLL_VDD

C790
100p
50V

C735

C801

100n

100p

10V

50V

C730

10V

100n
10V

C732

C794

100n

100p

10V

50V

C733

C793

100n

100p

10V

50V

C731

C792

100n

100p

10V

50V

C798

C734

100p

100n

50V

10V

C795

C726

100p

100n

50V

10V

C767

C702

10n

100n

16V

10V

C765

C704

10n

100n

16V

10V

C719

C717

100n

100n

10V

10V

C804

C713 C803

100p

100n

50V

10V

C709
100n
10V 16V

F241

C788
220u
6V3

USB_VDD_1V0

VDD_AF_2V5

C797
100p
50V

VDD_SATA_OSC_1V0

USB_VDD_2V5

VDD_SATA_OSC_2V5

VDD_CKGA

VDD_ANA_2V5

VDD_S_LMI_2V6

VDD_V_LMI_2V6

VDD_CKG_2V5

C808
100p
50V

C720
100n
10V

C777

C716

10n

100n
10V

C1155

C772

100n

10n

10V

16V 10V

VDD_CKGB

100p
50V

C715
100n
10V

VDD_1V0

C780
10n
16V

C706

C771 C774

100n

10n
16V

C705
100n
10V

VDD_3V3
VDD_1V0

VDD_3V3

10n
16V

AK24

AM9
AM10
AM11
AM12
AM13
AM14
AM15

AP7

AN8

W30
AL24

F4
F5

G4
N16
N17
N18
N19
P17
P18
R13
R17
R18
R22
T13
T14
T21
T22
U13
U14
U21
U22
V13
V14
V21
V22
W13
W14
W21
W22
Y13
Y17
Y18
Y22

AA17
AA18
AB16
AB17
AB18
AB19
AF30
AK16
AL16
AM16
AM17
AM18
AM19
AN16
AP16

A30
B30
K31
C31
G31
D27
M32

VDDE3V3_11
VDDE3V3_12
VDDE3V3_13
VDDE3V3_14
VDDE3V3_15
VDDE3V3_16
VDDE3V3_17
VDDE3V3_18
VDDE3V3_19
VDDE3V3_20
TMDSVDDE3V3
USBVDDB3V3
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
AUD_GNDA
AUD_GNDAS
DGNDPLL80V0
FS0_GNDA
FS0_GNDD
GND_ANA_1
GND_ANA_2

VDD_3V3

AK23

AF34

AF33

AF32

VDDE3V3_7

VDDE3V3_8

VDDE3V3_9

VDDE3V3_10

GND_4

GND_5

GND_6

GND_7

N22

N21

N20

N15

G34

G33

AF31

VDDE3V3_4

VDDE3V3_5

VDDE3V3_6

GND_1

GND_2

GND_3

N14

N13H3AP6

C26

B26

A26

VDDE3V3_1

VDDE3V3_2

VDDE3V3_3

GNDE_47

GNDE_48

GNDE_49

AP4

AN6

VDD_ANA_2V5

VDD_CKG_2V5

VDD_ANA_2V5

VDD_CKG_2V5

VDD_AF_2V5

H32

E29

E31

D31

G32

AN7

AM7

VDDE2V5_5

VDDE2V5_4FS_ANA

VDDE2V5_AUD_ANA

VDDE2V5_FS0_ANA

VDDE2V5_VID_ANA

VDDE2V5_PLL80_ANA

GNDE_41

GNDE_42

GNDE_43

GNDE_44

GNDE_45

GNDE_46

AN4

AL5

AL4

AK5

AK4

AM6

AM4

TP227
TP228
TP273
TP249
TP238
TP226

TP248
TP247
TP255
TP252
TP256
TP258
TP277
TP246

AL7

AK7

AK3

AM23

VDDE2V5_1

VDDE2V5_2

VDDE2V5_3

VDDE2V5_4

GNDE_37

GNDE_38

GNDE_39

GNDE_40

AJ3

AH3

AG3

AF3

2V6

1

2V6_ST

1

VDDM

1

VDD_DMC

1

VDD_DMQ

1

VDD_S_LMI_2V6

1

VDD_V_LMI_2V6

2V5

1

2V5_ST

1

VDD_CKG_2V5

1

VDD_AF_2V5

1

VDD_ANA_2V5

1

VDD_SATA_OSC_2V5

1

USB_VDD_2V5

1

2V5A_FE

1

2V5_QAM

USB_VDD_2V5

VDD_SATA_OSC_2V5

VDD_CKG_2V5

L30

AN23

AN24

AM24

AM26

USBVDDP2V5

USBVSSC2V5

USBVSSP2V5

USBVDDBC2V5

SATAVDDOSC2V5

CKGB_4FS1_VCCA

GNDE_31

GNDE_32

GNDE_33

GNDE_34

GNDE_35

GNDE_36

T3R5R4R3P3N3M3L3K3

AE3

AD3

VDD_CKG_2V5

VDD_CKG_2V5

VDD_ANA_2V5

C2D2B1D1C3

M30

N30

B29

AUD_VCCA

AVDDPLL80V0

CKGB_4FS0_VCCA

GNDE_30

CKGA_PLL_VDDE2V5

CKGA_PLL1_AGNDPLL2V5

CKGA_PLL1_AVDDPLL2V5

CKGA_PLL2_AGNDPLL2V5

CKGA_PLL2_AVDDPLL2V5

GNDE_23

GNDE_24

GNDE_25

GNDE_26

GNDE_27

GNDE_28

GNDE_29

J3

E23

TP198
TP276
TP275
TP225
TP232
TP231
TP266
TP230
TP229
TP235
TP234
TP236

VDD_CKG_2V5

VDD_V_LMI_2V6

C29

E30

D30

E12

FS0_VCCA

DA_HD_0_VCCA

DA_SD_0_VCCA

LMIVIDVDDE2V5_10

GNDE_19

GNDE_20

GNDE_21

GNDE_22

D23

C24

C23

C22

3V3

1

3V3_VCC

1

AVDD_AU

1

AVDD_USB

1

3V3_HDMI

1

VDD_3V3

1

3V3_ETH

1

3V3A_USB

1

3V3D_FE

1

3V3_QAM

1

VCC_F

1

3V3_CI

1

3V3D_USB

C9C8C7C6C5

D12

C13

C10

LMIVIDVDDE2V5_6

LMIVIDVDDE2V5_7

LMIVIDVDDE2V5_8

LMIVIDVDDE2V5_9

C4

LMIVIDVDDE2V5_2

LMIVIDVDDE2V5_3

LMIVIDVDDE2V5_4

LMIVIDVDDE2V5_5

8

U160

STI7101YWC

GNDE_11

GNDE_12

GNDE_13

GNDE_14

GNDE_15

GNDE_16

GNDE_17

GNDE_18

C21

C20

C19

C18

C17

C16

C15

C14

B24

TP143

TP201

TP197
TP241
TP274
TP233
TP158

VDD_S_LMI_2V6

Y4Y3W3V3U3T2T1

AC3

AB3

AA5

AA3

LMISYSVDDE2V5_5

LMISYSVDDE2V5_6

LMISYSVDDE2V5_7

LMISYSVDDE2V5_8

LMISYSVDDE2V5_9

LMIVIDVDDE2V5_1

LMISYSVDDE2V5_10

LMISYSVDDE2V5_11

GNDE_3

GNDE_4

GNDE_5

GNDE_6

GNDE_7

GNDE_8

GNDE_9

GNDE_10

A24

U31

V30

AK32

AJ32

AH32

AG34

AG33

8V

1

8V_VCC

12V

1

12V_VCC 3V3_STBY

USB_VDD_1V0

W33

AP24

AL25

USBVDDP

TMDSVDDX

USBVDDBS

LMISYSVDDE2V5_1

LMISYSVDDE2V5_2

LMISYSVDDE2V5_3

LMISYSVDDE2V5_4

TMDSVSSSL

TMDSVSSX

USBVSSBS

USBVSSP

AGNDPLL80V0

GNDE_1

GNDE_2

D32

V33

AP23

AL23

U32

AG32

TP202

AA32

AC32

AB32

TMDSVDDD

TMDSVDDP

TMDSVDDSL

TMDSVSSCK

TMDSVSSD

TMDSVSSP

P32

N32

V32

5V_STBY

1

5V_STBY

W32

W34

Y32

W31

TMDSVDDC1

TMDSVDDC2

TMDSVDDCK

TMDSVSSC0

TMDSVSSC1

TMDSVSSC2

V34

N33

N34

R32

V31

AP29

AN29

TMDSVDD

TMDSVDDC0

SATAVDDT[0]

SATAVDDT[1]

SATAVSSR

SATAVSSREF

SATAVSST

TMDSGNDE

AP28

AM27

AN28

AL30

AL28

SATAVDDREF

SATAVSSOSC

AL27

AM28

TP242
TP142

TP239
TP240
TP144

5V

1

5V_VCC

1

5V_CI

1

5V_SPDIF

1

5V_AV

1

5V_TUN

VESTEL

SCH NAME :
DRAWN BY :

VDD_SATA_OSC_1V0

V_LMI_DLL_VDD

S_LMI_DLL_VDD

A12H4G30

K30

AM29

AL26

AL29

SATAVDDDLL

SATAVDDOSC

SATAVDDR[0]

SATAVDDR[1]

GNDE_VID_ANA

LMISYSDLL_VSS

LMIVIDDLL_VSS

SATAVSSDLL

C12G3J32

H30

FS0_VDDD

DVDDPLL80V0

LMISYSDLL_VDD

LMIVIDDLL_VDD

GNDE_4FS_ANA

GNDE_AUD_ANA

GNDE_FS0_ANA

GNDE_PLL80_ANA

K32

F32

E32

F31

F30

1V26_STBY

VDDC

1

1V26_STBY

3V3_STBY

VDDP
AVDD_33

1

PROJECT NAME :

STi7101 POWER
HUSEYIN E. CETIN

VDD_CKGA

VDD_CKGA

VDD_CKGB

E4E3F3

D3

J30

CKGB_4FS0_VDDD

CKGB_4FS1_VDDD

CKGA_PLL1_DGNDPLL1V0

CKGA_PLL1_DVDDPLL1V0

CKGA_PLL2_DGNDPLL1V0

CKGA_PLL2_DVDDPLL1V0

CKGB_4FS0_GNDA

CKGB_4FS0_GNDD

CKGB_4FS1_GNDA

CKGB_4FS1_GNDD

DA_HD_0_GNDA

DA_SD_0_GNDA

C32

H31

L32

J31

M31

TP260
TP259
TP243
TP257
TP244
TP279
TP278
TP237
TP253
TP254

GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74

1V0

USB_VDD_1V0
VDD_CKGA
VDD_CKGB
VDD_SATA_OSC_1V0
VDD_1V0
1V0D_FE1
1V0A_FE1
1V_QAM
S_LMI_DLL_VDD
V_LMI_DLL_VDD

17mb37

14-10-2009_09:10

P13
P14
P15
P16
P19
P20
P21
P22
R14
R15
R16
R19
R20
R21
T15
T16
T17
T18
T19
T20
U15
U16
U17
U18
U19
U20
V15
V16
V17
V18
V19
V20
W15
W16
W17
W18
W19
W20
Y14
Y15
Y16
Y19
Y20

Y21
AA13
AA14
AA15
AA16
AA19
AA20
AA21
AA22
AB13
AB14
AB15
AB20
AB21
AB22
AK29
AK30
AK31
AL31
AM22
AN26
AN32
AP26
AP32

SHEET:

17 18

87654321

A

B

C

D

E

F

A3

OF:

AX M

1 2 3 4 5 6 7 8

A

3V3_ETH

1k

1k

R1181

LED_L

VCCA2

35

LED_C

GNDA3

14

1k

R1178

34

LED_S

IREF

15

33

TEST_SE

MDIX_DIS

RESET

PWR_DWN

GNDE1

GNDA5

GNDA4

VCCA4

VCCA3

16

32

SCLK

31

CF2

30

29

RIP

28

27

26

TEST

25

24

23

TXN

22

NC2

21

TXP

20

19

RXP

18

RXN

17

3V3_ETH_A

S230

S229

ETH_TXN

3V3_ETH_A

ETH_TXP

ETH_RXP

ETH_RXN

3V3_ETH_A

RESET_DVB

ETH_RESET

Place these resistors
close to STE100P

47R

R1132

ETH_TXP

ETH_TXN

ETH_RXP

ETH_RXN

47R

47R

R1134

R1131

3V3_ETH_A

47R

R1133

3V3_ETH_A

10R

R1170

TR1

16

R1125

15

75R

13

14

12

11

R1121 R1126

10

75R

98

C996

S255

75R

R1120

75R

1kV

1n

C1005

S247

50V

15n

C890

1

2

4

3

5

6

7

Place these capacitors

16V

close to transformer

100n

Ethernet lines must be 100ohm differential pairs

1

TX+

2

TX-

3

RX+

4

GND1

5

GND2

6

RX-

7

GND3

8

GND4

JK108

1k

39

GNDE2

VCCA1

10

1k

3V3_ETH

R1186

R1190

37

38

VDD

LED_R10

GNDA2X2X1

12

11

R1189

36

LED_TR

13

MII_RXD1

MII_RXD2

MII_RX_DV

MII_RXD0

45

46

47

B

MII_RX_CLK

MII_RX_ER

S262

MII_TX_CLK

MII_TX_EN

MII_TXD0

MII_TXD1

C

MII_MDINT

3V3_ETH

R1187

3V3_ETH

3V3_ETH

R1188

R1191

R1192

MII_TXD2

MII_TXD3

MII_COL

MII_CRS

R999

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

RX_CLK

GNDE3

RXD4_RX_ER

TXD4_TX_ER

TX_CLK

TX_EN

TXD0

TXD1

TXD2

TXD3

COL

CRS

MDINT

VDD2

CFG1

CFG0

48

RX_DV

MF4

1

RXD0

MF3

2

RXD1

MF2

3

4

3V3_ETH

44

VDD1

RXD2

MF1

MF0

5

MII_RXD3

MII_MDC

42

43

MDC

RXD3

U186

STE100P

FDE

GNDA1

7

6

MII_MDIO

40

41

MDIO

NC1

9

8

D

S263

A

B

C

D

3V3_ETH_A

R1145

1M

41

3

25MHz

R1183

R1182

R1180

R1179

R1196

E

3V3_ETH

3V3_ETH

3V3_ETH

R1195

R1185

R1184

3V3_ETH

R1198

R1197

3V3_ETH

R1194

R1193

3V3_ETH

C1016

22p

50V

X1

2

F

3V3_ETH_A

R1208

C1017
22p
50V

3V3_VCC

3V3_VCC

F271

1k

F278

1k

C998

6V3

10u

C1004

C891

6V3

10u

16V

100n

C859

C1014

16V

100n

100n

C866

16V

16V

100n

3V3_ETH

3V3_ETH_A

VESTEL

SCH NAME :
DRAWN BY :

PROJECT NAME :

ETHERNET
ERTUG BAL

17mb37

14-10-2009_09:10

87654321

SHEET:

A3

OF:

18 18

E

F

AX M

5k1

220k

R1207

PARTS LIST

N o. C om ponent D escription

1

VE20432333 BACK CVR.AS.22880 SP-BO&DVD&FBT(WO/IP

2

VE20444080 BUTTON FUNCTION MB25 W/ST.BY(HOTST.-BLK

3

VE20500505 FRONT 22890 (B.C.BL/P-V(S)L-SANYO

4

VE20439864 LENS LED 19890 (PEARL SILVER/P)

5

VE20449329 LENS LED 19890 MILKY%30(I)

6

VE20454403 CN.A.FFC 30P/300 P=1MM LVDS(22"MB25

7

VE30064829 TFT LCD 216W LG LC220WXE TBA1 RoHS

8

VE20447336 MD.ASY.17LD104-19-22890 (MB25)BLUE

9

VE20484013 CHS.ASSY.17MB37-52K12315372211115B6

10

VE20492338 MD.ASY.17IPS15-4-22"(MB25)(AVUSTRALYA)

11

VE30066607 HCN DL08DIVX G1WO\USBMMCSAFE-ROHS (N.Hw)

12

VE30064217 5P/200 FLT W/C UL2468AWG26 ROHS

13

VE30064503 CNAS 12P/350 SHL W/DC DVD UL2464#26 ROHS

14

VE20463632 SPK.AS.19820/2/850(16/9(DVD(R/L)(MB37)BL

15

VE30064154 CNAS 20P/100 SIS W/DC UL1007AWG24RoHS

16

VE20444098 REMOTE CONTROL

PART LIST EXPLANATION

1. VE20432333 BACK COVER

2. VE20444080 BUTTON FUNCTION

3. VE20500505 FRONT 22890 (B.C.BL/P-V(S)L-SANYO

4. VE20439864 LENS LED 19890 (PEARL SILVER/P)

5. VE20449329 LENS LED 19890 MILKY%30(I)

Button Function

VE20454403

LVDS

CABLE

6. VE20454403 CABLE FFC 30P/300 P=1MM LVDS(22"MB25

7. VE30064829 TFT LCD

8. VE20447336 MD.ASY.17LD104-19-22890 (MB25)BLUE

9. VE20484013 CHASSIS

10. VE20492338 POWER SUPPLY IPS BOARD

11. VE30066607 DVD LOADER

12. VE30064217 CNAS 5P/200 FLT W/C UL2468AWG26 ROHS. The cable from led
board to chassis (fix C119 position in chassis)

13. VE30064503 CNAS 12P/350 SHL W/DC DVD UL2464#26 ROHS. The cable from
DVD to chassis (fix C143 position in chassis)

14. VE20463632 Double Speaker.This code also includes the Speaker cable from
speaker to Chassis and this cable should be fixed CN115 position on chassis side.

15. VE30064154 CNAS 20P/100 SIS W/DC UL1007AWG24RoHS. The cable from
Power board to chassis (fix C137 position in chassis)

June/2008