SanDisk SDSDB-16, SDSDB-32, SDSDJ-64, SDSDJ-128, SDSDJ-256 Product Manual

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SanDisk Secure Digital Card

Product Manual

Version 1.9

Document No. 80-13-00169

December 2003

Corporate Headquarters • 140 Caspian Court • Sunnyvale, CA 94089

SanDisk Corporation

Phone (408) 542-0500 • Fax (408) 542-0503

www.sandisk.com

SanDisk® Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages. See “Limited Warranty and Disclaimer of Liability.”

This document is for information use only and is subject to change without prior notice. SanDisk Corporation assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this material. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of SanDisk Corporation.

SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation.

Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

SanDisk products are covered or licensed under one or more of the following U.S. Patent Nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and pending.

Lit. No. 80-13-00169 Rev. 1.9 12/2003 Printed in U.S.A.

Revision History

• Revision 1.0 dated 6/2001

• Revision 1.1 dated 11/2001

• Revision 1.2 dated 6/2002

• Revision 1.3 dated 7/2002

• Revision 1.4 dated 11/2002—minor editorial change.

• Revision 1.5 dated 3/2003— changed power requirements in Section 2.3, Table 2.3; updated addresses in Appendix A; adjusted footers and front matter.

• Revision 1.6 dated 8/2003—added 512- and 1024-Mb capacities; updated “Limited Warranty” appendix; added “Disclaimer

of Liability” appendix.

• Revision 1.7 dated 9/2003—minor revisions; added appnote as Appendix A

• Revision 1.8 dated 11/2003—changed VDD read/write values in Section 2 and Table 3-10

• Revision 1.9 dated 12/2003—changed VDD read/write values in Table 3-10

−

initial release.

−

minor editorial and technical changes.

−

minor editorial and technical changes.

−

minor editorial and technical changes.

Table of Contents

1. Introduction to the SD Card ............................................................................................................................... 1-1

1.1. Scope................................................................................................................................................. 1-2

1.2. Product Models ................................................................................................................................. 1-2

1.3. System Features................................................................................................................................. 1-2

1.4. SD Card Standard.............................................................................................................................. 1-3

1.5. Functional Description ...................................................................................................................... 1-3

1.5.1. Flash Technology Independence............................................................................................. 1-4

1.5.2. Defect and Error Management................................................................................................ 1-4

1.5.3. Copyright Protection ............................................................................................................... 1-4

1.5.4. Endurance ............................................................................................................................... 1-5

1.5.5. Wear Leveling......................................................................................................................... 1-5

1.5.6. Using the Erase Command...................................................................................................... 1-5

1.5.7. Automatic Sleep Mode............................................................................................................ 1-5

1.5.8. Hot Insertion ........................................................................................................................... 1-5

1.5.9. SD Card—SD Bus Mode ........................................................................................................ 1-6

1.5.9.1. SD Card Standard Compliance .............................................................................. 1-6

1.5.9.2. Negotiating Operation Conditions ......................................................................... 1-6

1.5.9.3. Card Acquisition and Identification....................................................................... 1-6

1.5.9.4. Card Status............................................................................................................. 1-6

1.5.9.5. Memory Array Partitioning.................................................................................... 1-7

1.5.9.6. Read and Write Operations.................................................................................... 1-9

1.5.9.7. Data Transfer Rate................................................................................................. 1-9

1.5.9.8. Data Protection in the Flash Card .......................................................................... 1-10

1.5.9.9. Erase ...................................................................................................................... 1-10

1.5.9.10. Write Protection................................................................................................... 1-10

1.5.9.11. Copy Bit............................................................................................................... 1-10

1.5.9.12. The CSD Register ................................................................................................ 1-10

1.5.10. SD Card—SPI Mode............................................................................................................. 1-10

1.5.10.1. Negotiating Operating Conditions ....................................................................... 1-11

1.5.10.2. Card Acquisition and Identification..................................................................... 1-11

1.5.10.3. Card Status...........................................................................................................1-11

1.5.10.4. Memory Array Partitioning.................................................................................. 1-11

1.5.10.5. Read and Write Operations.................................................................................. 1-11

1.5.10.6. Data Transfer Rate............................................................................................... 1-11

1.5.10.7. Data Protection in the SD Card............................................................................ 1-11

1.5.10.8. Erase .................................................................................................................... 1-11

1.5.10.9. Write Protection................................................................................................... 1-12

1.5.10.10. Copyright Protection.......................................................................................... 1-12

2. Product Specifications ........................................................................................................................................ 2-1

2.1. System Environmental Specifications............................................................................................... 2-1

2.2. Reliability and Durability.................................................................................................................. 2-1

2.3. Typical Card Power Requirements.................................................................................................... 2-2

2.4. System Performance.......................................................................................................................... 2-2

2.5. System Reliability and Maintenance................................................................................................. 2-2

2.6. Physical Specifications...................................................................................................................... 2-3

3. SD Card Interface Description ........................................................................................................................... 3-1

3.1. General Description of Pins and Registers........................................................................................ 3-1

3.1.1. Pin Assignments in SD Card Mode ........................................................................................ 3-1

Table of Contents

3.1.2. Pin Assignments in SPI Mode................................................................................................. 3-2

3.2. SD Bus Topology.............................................................................................................................. 3-3

3.2.1. Power Protection ..................................................................................................................... 3-5

3.3. SPI Bus Topology ............................................................................................................................. 3-5

3.3.1. Power Protection ..................................................................................................................... 3-6

3.4. Electrical Interface ............................................................................................................................ 3-6

3.4.1. Power-up ................................................................................................................................. 3-7

3.4.2. Bus Operating Conditions....................................................................................................... 3-8

3.4.3. Bus Signal Line Load.............................................................................................................. 3-8

3.4.4. Bus Signal Levels.................................................................................................................... 3-9

3.4.5. Bus Timing.............................................................................................................................. 3-10

3.5. SD Card Registers ............................................................................................................................. 3-11

3.5.1. Operating Conditions Register (OCR) .................................................................................... 3-11

3.5.2. Card Identification (CID) Register.......................................................................................... 3-12

3.5.3. CSD Register........................................................................................................................... 3-13

3.5.4. SCR Register........................................................................................................................... 3-19

3.5.5. Status Register......................................................................................................................... 3-20

3.5.6. SD Status................................................................................................................................. 3-23

3.5.7. RCA Register .......................................................................................................................... 3-23

3.5.8. SD Card Registers in SPI Mode.............................................................................................. 3-24

3.6. Data Interchange Format and Card Sizes.......................................................................................... 3-24

4. Secure Digital (SD) Card Protocol Description.................................................................................................. 4-1

4.1. SD Bus Protocol................................................................................................................................ 4-1

4.2. Protocol’s Functional Description..................................................................................................... 4-4

4.3. Card Identification Mode .................................................................................................................. 4-5

4.3.1. Reset........................................................................................................................................ 4-6

4.3.2. Operating Voltage Range Validation ...................................................................................... 4-7

4.3.3. Card Identification Process ..................................................................................................... 4-7

4.4. Data Transfer Mode .......................................................................................................................... 4-8

4.4.1. Wide Bus Selection/Deselection ............................................................................................. 4-10

4.4.2. Data Read Format ................................................................................................................... 4-10

4.4.3. Data Write Format .................................................................................................................. 4-11

4.4.4. Write Protect Management ..................................................................................................... 4-13

4.4.4.1. Mechanical Write Protect Switch .......................................................................... 4-13

4.4.4.2. Card’s Internal Write Protection (Optional) .......................................................... 4-13

4.4.5. Application Specific Commands............................................................................................. 4-13

4.5. Clock Control .................................................................................................................................... 4-14

4.6. Cyclic Redundancy Codes (CRC)..................................................................................................... 4-15

4.7. Error Conditions................................................................................................................................ 4-17

4.7.1. CRC and Illegal Command ..................................................................................................... 4-17

4.7.2. Read, Write and Erase Time-out Conditions .......................................................................... 4-17

4.8. Commands......................................................................................................................................... 4-17

4.8.1. Command Types ..................................................................................................................... 4-18

4.8.2. Command Format.................................................................................................................... 4-18

4.8.3. Command Classes ................................................................................................................... 4-18

4.8.4. Detailed Command Description.............................................................................................. 4-20

4.9. Card State Transition Table............................................................................................................... 4-24

4.10. Responses........................................................................................................................................ 4-25

4.11. Timings ........................................................................................................................................... 4-27

4.11.1. Command and Response....................................................................................................... 4-27

4.11.2. Data Read.............................................................................................................................. 4-28

Table of Contents

4.11.3. Data Write............................................................................................................................. 4-29

4.11.4. Timing Values....................................................................................................................... 4-32

5. SPI Protocol Definition ...................................................................................................................................... 5-1

5.1. SPI Bus Protocol ............................................................................................................................... 5-1

5.1.1. Mode Selection ....................................................................................................................... 5-1

5.1.2. Bus Transfer Protection .......................................................................................................... 5-2

5.1.3. Data Read................................................................................................................................ 5-2

5.1.4. Data Write............................................................................................................................... 5-3

5.1.5. Erase and Write Protect Management..................................................................................... 5-4

5.1.6. Read CID/CSD Registers........................................................................................................ 5-4

5.1.7. Reset Sequence ....................................................................................................................... 5-5

5.1.8. Clock Control.......................................................................................................................... 5-5

5.1.9. Error Conditions...................................................................................................................... 5-6

5.1.9.1. CRC and Illegal Commands .................................................................................. 5-6

5.1.9.2. Read, Write and Erase Time-out Conditions ......................................................... 5-6

5.1.10. Memory Array Partitioning................................................................................................... 5-8

5.1.11. Card Lock/Unlock................................................................................................................. 5-8

5.1.12. Application Specific Commands...........................................................................................5-8

5.1.13. Copyright Protection Commands.......................................................................................... 5-8

5.2. SPI Command Set ............................................................................................................................. 5-8

5.2.1. Command Format.................................................................................................................... 5-8

5.2.2. Command Classes ................................................................................................................... 5-9

5.2.2.1. Detailed Command Description............................................................................. 5-9

5.2.3. Responses................................................................................................................................ 5-12

5.2.3.1. Format R1 ..............................................................................................................5-13

5.2.3.2. Format R1b ............................................................................................................ 5-13

5.2.3.3. Format R2 ..............................................................................................................5-13

5.2.3.4. Format R3 ..............................................................................................................5-14

5.2.3.5. Data Response ....................................................................................................... 5-15

5.2.4. Data Tokens ............................................................................................................................ 5-15

5.2.5. Data Error Token .................................................................................................................... 5-16

5.2.6. Clearing Status Bits................................................................................................................. 5-16

5.3. Card Registers ................................................................................................................................... 5-16

5.4. SPI Bus Timing Diagrams................................................................................................................. 5-16

5.4.1. Command/Response................................................................................................................ 5-17

5.4.2. Data Read................................................................................................................................ 5-18

5.4.3. Data Write............................................................................................................................... 5-18

5.4.4. Timing Values......................................................................................................................... 5-19

5.5. SPI Electrical Interface...................................................................................................................... 5-19

5.6. SPI Bus Operating Conditions .......................................................................................................... 5-19

5.7. Bus Timing........................................................................................................................................ 5-19

Appendix A. Application Note............................................................................................................................... A-1

Host Design Considerations: NAND MMC and SD-based Products

Introduction.............................................................................................................................................. A-1

Timing...................................................................................................................................................... A-1

Timing specifications ............................................................................................................................... A-1

Read access and program times................................................................................................................ A-1

Interface.................................................................................................................................................... A-2

Read/Write Mode Selection ..................................................................................................................... A-4

Power and Clock Control ......................................................................................................................... A-4

Initialization Algorithm............................................................................................................................ A-5

Table of Contents

File System Support ................................................................................................................................. A-5

Appendix B. Ordering Information ........................................................................................................................ B-1

Appendix C. SanDisk Worldwide Sales Offices .................................................................................................... C-1

Appendix D. Limited Warranty.............................................................................................................................. D-1

Appendix E. Disclaimer of Liability ...................................................................................................................... E-1

1. Introduction to the SD Card

The Secure Digital Card is a flash-based memory card that is specifically designed to meet the security, capacity, performance and environmental requirements inherent in newly emerging audio and video consumer electronic devices. The SD Card includes a copyright protection mechanism that complies with the security of the SDMI standard, and is faster and capable of higher Memory capacity. The SD Card security system uses mutual authentication and a “new cipher algorithm” to protect from illegal usage of the card content. A non-secured access to the user‘s own content is also available. The physical form factor, pin assignment and data transfer protocol are forward compatible with the SD Card, with some additions.

The SD Card communication is based on an advanced nine-pin interface (Clock, Command, 4xData and 3xPower lines) designed to operate in a low voltage range. The communication protocol is defined as part of this specification. The SD Card host interface supports regular MultiMediaCard operation as well. In other words, MultiMediaCard forward compatibility was kept. Actually the main difference between SD Card and MultiMediaCard is the initialization process. The SD Card specifications were originally defined by MEI (Matsushita Electric Company), Toshiba Corporation and SanDisk Corporation. Currently, the specifications are controlled by the Secure Digital Association (SDA). The SanDisk SD Card was designed to be compatible with the SD Card Physical Specification.

The SD Card interface allows for easy integration into any design, regardless of microprocessor used. For compatibility with existing controllers, the SanDisk SD Card offers, in addition to the SD Card interface, an alternate communication protocol, which is based on the SPI standard.

The current SD Card provides up to 1024 million bytes of memory using flash memory chips, which were designed especially for use in mass storage applications. In addition to the mass storage specific flash memory chip, the SD Card includes an on-card intelligent controller which manages interface protocols, security algorithms for copyright protection, data storage and retrieval, as well as Error Correction Code (ECC) algorithms, defect handling and diagnostics, power management and clock control.

Data In/Out

Control

SanDisk SD Card

Flash

Modules

SD Bus/SPI Bus

Interface

SanDisk

Single Chip

Controller

Figure 1-1. SD Card Block Diagram

Introduction to the SD Card

1.1. Scope

This document describes the key features and specifications of the SD Card, as well as the information required to interface this product to a host system.

1.2. Product Models

The SD Card is available in the capacities shown in Table 1-1.

Table 1-1. SD Card Capacities

Model No. Capacities

SDSDB-16 16 MB

SDSDB-32 32 MB

SDSDJ-64 64 MB

SDSDJ-128 128 MB

SDSDJ-256 256 MB

SDSDJ-512 512 MB

SDSDJ-1024 1024 MB

SDSDB = Binary NAND technology. SDSDJ = Multi Level Cell (MLC) NAND technology.

1.3. System Features

The SD Card provides the following features:

• Up to 1-GB of data storage.

• SD Card protocol compatible.

• Supports SPI Mode.

• Targeted for portable and stationary applications for secured (copyrights protected) and non-secured

data storage.

• Voltage range:

− Basic communication (CMD0, CMD15, CMD55, ACMD41): 2.0—3.6V.

− Other commands and memory access: 2.7—3.6V.

• Variable clock rate 0—25 MHZ.

• Up to 12.5 MB/sec data transfer rate (using 4 parallel data lines).

• Maximum data rate with up to 10 cards.

• Correction of memory field errors.

• Copyrights Protection Mechanism—Complies with highest security of SDMI standard.

• Password Protected of Cards (not on all models).

• Write Protect feature using mechanical switch.

• Built-in write protection features (permanent and temporary).

• Card Detection (Insertion/Removal).

• Application specific commands.

Introduction to the SD Card

• Comfortable erase mechanism.

The performance of the communication channel is described in Table 1-2.

Table 1-2. SD Bus/SPI Bus Comparison

SD Card Using SD Bus SD Card Using SPI Bus

Six-wire communication channel (clock, command, 4 data lines).

Error-protected data transfer. Optional non-protected data transfer mode available.

Single or multiple block oriented data transfer. Single or multiple block oriented data transfer.

Three-wire serial data bus (Clock, dataIn, dataOut) + card specific CS signal (hardwired card selection).

1.4. SD Card Standard

SanDisk SD Cards are fully compatible with the following SD Card Physical Layer Specification standard:

The SD Card Physical Layer System Specification, Version 1.01

This specification may be obtained from:

SD Card Association 53 Muckelemi St. P.O. Box 189 San Juan Bautista, CA 95045-0189 USA Phone: 831-623-2107 Fax: 831-623-2248 Email: rcreech@sdcard.org http://www.sdcard.org

1.5. Functional Description

SanDisk SD Cards contain a high level, intelligent subsystem as shown in Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities not found in other types of memory cards. These capabilities include:

• Host independence from details of erasing and programming flash memory.

• Sophisticated system for managing defects (analogous to systems found in magnetic disk drives).

• Sophisticated system for error recovery including a powerful error correction code (ECC).

• Power management for low power operation.

Introduction to the SD Card

1.5.1. Flash Technology Independence

The 512-byte sector size of the SD Card is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the SD Card. This command contains the address. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the SD Card uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the SD Card today will be able to access future SanDisk SD Cards built with new flash technology without having to update or change host software.

1.5.2. Defect and Error Management

SD Cards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. SD Cards do a read after write under margin conditions to verify that the data is written correctly. In the rare case that a bit is found to be defective, SD Cards replace this bad bit with a spare bit within the sector header. If necessary, SD Cards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.

The SD Card’s soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, SD Cards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ a powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems. These defect and error management systems coupled with the solid-state construction give SD Cards unparalleled reliability.

1.5.3. Copyright Protection

A detailed description of the Copyright Protection mechanism and related security SD Card commands can be found in the SD Card Security Specification document from the SD Card Association. All SD Card security related commands operate in the data transfer mode.

As defined in the SDMI specification, the data content that is saved in the card is saved already encrypted and it passes transparently to and from the card. No operation is done on the data and there is no restriction to read the data at any time. Associated with every data packet (song, for example) that is saved in the unprotected memory there is a special data that is saved in a protected memory area. For any access (any Read, Write or Erase command) from/to the data in the protected area. For an authentication procedure is done between the card and the connected device, either the LCM (PC for example) or the PD (portable device, such as SD player). After the authentication process passes, the card is ready to accept or give data from/to the connected device. While the card is in the secured mode of operation (after the authentication succeeded) the argument and the associated data that is sent to the card or read from the card are encrypted. At the end of the Read, Write or Erase operation, the card gets out automatically of its secured mode.

Introduction to the SD Card

1.5.4. Endurance

SanDisk SD Cards have an endurance specification for each sector of 100,000 writes typical (reading a logical sector is unlimited). This far exceeds what is typically required in nearly all applications of SD Cards. For example, even very heavy use of the SD Card in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s lifetime. For instance, it would take over 10 years to wear out an area on the SD Card on which a file of any size (from 512 bytes to maximum capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.

With typical applications, the endurance limit is not of any practical concern to the vast majority of users.

1.5.5. Wear Leveling

Wear-leveling is an intrinsic part of the Erase Pooling functionality of SD using NAND memory. The SD Card’s Wear Level command is supported as a NOP operation to maintain backward compatibility with existing software utilities.

1.5.6. Using the Erase Command

The Erase (sector or group) command provides the capability to substantially increase the write performance of the SD Card. Once a sector has been erased using the Erase command, a write to that sector will be much faster. This is because a normal write operation includes a separate sector erase prior to write.

1.5.7. Automatic Sleep Mode

A unique feature of the SanDisk SD Card (and other SanDisk products) is automatic entrance and exit from sleep mode. Upon completion of an operation, the SD Card will enter the sleep mode to conserve power if no further commands are received within 5msec. The host does not have to take any action for this to occur. In most systems, the SD Card is in sleep mode except when the host is accessing it, thus conserving power.

When the host is ready to access the SD Card and it is in sleep mode, any command issued to the SD Card will cause it to exit sleep and respond.

1.5.8. Hot Insertion

Support for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA and MMCA devices to allow for hot insertion.

Introduction to the SD Card

1.5.9. SD Card—SD Bus Mode

The following sections provide valuable information on the SC Card in SD Bus mode.

1.5.9.1. SD Card Standard Compliance

The SD Card is fully compliant with SD Card Physical Layer Standard Specification V1.01. The structure of the Card Specific Data (CSD) register is compliant with CSD Structure 1.0.

1.5.9.2. Negotiating Operation Conditions

The SD Card supports the operation condition verification sequence defined in the SD Card standard specifications. Should the SD Card host define an operating voltage range, which is not supported by the SD Card it will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again.

In Addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.

1.5.9.3. Card Acquisition and Identification

The SD Card bus is a single master (SD Card host application) and multi-slaves (cards) bus. The Clock and Power lines are common to all cards on the bus. During the identification process, the host accesses each card separately through its own command lines. The SD Card’s CID register is pre-programmed with a unique card identification number, which is used during the identification procedure.

In addition, the SD Card host can read the card’s CID register using the READ_CID SD Card command. The CID register is programmed during the SD Card testing and formatting procedure, on the manufacturing floor. The SD Card host can only read this register and not write to it.

An internal pull-up resistor on the DAT3 line may be used for card detection (insertion/removal). The resistor can be disconnected during data transfer (using ACMD42). Additional practical card detection methods can be found in SD Physical Specification’s Application Notes given by the SDA.

1.5.9.4. Card Status

The card status is separated into the following two fields:

• Card Status is stored in a 32-bit status register that is sent as the data field in the card respond to host

commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.

• SD_Status is stored in 512 bits that are sent as a single data block after it was requested by the host

using the SD_STATUS (ACMD13) command. SD_STATUS contains extended status bits that relate to BUS_WIDTH, security related bits and future specific applications.

Introduction to the SD Card

1.5.9.5. Memory Array Partitioning

The basic unit of data transfer to/from the SD Card is one byte. All data transfer operations which require a block size always define block lengths as integer multiples of bytes. Some special functions need other partition granularity. Figure 1-2 shows the Memory Array Partitioning.

For block-oriented commands, the following definition is used:

• Block—The unit that is related to the block-oriented read and write commands. Its size is the number

of bytes that are transferred when one block command is sent by the host. The size of a block is either programmable or fixed. The information about allowed block sizes and the programmability is stored in the CSD.

The granularity of the erasable units is in general not the same as for the block-oriented commands:

• Sector—The unit that is related to the erase commands. Its size is the number of blocks that are erased

in one portion. The size of a sector is fixed for each device. The information about the sector size (in blocks) is stored in the CSD.

For devices that include write protection, the following definition is used:

• WP Group—The minimal unit that may which may have individual write protection. Its size is the

number of groups which will be write protected by one bit. The size of a WP-group is fixed for each device. The information about the size is stored in the CSD.

Introduction to the SD Card

SD Memory Card

WP Group 0

Sector 1

Block

Sector 2

Sector 3

Sector n

WP Group 1

WP Group n

Protected Area (Copyright protection)

Sector 1

Block

Sector n

Figure 1-2. Memory Array Partitioning

Table 1-3. Memory Array Structures Summary

Part Number Block Size

(Byte)

SDSDJ-1024 512 2,004,224 20,480 1,983,744

SDSDJ-512 512 1,001,104 10,240 940,864

SDSDJ-256 512 499,456 5,376 494,080

SDSDJ-128 512 248,640 2,624 246,016

SDSDJ-64 512 123,232 1,376 121,856

SDSDB-32 512 60,512 736 59,776

SDSDB-16 512 29,152 352 28,800

Data Area + Protected size

(Blocks)

Protected Area size

(Blocks)

User Area

(Blocks)

NOTE: All measurements are in units per card.

Protected Area—The part of the Card that relates to the secured copyright management and has separate DOS

partitioning including sectors and blocks. The card write protection mechanism does not effect this area.

Introduction to the SD Card

1.5.9.6. Read and Write Operations

The SD Card supports two read/write modes as shown in Figure 1-3.

Multiple Block Mode

Memory

Sectors

Memory

Sectors

Memory

Sectors

Start

Address

Single Block Mode

Memory

Sectors

Start

Address

(Read)

Memory

Sectors

Memory

Sectors

Memory

Sectors

Write Read

Memory

Sectors

Start

Address

(Write)

Stop

Memory

Sectors

Start

Memory

Sectors

Memory

Sectors

Misalignment Error

Memory

Sectors

Start

Address

(Read/Write)

Memory

Sectors

Stop

Memory

Sectors

Figure 1-3. Data Transfer Formats

Single Block Mode

In this mode the host reads or writes one data block in a pre-specified length. The data block transmission is protected with 16-bit CRC that is generated by the sending unit and checked by the receiving unit.

The block length for read operations is limited by the device sector size (512 bytes) but can be as small as a single byte. Misalignment is not allowed. Every data block must be contained in a single physical sector. The block length for write operations must be identical to the sector size and the start address aligned to a sector boundary.

Multiple Block Mode

This mode is similar to the single block mode, but the host can read/write multiple data blocks (all have the same length) which will be stored or retrieved from contiguous memory addresses starting at the address specified in the command. The operation is terminated with a stop transmission command.

Misalignment and block length restrictions apply to multiple blocks as well and are identical to the single block read/write operations.

1.5.9.7. Data Transfer Rate

The SD Card can be operated using either a single data line (DAT0) or four data lines (DAT0-DAT3) for data transfer. The maximum data transfer rate for a single data line is 25 Mbit per second and for four data lines it is 100 Mbit (12 MB) per second.

Introduction to the SD Card

1.5.9.8. Data Protection in the Flash Card

Every sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.

1.5.9.9. Erase

The smallest erasable unit in the SD Card is a sector. In order to speed up the erase procedure, multiple sectors can be erased at the same time. To facilitate selection, a first command with the starting address is followed by a second command with the final address, and all sectors within this range will be selected for erase.

1.5.9.10. Write Protection

Two-card level write protection options are available: permanent and temporary. Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared. This feature is implemented in the SD Card controller firmware and not with a physical OTP cell.

NOTE: Use the Write Protect (WP) Switch located on the card’s side edge to prevent the host from writing to or

erasing data on the card. The WP switch does not have any influence on the internal Permanent or Temporary WP bits in the CSD.

1.5.9.11. Copy Bit

The content of a SD Card can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared. The Copy bit of the SD Card is programmed (during test and formatting on the manufacturing floor) as a copy. The SD Card can be purchased with the copy bit set (copy) or cleared, indicating the card is a master. This feature is implemented in the SD Card controller firmware and not with a physical OTP cell.

1.5.9.12. The CSD Register

All the configuration information of the SD Card is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contain the host-controlled data, the card Copy, write protection and the user file format indication.

The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.

1.5.10. SD Card—SPI Mode

The SPI mode is a secondary communication protocol for SD Cards. This mode is a subset of the SD Card protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.

Introduction to the SD Card

1.5.10.1. Negotiating Operating Conditions

The operating condition negotiation function of the SD Card bus is supported differently in SPI mode by using the READ_OCR (CMD58) command. The host shall work within the valid voltage range (2.7 to 3.6 volts) of the card or put the card in inactive state by sending a GO_INACTIVE command to the card.

1.5.10.2. Card Acquisition and Identification

The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal (CD/DAT3). The internal pullup resistor on the CD/DAT3 line may be used for card detection (insertion/removal). Additional practical card detection methods can be found in SD Physical Specification’s Application Notes given by the SDA.

1.5.10.3. Card Status

In SPI mode, only 16 bits (containing the errors relevant to SPI mode) can be read out of the 32-bit SD Card status register. The SD_STATUS can be read using ACMD13, the same as in SD Bus mode.

1.5.10.4. Memory Array Partitioning

Memory partitioning in SPI mode is equivalent to SD Bus mode. All read and write commands are byte addressable with the limitations given in Section 1.5.9.5.

1.5.10.5. Read and Write Operations

In SPI mode, both single and multiple block data transfer modes are supported.

1.5.10.6. Data Transfer Rate

In the SPI mode, only one data line is used for each direction. The SPI mode data transfer rate is the same as the SD Bus mode data transfer rate when using one data line only (up to 25 Kbits per second).

1.5.10.7. Data Protection in the SD Card

Same as for the SD Card mode.

1.5.10.8. Erase

Same as in SD Card mode.

Introduction to the SD Card

1.5.10.9. Write Protection

Same as in SD Card mode.

1.5.10.10. Copyright Protection

Same as in SD Card mode.

Introduction to the SD Card

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2. Product Specifications

For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless otherwise stated.

2.1. System Environmental Specifications

Table 2-1. System Environmental Specifications

Temperature Operating:

Non-Operating:

Humidity Operating:

Non-Operating:

ESD Protection Contact Pads:

Non Contact Pad Area:

-25° C to 85° C

-40° C to 85° C

25% to 95%, non-condensing 25% to 95%, non-condensing

± 4kV, Human body model according to ANSI EOS/ESD-S5.1-1998

± 8kV (coupling plane discharge) ± 15kV (air discharge) Human body model per IEC61000-4-2

2.2. Reliability and Durability

Table 2-2. Reliability and Durability Specifications

Durability 10,000 mating cycles

Bending 10N

Torque 0.15N.m or ±2.5 deg.

Drop Test 1.5m free fall

UV Light Exposure UV: 254nm, 15Ws/cm2 according to ISO 7816-1

Visual Inspection/Shape and Form No warpage; no mold skin; complete form; no cavities; surface

Minimum Moving Force of WP Switch 40 gf (ensures that the WP switch will not slide while it is

WP Switch Cycles Minimum 1,000 Cycles @ slide force 0.4N to 5N

smoothness ≤ -0.1 mm/cm pollution (oil, dust, etc.)

inserted in the connector).

within contour; no cracks; no

Product Specifications

2.3. Typical Card Power Requirements

Table 2-3. Card Power Requirements

VDD (ripple: max, 60 mV peak to peak) 2.7 V – 3.6 V

(Ta = 25°C @3 V)

Value Measurement Notes

Sleep 250 uA Max

Read 65 mA Max

Write 75 mA Max

2.4. System Performance

Table 2-4. System Performance

Typical Maximum

Block Read Access Time

Binary Products MLC Products

Block Write Access Time

Binary Products MLC Products

CMD1 to Ready (after power up)

Sleep to Ready 1msec 2msec

NOTES: All values quoted are under the following conditions:

1) Voltage range: 2.7 V to 3.6 V.

2) Temperature range: -25° C to 85° C.

3) Are independent of the SD Card clock frequency.

1.5msec 10msec

24msec 40msec

50msec 500msec

100msec 100msec

250msec 250msec

2.5. System Reliability and Maintenance

Table 2-5. System Reliability and Maintenance Specifications

MTBF > 1,000,000 hours

Preventive Maintenance None

Data Reliability < 1 non-recoverable error in 1014 bits read

Endurance 100,000 write/erase cycles (typical)

Product Specifications

2.6. Physical Specifications

Refer to Table 2-6 and to Figures 2-1 through 2-3 for SD Card physical specifications and dimensions.

Table 2-6. Physical Specifications

Weight 2.0 g. maximum

Length: 32mm ± 0.1mm

Width: 24mm ± 0.1mm

Thickness: 2.1mm ± 0.15mm

(in substrate area only, 2.25mm maximum)

Figure 2-1. SD Card Dimensions

Product Specifications

Figure 2-2. SD Card Dimensions

Product Specifications

Figure 2-3. SD Card Dimensions

Product Specifications

This page intentionally left blank.

3. SD Card Interface Description

3.1. General Description of Pins and Registers

The SD Card has nine exposed contacts on one side (see Figure 3-1). The host is connected to the SD Card using a dedicated 9-pin connector.

3.1.1. Pin Assignments in SD Card Mode

Table 3-1 lists the pin assignments and definitions in SD Card Mode.

Table 3-1. SD Bus Mode Pad Definition

Pin # Name Type1 SD Description

1 CD/DAT32 I/O3 Card Detect/Data Line [Bit 3]

2 CMD I/O Command/Response

3 V

4 VDD S Supply voltage

5 CLK I Clock

6 V

7 DAT0 I/O Data Line [Bit 0]

8 DAT1 I/O Data Line [Bit 1]

9 DAT2 I/O Data Line [Bit 2]

NOTES: 1) S=power supply; I=input; O=output using push-pull drivers.

2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after the SET_BUS_WIDTH command. It is the responsibility of the host designer to connect external pullup resistors to all data lines even if only DAT0 is to be used. Otherwise, non-expected high current consumption may occur due to the floating inputs of DAT1 & DAT2 (in case they are not used).

3) After power up, this line is input with 50Kohm(+/-20Kohm) pull-up (can be used for card detection or SPI mode selection). The pull-up may be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.

S Supply voltage ground

SS1

S Supply voltage ground

SS2

SD Card Interface Description

3.1.2. Pin Assignments in SPI Mode

Table 3-2 lists the pin assignments and definitions in SPI Mode.

Table 3-2. SPI Bus Mode Pad Definition

Pin # Name Type1 SPI Description

1 CS I Chip Select (Active low)

2 DataIn I Host to Card Commands and Data

3 VSS1 S Supply Voltage Ground

4 VDD S Supply Voltage

5 CLK I Clock

6 VSS2 S Supply Voltage Ground

7 DataOut O Card to Host Data and Status

8 RSV(2) I Reserved

9 RSV(2) I Reserved

NOTES: 1) S=power supply; I=input; O=output.

2) The ‘RSV’ pins are floating inputs. It is the responsibility of the host designer to connect external pullup resistors to those lines. Otherwise non-expected high current consumption may occur due to the floating inputs.

Each card has a set of information registers (refer to Table 3-3). Detailed descriptions are provided in Section 3.5.

Table 3-3. SD Card Registers

Name Width Description

CID 128 Card identification number: individual card number for identification.

RCA1 16 Relative card address: local system address of a card, dynamically

suggested by the card and approved by the host during initialization.

CSD 128 Card specific data: information about the card operation conditions.

SCR 64 SD Configuration Register: information about the SD Card’s special

features capabilities.

OCR 32 Operation Condition Register

NOTE: 1) The RCA register is not available in SPI Mode.

The host may reset the cards by switching the power supply off and on again. The card has its own power-on detection circuitry which puts the card into an idle state after the power-on. The card can also be reset by sending the GO_IDLE (CMD0) command.

SD Card Interface Description

Figure 3-1. SD Card Architecture

3.2. SD Bus Topology

The SD bus has six communication lines and three supply lines:

• CMD—Command is a bi-directional signal. (Host and card drivers are operating in push pull mode.)

• DAT0-3—Data lines are bi-directional signals. (Host and card drivers are operating in push pull

mode.)

• CLK—Clock is a host to cards signal. (CLK operates in push pull mode.)

• VDD—VDD is the power supply line for all cards.

• VSS[1:2]—VSS are two ground lines.

SD Card Interface Description

Figure 3-2 shows the bus topology of several cards with one host in SD Bus mode.

HOST

CLK

Vdd Vss

D0-3(A), CMD(A)

D0-3(B), CMD(B)

D0-D3, CMD

CLK

Vdd Vss

CLK

Vdd Vss

CLK

SD Memory

Card (A)

SD Memory

Card (B)

Vdd Vss

MultiMediaCard

(C)

D0-3(C) CMD(C)

D0, CS, CMD

D1&D2 Not

Connected

Figure 3-2. SD Card System Bus Topology

During the initialization process, commands are sent to each card individually, allowing the application to detect the cards and assign logical addresses to the physical slots. Data is always sent to each card individually. However, to simplify the handling of the card stack, after initialization, all commands may be sent concurrently to all cards. Addressing information is provided in the command packet.

The SD Bus allows dynamic configuration of the number of data lines. After power-up, by default, the SD Card will use only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines). This feature allows and easy trade off between hardware cost and system performance.

SD Card Interface Description

DAT

Memory

Card

Host

Figure 3-3. Bus Circuitry Diagram

DAT

and R

are pull-up resistors protecting the CMD and the DAT line against bus floating when no card is

CMD

inserted or when all card drivers are in a hi-impedance mode. RWP is used for the Write Protect Switch. See Section 5.4.2 for the component values and conditions.

CMD

C1C

DAT0-3

Write Protect

CMD

Vss

1 2 3 4 5 6 7 8

SD Memory

Card

CLK

Hot Insertion/Removal

Hot insertion and removal are allowed. The SanDisk SD Card will not be damaged by inserting or removing it into the SD bus even when the power is up:

• The inserted card will be properly reset also when CLK carries a clock frequency f

• Data transfer failures induced by removal/insertion should be detected by the bus master using the

CRC codes that suffix every bus transaction.

3.2.1. Power Protection

Cards can be inserted into or removed from the bus without damage. If one of the supply pins (V connected properly, then the current is drawn through a data line to supply the card.

DD or VSS)

is not

Data transfer operations are protected by CRC codes; therefore, any bit changes induced by card insertion and removal can be detected by the SD bus master. The inserted card must be properly reset also when CLK carries a clock frequency f between V

If the hot insertion feature is implemented in the host, than the host has to withstand a shortcut

pp.

and V

without damage.

3.3. SPI Bus Topology

The SD Card SPI interface is compatible with SPI hosts available on the market. As any other SPI device the SD Card SPI channel consists of the following four signals:

• CS—Host to card Chip Select signal.

• CLK—Host to card clock signal.

• DataIn—Host to card data signal.

• DataOut—Card to host data signal.

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