SanDisk SDP3B Product Manual

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SDP3B FlashDisk

Product Manual

CORPORATE HEADQUARTERS

140 Caspian Court

Sunnyvale, CA 94089

408-542-0500

FAX: 408-542-0503

URL: http://www.sandisk.com

SanDisk® Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages.

The information in this manual is subject to change without notice. SanDisk Corporation shall not be liable for technical or editorial errors or omissions contained herein; nor for incidental or

consequential damages resulting from the furnishing, performance, or use of this material. All parts of the SanDisk SDP3B FlashDisk documentation are protected by copyright law and all rights are reserved. This

documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine readable form without prior consent, in writing, from SanDisk Corporation.

SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation. Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks

5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and pending.

Lit. No. 20-10-00041 Rev. 3 5/98 Printed in U.S.A.

SDP3B FlashDisk Product Manual

Table of Contents

1.0 Introduction to the SDP3B FlashDisk................................................................7

1.1 Scope...............................................................................................................................7

1.2 Product Models.................................................................................................................7

1.3 System Features...............................................................................................................8

1.4 PCMCIA Standard...........................................................................................................8

1.5 Related Documentation....................................................................................................8

1.6 The SDP3B FlashDisk Compared to the Previous FlashDisks...........................................8

1.6.1 System Power Requirements..................................................................................9

1.6.2 Card Information Structure (CIS)........................................................................10

1.6.3 Capacity Specifications.....................................................................................10

1.6.4 Voltage Sense Signal -VS1.................................................................................11

1.6.5 True IDE Mode...................................................................................................11

1.6.6 Identify Drive Information.................................................................................11

1.7 Functional Description...................................................................................................11

1.7.1 Flash Technology Independence..........................................................................11

1.7.2 Defect and Error Management.............................................................................11

1.7.3 Endurance .........................................................................................................12

1.7.4 Wear Leveling...................................................................................................12

1.7.5 Using the Erase Sector and Write without Erase Commands.................................12

1.7.5.1 Interaction with Systems not Aware of the Erase Sector and

Write without Erase Commands..........................................................12

1.7.5.2 Limitations and Issues.........................................................................13

1.7.6 Automatic Sleep Mode.......................................................................................13

1.7.7 Dynamic Adjustment of Performance versus Power Consumption ..........................13

1.7.8 Power Supply Requirements................................................................................13

2.0 Product Specifications................................................................................14

2.1 SDP3B FlashDisk System Environmental Specifications.................................................14

2.2 SDP3B FlashDisk System Power Requirements...............................................................14

2.3 System Performance.......................................................................................................15

2.4 System Reliability and Maintenance..............................................................................15

2.5 Physical Specifications..................................................................................................15

2.6 Capacity Specifications.................................................................................................18

3.0 Installation .............................................................................................19

3.1 Mounting........................................................................................................................19

4.0 SDP3B FlashDisk Interface Description ...........................................................20

4.1 Physical Description......................................................................................................20

4.1.1 Pin Assignments and Pin Type.............................................................................20

4.2 Electrical Description....................................................................................................20

4.3 Electrical Specification..................................................................................................28

4.3.1 Input Leakage Current........................................................................................28

4.3.2 Input Characteristics.........................................................................................28

4.3.3 Output Drive Type.............................................................................................29

4.3.4 Output Drive Characteristics.............................................................................29

4.3.5 Interface/Bus Timing..........................................................................................30

SDP3B FlashDisk Product Manual

Table of Contents (continued)

4.3.6 Attribute Memory Read Timing Specification.....................................................30

4.3.7 Attribute Memory Write Timing Specification....................................................31

4.3.8 Common Memory Read Timing Specification.......................................................32

4.3.9 Common Memory Write Timing Specification......................................................33

4.3.10 I/O Input (Read) Timing Specification................................................................34

4.3.11 I/O Output (Write) Timing Specification............................................................35

4.3.12 True IDE Mode I/O Input (Read) Timing Specification.........................................36

4.3.13 True IDE Mode I/O Output (Write) Timing Specification.....................................37

4.4 Card Configuration........................................................................................................38

4.4.1 Attribute Memory Function.................................................................................39

4.4.2 Configuration Option Register (Address 200h in Attribute Memory).....................40

4.4.3 Card Configuration and Status Register (Address 202h in Attribute Memory).......40

4.4.4 Pin Replacement Register (Address 204h in Attribute Memory)............................41

4.4.5 Socket and Copy Register (Address 206h in Attribute Memory)............................42

4.5 I/O Transfer Function.....................................................................................................43

4.5.1 I/O Function.......................................................................................................43

4.6 Common Memory Transfer Function.................................................................................44

4.6.1 Common Memory Function...................................................................................44

4.7 True IDE Mode I/O Transfer Function..............................................................................45

4.7.1 True IDE Mode I/O Function................................................................................45

5.0 ATA Drive Register Set Definition and Protocol..................................................46

5.1 I/O Primary and Secondary Address Configurations........................................................47

5.2 Contiguous I/O Mapped Addressing................................................................................48

5.3 Memory Mapped Addressing..........................................................................................49

5.4 True IDE Mode Addressing..............................................................................................50

5.5 ATA Registers................................................................................................................51

5.5.1 Data Register (Address - 1F0[170]; Offset 0,8,9)...................................................51

5.5.2 Error Register (Address - 1F1[171]; Offset 1, 0Dh Read Only)...............................52

5.5.3 Feature Register (Address - 1F1[171]; Offset 1, 0Dh Write Only)..........................52

5.5.4 Sector Count Register (Address - 1F2[172]; Offset 2).............................................52

5.5.5 Sector Number (LBA 7-0) Register (Address - 1F3[173]; Offset 3)..........................52

5.5.6 Cylinder Low (LBA 15-8) Register (Address - 1F4[174]; Offset 4).........................52

5.5.7 Cylinder High (LBA 23-16) Register (Address - 1F5[175]; Offset 5)......................52

5.5.8 Drive/Head (LBA 27-24) Register (Address 1F6[176]; Offset 6)............................53

5.5.9 Status & Alternate Status Registers (Address 1F7[177]&3F6[376]; Offsets 7 & Eh) 54

5.5.10 Device Control Register (Address - 3F6[376]; Offset Eh).......................................54

5.5.11 Card (Drive) Address Register (Address 3F7[377]; Offset Fh).............................55

6.0 ATA Command Description .........................................................................56

6.1 ATA Command Set.........................................................................................................56

6.1.1 Check Power Mode - 98H, E5H............................................................................58

6.1.2 Execute Drive Diagnostic - 90H...........................................................................58

6.1.3 Erase Sector(s) - C0H..........................................................................................59

6.1.4 Format Track - 50H............................................................................................60

6.1.5 Identify Drive - ECH.........................................................................................60

6.1.5.1 General Configuration.........................................................................62

SDP3B FlashDisk Product Manual

Table of Contents (continued)

6.1.5.2 Default Number of Cylinders..............................................................62

6.1.5.3 Default Number of Heads....................................................................62

6.1.5.4 Number of Unformatted Bytes per Track..............................................62

6.1.5.5 Number of Unformatted Bytes per Sector..............................................62

6.1.5.6 Default Number of Sectors per Track....................................................62

6.1.5.7 Number of Sectors per Card..................................................................62

6.1.5.8 Memory Card Serial Number...............................................................62

6.1.5.9 Buffer Type.........................................................................................62

6.1.5.10 Buffer Size..........................................................................................62

6.1.5.11 ECC Count...........................................................................................62

6.1.5.12 Firmware Revision..............................................................................62

6.1.5.13 Model Number....................................................................................62

6.1.5.14 Read/Write Multiple Sector Count......................................................62

6.1.5.15 Double Word Support..........................................................................62

6.1.5.16 Capabilities.......................................................................................62

6.1.5.17 PIO Data Transfer Cycle Timing Mode.................................................63

6.1.5.18 DMA Data Transfer Cycle Timing Mode...............................................63

6.1.5.19 Translation Parameters Valid.............................................................63

6.1.5.20 Current Number of Cylinders, Heads, Sectors/Track.............................63

6.1.5.21 Current Capacity................................................................................63

6.1.5.22 Multiple Sector Setting.......................................................................63

6.1.5.23 Total Sectors Addressable in LBA Mode...............................................63

6.1.6 Idle - 97H,E3H...................................................................................................64

6.1.7 Idle Immediate - 95H,E1H.................................................................................64

6.1.8 Initialize Drive Parameters - 91H......................................................................65

6.1.9 Read Buffer - E4H..............................................................................................65

6.1.10 Read Multiple - C4H..........................................................................................66

6.1.11 Read Long Sector - 22H & 23H............................................................................67

6.1.12 Read Sector(s) - 20H & 21H................................................................................67

6.1.13 Read Verify Sector(s) - 40H & 41H.....................................................................68

6.1.14 Recalibrate - 1XH..............................................................................................68

6.1.15 Request Sense - 03H............................................................................................69

6.1.16 Seek - 7XH.........................................................................................................70

6.1.17 Set Features - EFH.............................................................................................70

6.1.18 Set Multiple Mode - C6H....................................................................................72

6.1.19 Set Sleep Mode- 99H,E6H..................................................................................72

6.1.20 Standby - 96H,E2H............................................................................................73

6.1.21 Standby Immediate - 94H,E0H...........................................................................73

6.1.22 Translate Sector - 87H........................................................................................74

6.1.23 Wear Level - F5H..............................................................................................75

6.1.24 Write Buffer - E8H.............................................................................................75

6.1.25 Write Long Sector - 32H & 33H...........................................................................76

6.1.26 Write Multiple Command - C5H.........................................................................76

6.1.27 Write Multiple without Erase - CDH.................................................................77

6.1.28 Write Sector(s) - 30H & 31H...............................................................................78

6.1.29 Write Sector(s) without Erase - 38H...................................................................78

6.1.30 Write Verify Sector(s) - 3CH..............................................................................79

6.2 Error Posting..................................................................................................................80

SDP3B FlashDisk Product Manual

Table of Contents (continued)

7.0 CIS Description .......................................................................................83

Ordering Information and Technical Support.............................................................99

Ordering Information.............................................................................................................101

SanDisk SDP3B FlashDisk Series.................................................................................101

SanDisk FlashDisk Evaluation Kit...............................................................................101

SanDisk FlashDisk Adapter Board...............................................................................102

Technical Support Services.....................................................................................................103

Direct SanDisk Technical Support.................................................................................103

SanDisk Worldwide Web Site.......................................................................................103

System Software and Card Reader/Writers

Compatible with the SanDisk SDP3B FlashDisk..........................................................104

SanDisk Worldwide Sales Offices........................................................................107

Limited Warranty ...........................................................................................110

SDP3B FlashDisk Product Manual

1.0 Introduction to the SDP3B FlashDisk

The SanDisk SDP3B FlashDisk products provide high capacity solid state flash memory that electrically complies with the Personal Computer Memory Card International Association ATA (PC Card ATA) standard. (In Japan, the applicable standards group is JEIDA.) The SDP3B FlashDisk also supports a True IDE Mode that is electrically compatible with an IDE disk drive. SDP3B FlashDisks provide up to 220 million bytes (Megabytes, MBytes or MB) of formatted storage capacity in a Type II or Type III form factor. The host system can support as many cards as there are Type II or III PCMCIA slots.

The SDP3B FlashDisk uses SanDisk Flash memory chips which were designed by SanDisk specifically for use in mass storage applications. In addition to the mass storage specific Flash

memory chips, the SDP3B FlashDisks include an on-card intelligent controller that provides a high level interface to the host computer. This interface allows a host computer to issue commands to the memory card to read or write blocks of memory. A block of memory consists of 512 bytes of data and is protected by a powerful Error Correcting Code (ECC).

The SDP3B FlashDisk on-card intelligent controller manages interface protocols, data storage and retrieval as well as ECC, defect handling and diagnostics, power management and clock control. Once the SDP3B FlashDisk has been configured by the host, it appears to the host as a standard ATA (IDE) disk drive. Additional ATA commands have been provided to enhance system performance.

Figure 1-1 SDP3B FlashDisk Block Diagram

1.1 Scope

This document describes the key features and specifications of the SDP3B FlashDisk, as well as the information required to interface this product to a host system.

1.2 Product Models

The SDP3B FlashDisk is available in 2 to 220 megabyte capacities. All SDP3B FlashDisks are shipped formatted with a DOS 5.0 file structure.

SDP3B FlashDisk Product Manual

1.3 System Features

• Up to 220 megabytes of data storage available

• PC Card ATA protocol compatible

• True IDE Mode compatible

• Very low CMOS power

• Very high performance

• Programmable power versus performance

• Very rugged

• Low weight

• Noiseless

• Low Profile

• +5 Volts or +3.3 Volts operation

• Automatic error correction and retry capabilities

• Supports power down commands and sleep modes

• Non-volatile storage (no battery required)

• MTBF of 1,000,000 hours for Type II FlashDisk, 500,000 hours for Type III FlashDisk

• Minimum 10,000 insertions

1.5 Related Documentation

1) American National Standard X3.221 AT Attachment for Interface for Disk Drives Document

This document can be obtained by calling

Global Engineering at 1-800-854-7179.

1.6 The SDP3B FlashDisk Compared to Previous FlashDisks

The SDP3B FlashDisk is compatible with SanDisk’s previous FlashDisk products, the SDP, SDP5, and the SDP5A product. The SDP3B FlashDisk is not compatible with the SDP5L which was designed specifically for the HP95LX. Therefore, the SDP3B FlashDisk is not system compatible with the HP95LX. For this document, any of these products are defined as the SDP Series products. Several improvements have been added to the SDP3B FlashDisk that do not appear in previous products. Differences between the SDP3B FlashDisk and the previous FlashDisks that could be noticed by previous FlashDisk users are explained in the following sections.

• Standard (SDP3B) and industrial (SDP3BI) versions available

1.4 PCMCIA Standard

SDP3B FlashDisks are fully compatible with the PCMCIA specifications listed below. These specifications may be obtained from:

PCMCIA 2635 N. First St. Suite 209 San Jose, CA 95134 USA Phone: 408-433-2273 Fax: 408-433-9558

1) PCMCIA PC Card Standard, January 1995

2) PCMCIA PC Card ATA Specification, January 1995

1.6.1 System Power Requirements

SDP3B FlashDisk Product Manual

The system power requirements for the SDP3B FlashDisk are different from those of the SDP5A

SDP5A FlashDisk and the SDP3B FlashDisk power requirements.

FlashDisk. The two tables below show the

SDP3B

(Standard Version)

DC Input Voltage (VCC) 100 mV max. ripple (p-p)

Capacities of

85 MB & Lower

+5 V Currents (maximum Average value) See Notes 1 to 3.

Read/Write Peak

Capacities

above 85 MB

Read/Write Peak

Note 1. All values quoted are typical at ambient temperature and nominal supply voltage unless otherwise stated. Note 2. Sleep mode currently is specified under the condition that all card inputs are static CMOS levels and in a

“Not Busy “ operating state.

Note 3. The currents specified show the bounds of programmability of the product.

Sleep:

Reading:

Writing:

Sleep:

Reading:

Writing:

3.3V ±5% 5V ± 10% 3.3V ±5% 5 V ±5% Only

200 µA (Slow - Fast) 32 mA - 45 mA 32 mA - 60 mA 150 mA/50µs

200 µA (Slow - Fast) 32 mA - 50 mA 32 mA - 70 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 75 mA 46 mA - 90 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 90 mA 46 mA - 110 mA 150 mA/50µs

200 µA (Slow - Fast) 32 mA - 45 mA 32 mA - 60 mA 150 mA/50µs

200 µA (Slow - Fast) 32 mA - 50 mA 32 mA - 70 mA 150 mA/50µs

SDP3BI

(Industrial Version)

500 µA (Slow - Fast) 46 mA - 75 mA 46 mA - 90 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 90 mA 46 mA - 110 mA 150 mA/50µs

Model SDP5A Standard FlashDisk Industrial FlashDisk

DC Input Voltage (VPP) (Note 4) Not Used Not Used

DC Input Voltage (VCC)

100 mv max. ripple (p-p)

+5 V Currents

(maximum average value)

See Notes 1 to 5

Note 1. Sleep mode current is specified under the condition that all FlashDisk inputs are at static CMOS levels and

in a “Not Busy” operating state.

Note 2. The currents specified show the complete range of programmability in the PC Card ATA FlashDisk. A

tradeoff between performance and maximum current used can be done using the Set Features command. The FlashDisk defaults to the fastest speed and highest current. See the Set Features command for more details.

Note 3. For information on peak currents during power on, hot insertion and writing, please contact SanDisk

Technical Support at (408) 542-0400. Note 4. The Vpp pins are not connected in this product. Note 5. At maximum performance, typical average Read current is 70 mA and typical average write current is

100 mA.

Sleep:

Reading:

Writing: Type III

Reading:

Writing:

5 V ±10% 5 V ±5%

≤ 1 mA (Slow - Fast) 36 mA - 100 mA 36 mA - 125 mA

36 mA - 125 mA 36 mA - 150 mA

(Slow - Fast) 36 mA - 100 mA 36 mA - 125 mA

36 mA - 125 mA 36 mA - 150 mA

≤ 1 mA

SDP3B FlashDisk Product Manual

1.6.2 Card Information Structure (CIS)

The Card Information Structure (CIS) of the SDP5A FlashDisk is different from the SDP3B FlashDisk CIS. The SDP3B FlashDisk CIS indicates support for twin card and 3.3 volt operation which are not supported in the SDP5A

1.6.3 Capacity Specifications

The capacity specifications for the SDP5A FlashDisk are different from the capacity specifications of the SDP3B FlashDisk. The tables below show the capacity specifications of the SDP5A FlashDisk and the SDP3B FlashDisk.

FlashDisk. Both the SDP5A FlashDisk and the SDP3B FlashDisk support 5 volt operation.

Model

Number

SDP5A-5 Type II 5,242,880 bytes 10,240 2 32 160 SDP5A-10 Type II 10,485,760 bytes 20,480 2 32 320 SDP5A-20 Type II 20,971,520 bytes 40,960 2 32 640 SDP5A-40 Type II 41,943,040 bytes 81,920 4 32 640

SDP5A-110 Type III 110,100,480 bytes 215,040 8 32 840 SDP5A-175 Type III 175,374,336 bytes 342,528 12 32 892

Form

Factor

Capacity

(formatted)

Note: SanDisk defines a megabyte as one million

bytes.

Sectors/Card

(Max LBA+1)

No. of

Heads

No. of

Sectors/Track

Cylinders

No. of

Model

Number

SDP3B-2 Type II 2,015,232 bytes 3,936 2 16 123

SDP3B-4 Type II 4,030,464 bytes 7,872 2 32 123

SDP3B-6 Type II 6,029,312 bytes 11,776 2 32 184

SDP3B-8 Type II 8,028,160 bytes 15,680 2 32 245 SDP3B-10 Type II 10,485,760 bytes 20,480 2 32 320 SDP3B-20 Type II 20,971,520 bytes 40,960 2 32 640 SDP3B-40 Type II 41,943,040 bytes 81,920 4 32 640 SDP3B-60 Type II 60,162,048 bytes 117,504 6 32 612 SDP3B-85 Type II 85,196,800 bytes 166,400 8 32 650

SDP3B-110 Type II or III 110,100,480 bytes 215,040 8 32 840 SDP3B-175 Type II or III 175,374,336 bytes 342,528 12 32 892 SDP3B-220 Type II or III 220,200,960 bytes 430,080 16 32 840

Form

Factor

Capacity

(formatted)

Sectors/Card

(Max LBA+1)

No. of

Heads

No. of

Sectors/

Track

No. of

Cylinders

SDP3B FlashDisk Product Manual

1.6.4 Voltage Sense Signal -VS1

The Voltage Sense Signal -VS1, pin 43, of the SDP3B FlashDisk is grounded because the Card Information Structure (CIS) can be read at 3.3 volts. In the SDP5A FlashDisk, this pin is not grounded because the SDP5A FlashDisk CIS can only be read at 5 volts.

Note: In some early platforms, the -VS1 pin (pin 43) is

also the Refresh pin for DRAM cards. Plugging the SDP3B into a platform supporting the Refresh pin will hang the bus.

1.6.5 True IDE Mode

The SDP3B FlashDisk differs from the SDP5A FlashDisk in that it can be configured in True IDE Mode. See section 4.6 True IDE Mode I/O Transfer Function.

1.6.6 Identify Drive Information

Word 51 of the Identify Drive Command information has a default value of 0000H for the SDP5A FlashDisk. The data field type information for this word is “PIO data transfer cycle timing mode 0.”

For the SDP3B FlashDisk, word 51 of the Identify Drive Command information has a default value of 0001H. The data field type information for this word is “PIO data transfer cycle timing mode 1.”

4. Sophisticated system for error recovery including a powerful error correction code (ECC).

5. Power management for low power operation.

1.7.1 Flash Technology Independence

The 512 byte sector size of SDP3B FlashDisk is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the SDP3B FlashDisk. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Since the SDP3B FlashDisk uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the SDP3B FlashDisk today will be able to access future SanDisk cards built with new flash technology without having to update or change host software.

1.7.2 Defect and Error Management

1.7 Functional Description

SDP3B FlashDisks contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk

SDP3B FlashDisks contain a high level, intelligent subsystem as shown in the block diagram, Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities not found in other types of memory cards. These capabilities include:

1. Standard ATA register and command set (same as found on most magnetic disk drives).

2. Host independence from details of erasing and programming flash memory.

drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. SDP3B FlashDisks do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, SDP3B FlashDisks replace this bad bit with a spare bit within the sector header. If necessary, SDP3B FlashDisks will even replace the entire sector with a spare sector. This is completely

3. Sophisticated system for managing defects (analogous to systems found in

transparent to the host and does not consume any user data space.

magnetic disk drives).

SDP3B FlashDisk Product Manual

The SDP3B FlashDisk soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, SDP3B FlashDisks have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ a powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.

These defect and error management systems coupled with the solid state construction give SDP3B FlashDisks unparalleled reliability.

1.7.3 Endurance

SDP3B FlashDisks have an endurance specification for each sector of 300,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of SDP3B FlashDisks. Even very heavy use of SDP3B FlashDisks in PDAs, ruggedized handheld computers, palmtop and notebook computers will use only a fraction of the total endurance over the typical computer’s five year lifetime. For instance, it would take over 34 years to wear out an area on the SDP3B FlashDisk on which a file of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.

With typical applications (PIM software, word processing, spreadsheets, etc.), the endurance limit is not of any practical concern to the vast majority of users.

Erase Sector command, a write to that sector will be much faster. This is because a normal write operation includes a separate sector erase prior to write.

An example of where these commands may be useful is in a digital camera. The camera user may have plenty of time to erase pictures but may wish to take several pictures in rapid succession. To accomplish this, the host system (i.e., camera) would use the Erase Sectors command to pre-erase the sectors that will store the pictures. When the pictures are taken, the camera can store them in the previously erased sectors much faster than in non-erased sectors.

1.7.5.1 Interaction with Systems not Aware of the Erase Sector and Write without Erase Commands

Many systems that can read and write SDP3B FlashDisks may not be aware of the Erase Sector and Write without Erase Commands. These systems would not issue these commands but such a system might attempt a normal write or a normal read to a pre-erased sector.

A normal write to a pre-erased sector will function correctly, but will be at the normal write speed that is slower than a Write without Erase command.

If a normal read is attempted to a “pre-erased” sector, SDP3B FlashDisks will detect it is preerased and will return zero data and will not report an error even though the data ECC is not valid.

1.7.4 Wear Leveling

SDP3B FlashDisks do not require or perform a Wear Level operation. The command is supported as a NOP operation to maintain backward compatibility with existing software utilities.

1.7.5 Using the Erase Sector and Write without Erase Commands

The Erase Sector and Write without Erase commands provide the capability to substantially increase the write performance of the SDP3B FlashDisk. Once a sector has been erased using the

If an “un-aware” host system over-writes a preerased sector with a normal write and then the SDP3B FlashDisk is moved to the system that created the erased sectors, a situation exists where a Write without Erase might be attempted to a “normal” sector. If this occurs, the SDP3B FlashDisk will perform a normal write which means it will first erase the sector and then do a full write with all margin modes enabled. This write will of course be slower than if the sector were in fact pre-erased.

SDP3B FlashDisk Product Manual

1.7.5.2 Limitations and Issues

The advantage of the Write without Erase and Erase Sector commands is that they shift the bulk of the erase and write time to the Erase Sector command. The Erase Sector command performs most of the normal tasks needed. To increase the speed of the Write without Erase command, the final margin verify done in a normal write command is skipped for the first 16K writes. When the cycle count (hot count) of a sector exceeds 16K, the system controller automatically reverts to a full write, including the final margin verify. Since the erase is not required in this case, a write to a pre-erased sector with a hot count of over 16K is still faster than to a sector that has not been pre-erased. The Translate Sector command can be used to determine the “hot count” of a sector.

1.7.6 Automatic Sleep Mode

A unique feature of the SanDisk SDP3B FlashDisk (and other SanDisk products) is automatic entrance and exit from sleep mode. Upon completion of a command, the SDP3B FlashDisk will enter the sleep mode to conserve power if no further commands are received within 5 msec. The host does not have to take any action for this to occur. In most systems, the SDP3B FlashDisk is in sleep mode except when the host is accessing it, thus conserving power. Note that the delay from command completion to entering sleep mode can be adjusted.

1.7.7 Dynamic Adjustment of Performance versus Power Consumption

A very unique and valuable feature of the SDP3B FlashDisk is the ability of the host to control the power the card consumes. This allows SDP3B FlashDisks to work across a broad cross section of platforms without compromising performance. For instance, it can operate in a platform that provides only 32 mA at 3.3 volts average current (of course at reduced performance) or in a platform that provides 90 mA at full performance. Please see the Set Features command for details.

1.7.8 Power Supply Requirements

This is a dual voltage product which means it will operate at a voltage range of 3.30 volts ± 5% or 5.00 volts ± 10% (± 5% for industrial versions). Per the PCMCIA specification section 2.1.1, the host system must apply 0 volts in order to change a voltage range. This same procedure of providing 0 volts to the card is required if the host system applies an input voltage outside the desired voltage by more than 20%. This means less than

4.0 volts for the 5.00 volt range and less than 2.70

volts for the 3.30 volt range.

When the host is ready to access the SDP3B FlashDisk and it is in sleep mode, any command issued to the SDP3B FlashDisk will cause it to exit sleep and respond. The host does not have to follow the ATA protocol of issuing a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead but this must be done only for the SanDisk products as other ATA products may not support this feature.

SDP3B FlashDisk Product Manual

2.0 Product Specifications

For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless otherwise stated.

2.1 SDP3B FlashDisk System Environmental Specifications

SDP3B

(Standard Version)

Temperature Operating:

Non-Operating:

Humidity Operating:

Non-Operating: Acoustic Noise: 0 dB 0 dB Vibration Operating:

Non-Operating: Shock Operating:

Non-Operating:

0° C to 60° C

-25° C to 85° C 8% to 95%, non-condensing

8% to 95%, non-condensing

15 G peak to peak max. 15 G peak to peak max.

1,000 G max. 1,000 G max.

2.2 SDP3B FlashDisk System Power Requirements

SDP3B

(Standard Version)

DC Input Voltage (VCC) 100 mV max. ripple (p-p)

+5 V Currents (maximum Average value) See Notes 1 to 3.

Capacities of

85 MB & Lower

Sleep:

Reading:

Writing:

Read/Write Peak

Capacities

above 85 MB

Sleep:

Reading:

Writing:

Read/Write Peak

3.3V ±5% 5V ± 10% 3.3V ±5% 5V ±5% Only

200 µA (Slow - Fast) 32 mA - 45 mA 32 mA - 60 mA 150 mA/50µs

200 µA (Slow - Fast) 32 mA - 50 mA 32 mA - 70 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 75 mA 46 mA - 90 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 90 mA 46 mA - 110 mA 150 mA/50µs

SDP3BI

(Industrial Version)

-40° to 85° C

-50° to 100° C 8% to 95%, non-condensing

8% to 95%, non-condensing

15 G peak to peak max. 15 G peak to peak max.

1,000 G max. 1,000 G max.

SDP3BI

(Industrial Version)

200 µA (Slow - Fast) 32 mA - 45 mA 32 mA - 60 mA 150 mA/50µs

200 µA (Slow - Fast) 32 mA - 50 mA 32 mA - 70 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 75 mA 46 mA - 90 mA 150 mA/50µs

500 µA (Slow - Fast) 46 mA - 90 mA 46 mA - 110 mA 150 mA/50µs

“Not Busy” operating state.

Note 3. The currents specified show the bounds of programmability of the product.

2.3 System Performance

All performance timings assume the SDP3B FlashDisk controller is in the default (i.e., fastest) mode.

SDP3B FlashDisk Product Manual

Start Up Times Sleep to write:

Sleep to read:

Reset to ready:

Active to Sleep Delay Programmable

Data Transfer Rate

To/From Flash

Data Transfer Rate

To/From Host

Controller Overhead Command to DRQ 1.25 msec maximum

Note: The Sleep to Write and Sleep to Read times are the times it takes the SDP3B FlashDisk to exit sleep mode

when any command is issued by the host to when the card is reading or writing. SDP3B FlashDisks do not require a reset to exit sleep mode. See section 1.7.6.

2.5 msec maximum

2.0 msec maximum 50 msec typical 400 msec maximum

4.0 MBytes/sec burst for Type II SDP3B FlashDisk

3.0 MBytes/sec burst for Type III SDP3B FlashDisk

6.0 MBytes/sec burst

2.4 System Reliability and Maintenance

MTBF (@ 25°C) 1,000,000 hours for Type II SDP3B FlashDisk

500,000 hours for Type III SDP3B FlashDisk

Preventive Maintenance None

Data Reliability

Endurance SDP3B-XX 300,000 erase / program cycles per logical sector

Endurance SDP3BI-XX Industrial Product 100,000 erase / program cycles per logical sector

<1 non-recoverable error in 1014 bits read

guaranteed

2.5 Physical Specifications

Refer to the following table and to Figures 2-1 and 2-2 for additional information.

SDP3B Type II FlashDisks SDP3B Type III FlashDisks Weight: 43 g. (1.52 oz.) maximum 90 g. (3.2 oz.) maximum Length: 85.6 ± 0.20 mm (3.370 ± .008 in.) 85.6 ± 0.20 mm (3.370 ± .008 in.)

Width: 54.0 ± 0.10 mm (2.126 ± .004 in.) 54.0 ± 0.10 mm (2.126 ± .004 in.)

Thickness: 5.0 mm max. (.1968 in.) 10.5 mm max. (0.413 in.)

SDP3B FlashDisk Product Manual

Figure 2-1 SDP3B Type II FlashDisk Dimensions

SDP3B FlashDisk Product Manual

Figure 2-2 SDP3B Type III FlashDisk Dimensions

SDP3B FlashDisk Product Manual

2.6 Capacity Specifications

The table below shows the specific capacity for the various models and the default number of heads, sectors/track and cylinders.

Model

Number

SDP3B-2 Type II 2,015,232 bytes 3,936 2 16 123 SDP3B-4 Type II 4,030,464 bytes 7,872 2 32 123 SDP3B-6 Type II 6,029,312 bytes 11,776 2 32 184

SDP3B-110 Type II or III 110,100,480 bytes 215,040 8 32 840 SDP3B-175 Type II or III 175,374,336 bytes 342,528 12 32 892 SDP3B-220 Type II or III 220,200,960 bytes 430,080 16 32 840

Form

Factor

Capacity

(formatted)

Sectors/Card

(Max LBA+1)

No. of

Heads

No. of

Sectors/

Track

No. of

Cylinders

3.0 Installation

3.1 Mounting

The Type II SDP3B FlashDisks fit into any standard PCMCIA Type II (5 mm) or Type III (10.5 mm) socket. The Type III SDP3B FlashDisks only fit into Type III PCMCIA sockets.

SDP3B FlashDisk Product Manual

4.0 SDP3B FlashDisk Interface Description

4.1 Physical Description

The host is connected to the SDP3B FlashDisk using a standard 68 pin PCMCIA connector consisting of two rows of 34 female contacts each on 50 mil (1.27 mm) centers.

4.1.1 Pin Assignments and Pin Type

The signal/pin assignments are listed in Table 4-1. Low active signals have a “-” prefix. Pin types are Input, Output or Input/Output. Table 4-2 defines the DC characteristics for all input and output type structures.

4.2 Electrical Description

The SDP3B FlashDisk is optimized for operation with hosts which support the PCMCIA I/O interface standard conforming to the PC Card ATA specification. However, the SDP3B FlashDisk may also be configured to operate in systems that support only the memory interface standard. The configuration of the SDP3B FlashDisk will be controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the SDP3B FlashDisk.

Table 4-2 describes the I/O signals. Signals whose source is the host are designated as inputs while signals that the SDP3B FlashDisk sources are outputs. The SDP3B FlashDisk logic levels conform to those specified in the PCMCIA Release

2.1 specification. Refer to section 4.3 for definitions of Input and Output type.

SDP3B FlashDisk Product Manual

Table 4-1 Pin Assignments and Pin Type

PC Card Memory Mode PC Card I/O Mode True IDE Mode

Num

Signal Name

Type

In, Out

Type

Num

Signal Name

Type 1 GND Ground 1 GND Ground 1 GND Ground 2 D03 I/O I1Z,OZ3 2 D03 I/O I1Z,OZ3 2 D03 I/O I1Z,OZ3 3 D04 I/O I1Z,OZ3 3 D04 I/O I1Z,OZ3 3 D04 I/O I1Z,OZ3 4 D05 I/O I1Z,OZ3 4 D05 I/O I1Z,OZ3 4 D05 I/O I1Z,OZ3 5 D06 I/O I1Z,OZ3 5 D06 I/O I1Z,OZ3 5 D06 I/O I1Z,OZ3 6 D07 I/O I1Z,OZ3 6 D07 I/O I1Z,OZ3 6 D07 I/O I1Z,OZ3 7 -CE1 I I3U 7 -CE1 I I3U 7 -CS0 I I3Z 8 A10 I I1Z 8 A10 I I1Z 8 A10 9 -OE I I3U 9 -OE I I3U 9 -ATA SEL I I3U

10 10 10 11 A09 I I1Z 11 A09 I I1Z 11 A09 12 A08 I I1Z 12 A08 I I1Z 12 A08 13 13 13 14 14 14

15 16

-WE I

RDY/BSY O OT1

I3U 15

-WE I

IREQ O OT1 17 VCC Power 17 VCC Power 17 VCC Power 18 VPP (Not Used) 18 VPP (Not Used) 18 VPP (Not Used) 19 19 19 20 20 20

21 21 21 22 A07 I I1Z 22 A07 I I1Z 22 A07

23 A06 I I1Z 23 A06 I I1Z 23 A06 24 A05 I I1Z 24 A05 I I1Z 24 A05 25 A04 I I1Z 25 A04 I I1Z 25 A04 26 A03 I I1Z 26 A03 I I1Z 26 A03 27 A02 I I1Z 27 A02 I I1Z 27 A02 I I1Z 28 A01 I I1Z 28 A01 I I1Z 28 A01 I I1Z 29 A00 I I1Z 29 A00 I I1Z 29 A00 I I1Z 30 D00 I/O I1Z,OZ3 30 D00 I/O I1Z,OZ3 30 D00 I/O I1Z,OZ3 31 D01 I/O I1Z,OZ3 31 D01 I/O I1Z,OZ3 31 D01 I/O I1Z,OZ3 32 D02 I/O I1Z,OZ3 32 D02 I/O I1Z,OZ3 32 D02 I/O I1Z,OZ3 33 WP O OT3 33 -IOIS16 O OT3 33 -IOCS16 O ON3 34 GND Ground 34 GND Ground 34 GND Ground

35 36 37 38 39 40 41

GND Ground

-CD1 O Ground

D11 D12 D13 D14 D15

I/O I1Z,OZ3

35 36 37 38 39 40 41

GND Ground

-CD1 O Ground

D11 D12 D13 D14 D15

I/O I1Z,OZ3 I/O I1Z,OZ3 I/O I1Z,OZ3 I/O I1Z,OZ3 I/O I1Z,OZ3

In, Out

Type

I3U 15

Num

35 36 37 38 39 40 41

Signal Name

-WE

Type

In, Out

Type

I I1Z

I I1Z I I1Z

INTRQ O OZ1

I I1Z I I1Z I I1Z I I1Z I I1Z

GND Ground

-CD1 O Ground

D11 D12 D13 D14 D15

I/O I1Z,OZ3

I3U

SDP3B FlashDisk Product Manual

Table 4-1 Pin Assignments and Pin Type (continued)

PC Card Memory Mode PC Card I/O Mode True IDE Mode

Num

42 43 44

Signal Name

-CE2

-VS1 O Ground

-IORD I I3U

45 -IOWR I

Type

I I3U

In, Out

Type

I3U

Num

42 43 44 45 -IOWR I

Signal Name

-CE2

Type

I I3U

-VS1 O Ground

-IORD I I3U

46 46 46 47 47 47 48 48 48 49 49 49 50 50 50 51 VCC Power 51 VCC Power 51 VCC Power 52 VPP (Not Used) 52 VPP (Not Used) 52 VPP (Not Used) 53 53 53 54 54 54 55 55 55 56 -CSEL I I2Z 56 -CSEL I I2Z 56 -CSEL I I2U 57 -VS2 O OPEN 57 -VS2 O OPEN 57 -VS2 O OPEN 58 RESET I I2Z 58 RESET I I2Z 58 -RESET I I2Z 59 -WAIT O OT1 59 -WAIT O OT1 59 IORDY O ON1 60 -INPACK O OT1 60 -INPACK O OT1 60 -INPACK O OZ1 61 -REG I I3U 61 -REG I I3U 61 -REG 62 BVD2 I/O I1U,OT1 62 -SPKR I/O I1U,OT1 62 -DASP I/O I1U,ON1 63 BVD1 I/O I1U,OT1 63 -STSCHG I/O I1U,OT1 63 -PDIAG I/O I1U,ON1 64 D08 65 D09 66 D10 67

-CD2 O Ground

I/O I/O I/O

I1Z,OZ3 I1Z,OZ3 I1Z,OZ3

64 D08 65 D09 66 D10 67

I/O I/O I/O

-CD2 O Ground

68 GND Ground 68 GND Ground 68 GND Ground

In, Out

Type

I3U

I1Z,OZ3 I1Z,OZ3 I1Z,OZ3

Num

42 43 44 45 -IOWR I

64 D08 65 D09 66 D10 67

Signal Name

-CS1

Type

I I3Z

-VS1 O Ground

-IORD I I3Z

I I3U

I/O I/O I/O

-CD2 O Ground

In, Out

Type

I3Z

I1Z,OZ3 I1Z,OZ3 I1Z,OZ3

Note: 1. These signals are required only for 16 bit access and not required when installed in 8-bit systems.

For lowest power dissipation, leave these signals open.

2. Should be grounded by the host.

3. Should be tied to VCC by the host.

4. Please refer to section 4.3 for definitions of In, Out type.

SDP3B FlashDisk Product Manual

Table 4-2 Signal Description

Signal Name Dir. Pin Description

A10 - A0 (PC Card Memory Mode)

A10 - A0 (PC Card I/O Mode)

A2 - A0 (True IDE Mode)

A10 - A3 (True IDE Mode)

BVD1 (PC Card Memory Mode)

-STSCHG (PC Card I/O Mode) Status Changed

-PDIAG (True IDE Mode)

BVD2 (PC Card Memory Mode)

-SPKR (PC Card I/O Mode)

-DASP (True IDE Mode)

-CD1, -CD2 (PC Card Memory Mode)

-CD1, -CD2 (PC Card I/O Mode)

-CD1, -CD2 (True IDE Mode)

-CE1, -CE2 (PC Card Memory Mode) Card Enable

-CE1, -CE2 (PC Card I/O Mode) Card Enable

-CS0, -CS1 (True IDE Mode)

I 8, 11, 12, 22,

23, 24, 25, 26,

27, 28, 29

I 27, 28, 29 In True IDE Mode only A[2:0] are used to select the one of eight

I/O 63 This signal is asserted high as the BVD1 signal since a battery

I/O 62 This output line is always driven to a high state in Memory Mode

O 36, 67 These Card Detect pins are connected to ground on the SDP3B

I 7, 42 These input signals are used both to select the card and to

These address lines along with the -REG signal are used to select the following: The I/O port address registers within the SDP3B FlashDisk, the memory mapped port address registers within the card, a byte in the card's information structure and its configuration control and status registers.

This signal is the same as the PC Card Memory Mode signal.

registers in the Task File. In True IDE Mode, these remaining address lines should be

grounded by the host.

is not used with this product. This signal is asserted low to alert the host to changes in the

RDY/-BSY and Write Protect states, while the I/O interface is configured. Its use is controlled by the Card Config and Status Register.

In the True IDE Mode, this input / output is the Pass Diagnostic signal in the Master / Slave handshake protocol.

since a battery is not required for this product. This output line is always driven to a high state in I/O Mode

since this product does not support the audio function. In the True IDE Mode, this input/output is the Disk Active/Slave

Present signal in the Master/Slave handshake protocol.

FlashDisk. They are used by the host to determine if the product is fully inserted into its socket.

This signal is the same for all modes.

indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word.

-CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multi-plexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See Tables 4-11, 4-12, 4-15, and 4-16.

This signal is the same as the PC Card Memory Mode signal.

In the True IDE Mode -CS0 is the chip select for the task file registers while -CS1 is used to select the Alternate Status Register and the Device Control Register.

SDP3B FlashDisk Product Manual

Table 4-2 Signal Description (continued)

Signal Name Dir. Pin Description

-CSEL (PC Card Memory Mode)

-CSEL (PC Card I/O Mode)

-CSEL (True IDE Mode)

D15 - D00 (PC Card Memory Mode)

D15 - D00 (PC Card I/O Mode)

D15 - D00 (True IDE Mode)

GND (PC Card Memory Mode)

GND (PC Card I/O Mode)

GND (True IDE Mode)

-INPACK ( PC Card Memory Mode)

-INPACK ( PC Card I/O Mode) Input Acknowledge

-INPACK (True IDE Mode)

-IORD (PC Card Memory Mode)

-IORD (PC Card I/O Mode)

-IORD (True IDE Mode)

I 56 This signal is not used for this mode.

This signal is not used for this mode.

This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave.

I/O 41, 40, 39, 38,

37, 66, 65, 64,

6, 5, 4, 3, 2,

32, 31, 30

-- 1, 34, 35, 68 Ground.

O 60 This signal is not used in this mode.

I 44 This signal is not used in this mode.

These lines carry the Data, Commands and Status information between the host and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word.

This signal is the same as the PC Card Memory Mode signal.

In True IDE Mode, all Task File operations occur in byte mode on the low order bus D00-D07 while all data transfers are 16 bit using D00-D15.

This signal is the same for all modes.

The Input Acknowledge signal is asserted by the SDP3B FlashDisk when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the card and the CPU.

In True IDE Mode this output signal is not used and should not be connected at the host.

This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the SDP3B FlashDisk when the card is configured to use the I/O interface.

In True IDE Mode, this signal has the same function as in PC Card I/O Mode.

SDP3B FlashDisk Product Manual

Table 4-2 Signal Description (continued)

Signal Name Dir. Pin Description

-IOWR (PC Card Memory Mode)

-IOWR (PC Card I/O Mode)

-IOWR (True IDE Mode)

I 45 This signal is not used in this mode.

The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the SDP3B FlashDisk controller registers when the product is configured to use the I/O interface.

The clocking will occur on the negative to positive edge of the signal (trailing edge).

In True IDE Mode, this signal has the same function as in PC Card I/O Mode.

-OE (PC Card Memory Mode)

-OE (PC Card I/O Mode)

-ATA SEL (True IDE Mode)

RDY/-BSY (PC Card Memory Mode)

-IREQ ( PC Card I/O Mode)

INTRQ (True IDE Mode)

-REG (PC Card Memory Mode) Attribute Memory Select

-REG (PC Card I/O Mode)

-REG (True IDE Mode)

I 9 This is an Output Enable strobe generated by the host interface.

It is used to read data from the SDP3B FlashDisk in Memory Mode and to read the CIS and configuration registers.

In PC Card I/O Mode, this signal is used to read the CIS and configuration registers.

To enable True IDE Mode this input should be grounded by the host.

O 16 In Memory Mode this signal is set high when the SDP3B

FlashDisk is ready to accept a new data transfer operation and held low when the card is busy. The Host memory card socket must provide a pull-up resistor.

At power up and at Reset, the RDY/-BSY signal is held low (busy) until the SDP3B FlashDisk has completed its power up or reset function. No access of any type should be made to the SDP3B FlashDisk during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The SDP3B FlashDisk has been powered up with +RESET continuously disconnected or asserted.

I/O Operation - After the SDP3B FlashDisk Card has been configured for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt.

In True IDE Mode signal is the active high Interrupt Request to the host.

I 61 This signal is used during Memory Cycles to distinguish between

Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory.

The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus.

In True IDE Mode this input signal is not used and should be connected to VCC by the host.

SDP3B FlashDisk Product Manual

Table 4-2 Signal Description (continued)

Signal Name Dir. Pin Description

RESET (PC Card Memory Mode)

RESET (PC Card I/O Mode)

-RESET (True IDE Mode)

VCC (PC Card Memory Mode)

VCC (PC Card I/O Mode)

VCC (True IDE Mode)

VPP (PC Card Memory Mode)

VPP (PC Card I/O Mode)

VPP (True IDE Mode)

-VS1

-VS2 (PC Card Memory Mode)

-VS1

-VS2 (PC Card I/O Mode)

-VS1

-VS2 (True IDE Mode)

-WAIT (PC Card Memory Mode)

-WAIT (PC Card I/O Mode)

IORDY (True IDE Mode)

I 58 When the pin is high, this signal resets the SDP3B FlashDisk.

The card is Reset only at power up if this pin is left high or open from power-up. The card is also reset when the Soft Reset bit in the Card Configuration Option Register is set.

This signal is the same as the PC Card Memory Mode signal.

In the True IDE Mode this input pin is the active low hardware reset from the host.

-- 17, 51 +5 V, +3.3 V power.

This signal is the same for all modes.

18, 52 Programming Voltage power supply is not connected on the

SDP3B FlashDisk products. This signal is the same for all modes.

This signal is the same for all modes.

O 43

O 59 The -WAIT signal is driven low by the SDP3B FlashDisk to signal

Voltage Sense Signals. -VS1 is grounded so that the SDP3B FlashDisk CIS can be read at 3.3 volts and -VS2 is open and reserved by PCMCIA for a secondary voltage.

This signal is the same for all modes.

the host to delay completion of a memory or I/O cycle that is in progress.

This signal is the same as the PC Card Memory Mode signal.

In True IDE Mode this output signal may be used as IORDY.

-WE (PC Card Memory Mode)

-WE (PC Card I/O Mode)

-WE (True IDE Mode)

I 15 This is a signal driven by the host and used for strobing memory

write data to the registers of the SDP3B FlashDisk when the card is configured in the memory interface mode. It is also used for writing the configuration registers.

In PC Card I/O Mode, this signal is used for writing the configuration registers.

In True IDE Mode this input signal is not used and should be connected to VCC by the host.

SDP3B FlashDisk Product Manual

Table 4-2 Signal Description (continued)

Signal Name Dir. Pin Description

WP (PC Card Memory Mode) Write Protect

-IOIS16 ( PC Card I/O Mode)

-IOCS16 (True IDE Mode)

O 33 Memory Mode - The SDP3B FlashDisk does not have a write

protect switch. This signal is held low after the completion of the reset initialization sequence.

I/O Operation - When the SDP3B FlashDisk is configured for I/O Operation, Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port.

In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle.

SDP3B FlashDisk Product Manual

4.3 Electrical Specification

The following table defines all D.C.

Absolute Maximum conditions are:

Characteristics for the SDP3B FlashDisk.

Vcc = -0.3V min. to 7.0V max.

Unless otherwise stated, conditions are:

V* = -0.5V min. to Vcc + 0.5V max.

SDP3B SDP3BI

* Voltage on any pin except Vcc with respect to

Vcc = 5V ±10% Vcc = 5V ± 5%

GND.

Vcc = 3.3V ± 5% Vcc = 3.3V ± 5% Ta = 0°C to 60°C Ta = -40°C to 85°C

4.3.1 Input Leakage Current

Note: In the table below, x refers to the characteristics described in section 4.3.2. For example, I1U indicates a

pull up resistor with a type 1 input characteristic.

Type Parameter Symbol Conditions MIN TYP MAX Units

IxZ Input Leakage Current IL Vih = Vcc / Vil = Gnd -1 1 µA IxU Pull Up Resistor RPU1 Vcc = 5.0V 50k 500k Ohm IxD Pull Down Resistor RPD1 Vcc = 5.0V 50k 500k Ohm

Note: The minimum pullup resistor leakage current meets the PCMCIA specification of 10k ohms but is

intentionally higher in the SDP3B FlashDisk to reduce power use.

4.3.2 Input Characteristics

Type Parameter Symbol MIN TYP MAX MIN TYP MAX Units

VCC = 3.3 V VCC = 5.0 V

1 Input Voltage

CMOS

2 Input Voltage

CMOS

3 Input Voltage

CMOS

Schmitt Trigger

Vih

Vil

Vih

Vil

Vth

Vtl

2.4

1.5

1.8

1.0

0.6

2.4

0.8

2.0

0.8

2.8

2.0

Volts

SDP3B FlashDisk Product Manual

4.3.3 Output Drive Type

Note: In the table below, x refers to the characteristics described in section 4.3.4. For example, OT3 refers to

Totempole output with a type 3 output drive characteristic.

Type Output Type Valid Conditions

OTx Totempole Ioh & Iol OZx Tri-State N-P Channel Ioh & Iol OPx P-Channel Only Ioh Only ONx N-Channel Only Iol Only

4.3.4 Output Drive Characteristics

Type Parameter Symbol Conditions MIN TYP MAX Units

1 Output Voltage Voh

Vol

2 Output Voltage Voh

Vol

3 Output Voltage Voh

Vol

X Tri-State

Leakage Current

Ioz Vol = Gnd

Ioh = -4 mA

Iol = 4 mA

Ioh = -8 mA

Iol = 8 mA

Ioh = -8 mA

Iol = 8 mA

Voh = Vcc

Vcc

-0.8V Gnd

+0.4V

Vcc

-0.8V Gnd

+0.4V

Vcc

-0.8V Gnd

+0.4V

-10 10 µA

Volts

SDP3B FlashDisk Product Manual

4.3.5 Interface/Bus Timing

There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard Release 2.1. The SDP3B FlashDisk conforms to the timing in that reference document.

Table 4-3 Attribute Memory Read Timing

Speed Version 300 ns

Item Symbol IEEE Symbol Min ns. Max ns.

Read Cycle Time tc(R) tAVAV 300

Address Access Time ta(A) tAVQV 300

Card Enable Access Time ta(CE) tELQV 300

Output Enable Access Time ta(OE) tGLQV 150

Output Disable Time from CE tdis(CE) tEHQZ 100

Output Disable Time from OE tdis(OE) tGHQZ 100

Address Setup Time tsu (A) tAVWL 30

Output Enable Time from CE ten(CE) tELQNZ 5

Output Enable Time from OE ten(OE) tGLQNZ 5

Data Valid from Address Change tv(A) tAXQX 0

4.3.6 Attribute Memory Read Timing Specification

The Attribute Memory access time is defined as 300 ns. Detailed timing specifications are shown in Table 4-3.

tc(R)

-REG

ta(A)

tsu(A)

ta(CE)

tv(A)

-CE

ten(CE)

ta(OE)

tdis(CE)

-OE

ten(OE)

tdis(OE)

Dout

Figure 4-1 Attribute Memory Read Timing Diagram

Notes: All times are in nanoseconds. Dout signifies data provided by the SDP3B FlashDisk to the system. The -CE

signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations.

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