sandisk SDAT2FAH-128, SDBT2FAH-256, SDBT2FCH-512, SDBT2FCH-1024 User guide

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TriFlash with

Secure Digital (SD) Interface

Product Manual

(Preliminary)

CORPORATE HEADQUARTERS

140 Caspian Court

Sunnyvale, CA 94089-1000

408-542-0500

FAX: 408-542-0503

URL: http://www.sandisk.com

SanDisk® Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages.

The information in this manual is subject to change without notice.

SanDisk Corporation shall not be liable for technical or editorial errors or omissions contained herein; nor for incidental or consequential damages resulting from the furnishing, performance, or use of this material.

All parts of the TriFlash documentation are protected by copyright law and all rights are reserved. This documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior consent, in writing, from SanDisk Corporation.

SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation.

Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

SanDisk products are covered or licensed under one or more of the following U.S. Patent Nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and pending.

Lit. No. 80-13-00171 Rev. 1.2 3/2003 Printed in U.S.A.

Revision History

• Revision 0.1—Preliminary draft.

• Revision 0.5—First edits from marketing and engineering.

• Revision 0.8—Manual reformatted, minor editorial and technical changes.

• Revision 0.9—Minor editorial and technical changes.

• Revision 1.0—Minor editorial and technical changes to figures.

• Revision 1.1—Minor editorial and technical changes.

• Revision 1.2—Changed power requirements in Section 2.2, Table 2.2; updated addresses in Appendix A

Table of Contents

1. Introduction to the TriFlash with SD Interface .................................................................................................. 1-1

1.1. Scope................................................................................................................................................. 1-2

1.2. Product Models ................................................................................................................................. 1-2

1.3. System Features................................................................................................................................. 1-2

1.4. SD Memory Card Standard ............................................................................................................... 1-3

1.5. Functional Description ...................................................................................................................... 1-3

1.5.1. Flash Technology Independence............................................................................................. 1-4

1.5.2. Defect and Error Management................................................................................................ 1-4

1.5.3. Endurance ............................................................................................................................... 1-4

1.5.4. Wear Leveling......................................................................................................................... 1-4

1.5.5. Using the Erase Command...................................................................................................... 1-5

1.5.6. Automatic Sleep Mode............................................................................................................ 1-5

1.5.7. TriFlash—SD Bus Mode ........................................................................................................ 1-5

1.5.7.1. TriFlash Standard Compliance .............................................................................. 1-5

1.5.7.2. Negotiating Operation Conditions ......................................................................... 1-5

1.5.7.3. Device Acquisition and Identification ................................................................... 1-5

1.5.7.4. Device Status ......................................................................................................... 1-6

1.5.7.5. Memory Array Partitioning.................................................................................... 1-6

1.5.7.6. Read and Write Operations.................................................................................... 1-8

1.5.7.7. Data Transfer Rate................................................................................................. 1-9

1.5.7.8. Data Protection ...................................................................................................... 1-9

1.5.7.9. Erase ...................................................................................................................... 1-9

1.5.7.10. Write Protection................................................................................................... 1-9

1.5.7.11. Optional Copyright Protection............................................................................. 1-9

1.5.7.12. Copy Bit............................................................................................................... 1-10

1.5.7.13. The CSD Register ................................................................................................ 1-10

1.5.8. TriFlash—SPI Mode ............................................................................................................... 1-10

1.5.8.1. Negotiating Operating Conditions ......................................................................... 1-10

1.5.8.2. Card Acquisition and Identification....................................................................... 1-10

1.5.8.3. Card Status............................................................................................................. 1-10

1.5.8.4. Memory Array Partitioning.................................................................................... 1-10

1.5.8.5. Read and Write Operations.................................................................................... 1-11

1.5.8.6. Data Transfer Rate................................................................................................. 1-11

1.5.8.7. Data Protection in the TriFlash.............................................................................. 1-11

1.5.8.8. Erase ...................................................................................................................... 1-11

1.5.8.9. Write Protection..................................................................................................... 1-11

2. Product Specifications ........................................................................................................................................ 2-1

2.1. System Environmental Specifications............................................................................................... 2-1

2.2. Typical Power Requirements ............................................................................................................ 2-1

2.3. System Performance.......................................................................................................................... 2-2

2.4. System Reliability and Maintenance................................................................................................. 2-2

2.5. Physical Specifications...................................................................................................................... 2-3

3. TriFlash Interface Description............................................................................................................................ 3-1

3.1. General Description of Pins and Registers........................................................................................ 3-1

3.1.1. Pin Assignments in SD Bus Mode.......................................................................................... 3-1

3.1.2. Pin Assignments in SPI Mode................................................................................................. 3-2

3.1.3. Registers.................................................................................................................................. 3-2

3.2. SD Bus Topology.............................................................................................................................. 3-3

3.3. SPI Bus Topology ............................................................................................................................. 3-5

3.4. Electrical Interface ............................................................................................................................ 3-6

3.4.1. Power-up ................................................................................................................................. 3-6

iii

Table of Contents

3.4.2. Bus Operating Conditions....................................................................................................... 3-8

3.4.3. Bus Signal Levels.................................................................................................................... 3-9

3.4.4. Bus Timing.............................................................................................................................. 3-10

3.4.5. TriFlash-Specific Functions.................................................................................................... 3-12

3.4.5.1. Ready/Busy Function [Output].............................................................................. 3-12

3.4.5.2. Write Protect Function [Input + Pullup] ................................................................ 3-12

3.4.5.3. Reset Function [Input + Pullup]............................................................................. 3-12

3.5. TriFlash Registers ............................................................................................................................. 3-12

3.5.1. Operating Conditions Register (OCR) .................................................................................... 3-12

3.5.2. Card Identification (CID) Register.......................................................................................... 3-14

3.5.3. CSD Register........................................................................................................................... 3-14

3.5.4. SCR Register........................................................................................................................... 3-21

3.5.5. Status Register......................................................................................................................... 3-22

3.5.6. SD Status................................................................................................................................. 3-24

3.5.7. RCA Register .......................................................................................................................... 3-25

3.5.8. TriFlash Registers in SPI Mode .............................................................................................. 3-25

3.6. Standard Data Interchange Format and Card Sizes........................................................................... 3-25

3.6.1. Data Interchange Format and Card Sizes with Optional Security........................................... 3-25

4. Secure Digital (SD) Bus Protocol Description ................................................................................................... 4-1

4.1. SD Bus Protocol................................................................................................................................ 4-1

4.2. Protocol’s Functional Description..................................................................................................... 4-4

4.3. Card Identification Mode .................................................................................................................. 4-5

4.3.1. Reset........................................................................................................................................ 4-6

4.3.2. Operating Voltage Range Validation ...................................................................................... 4-7

4.3.3. Device Identification Process.................................................................................................. 4-8

4.4. Data Transfer Mode .......................................................................................................................... 4-8

4.4.1. Wide Bus Selection/Deselection ............................................................................................. 4-10

4.4.2. Data Read Format ................................................................................................................... 4-10

4.4.3. Data Write Format .................................................................................................................. 4-11

4.4.4. Write Protect Management ..................................................................................................... 4-13

4.4.4.1. Device’s Internal Write Protection (Optional)....................................................... 4-13

4.4.5. Card Lock/Unlock................................................................................................................... 4-13

4.4.6. Application Specific Commands............................................................................................. 4-13

4.5. Clock Control .................................................................................................................................... 4-14

4.6. Cyclic Redundancy Codes (CRC)..................................................................................................... 4-15

4.7. Error Conditions................................................................................................................................ 4-17

4.7.1. CRC and Illegal Command ..................................................................................................... 4-17

4.7.2. Read, Write and Erase Time-out Conditions .......................................................................... 4-17

4.8. Commands......................................................................................................................................... 4-17

4.8.1. Command Types ..................................................................................................................... 4-18

4.8.2. Command Format.................................................................................................................... 4-18

4.8.3. Command Classes ................................................................................................................... 4-18

4.8.4. Detailed Command Description.............................................................................................. 4-20

4.9. Card State Transition Table............................................................................................................... 4-24

4.10. Responses........................................................................................................................................ 4-26

4.11. Timings ........................................................................................................................................... 4-27

4.11.1. Command and Response....................................................................................................... 4-27

4.11.2. Data Read.............................................................................................................................. 4-28

4.11.3. Data Write............................................................................................................................. 4-29

4.11.4. Timing Values....................................................................................................................... 4-31

Table of Contents

5. SPI Protocol Definition ...................................................................................................................................... 5-1

5.1. SPI Bus Protocol ............................................................................................................................... 5-1

5.1.1. Mode Selection ....................................................................................................................... 5-1

5.1.2. Bus Transfer Protection .......................................................................................................... 5-2

5.1.3. Data Read................................................................................................................................ 5-2

5.1.4. Data Write............................................................................................................................... 5-3

5.1.5. Erase and Write Protect Management..................................................................................... 5-4

5.1.6. Read CID/CSD Registers........................................................................................................ 5-5

5.1.7. Reset Sequence ....................................................................................................................... 5-5

5.1.8. Clock Control.......................................................................................................................... 5-5

5.1.9. Error Conditions...................................................................................................................... 5-6

5.1.9.1. CRC and Illegal Commands .................................................................................. 5-6

5.1.9.2. Read, Write and Erase Time-out Conditions ......................................................... 5-6

5.1.10. Memory Array Partitioning................................................................................................... 5-6

5.1.11. Card Lock/Unlock................................................................................................................. 5-7

5.1.12. Application Specific Commands...........................................................................................5-7

5.1.13. Copyright Protection Commands.......................................................................................... 5-7

5.2. SPI Command Set ............................................................................................................................. 5-7

5.2.1. Command Format.................................................................................................................... 5-7

5.2.2. Command Classes ................................................................................................................... 5-7

5.2.2.1. Detailed Command Description............................................................................. 5-8

5.2.3. Responses................................................................................................................................ 5-12

5.2.3.1. Format R1 ..............................................................................................................5-12

5.2.3.2. Format R1b ............................................................................................................ 5-12

5.2.3.3. Format R2 ..............................................................................................................5-12

5.2.3.4. Format R3 ..............................................................................................................5-13

5.2.3.5. Data Response ....................................................................................................... 5-14

5.2.4. Data Tokens ............................................................................................................................ 5-14

5.2.5. Data Error Token .................................................................................................................... 5-15

5.2.6. Clearing Status Bits................................................................................................................. 5-15

5.3. Card Registers ................................................................................................................................... 5-15

5.4. SPI Bus Timing Diagrams................................................................................................................. 5-15

5.4.1. Command/Response................................................................................................................ 5-16

5.4.2. Data Read................................................................................................................................ 5-17

5.4.3. Data Write............................................................................................................................... 5-17

5.4.4. Timing Values......................................................................................................................... 5-18

5.5. SPI Electrical Interface...................................................................................................................... 5-18

5.6. SPI Bus Operating Conditions .......................................................................................................... 5-19

5.7. Bus Timing........................................................................................................................................ 5-19

Appendix A. Ordering Information........................................................................................................................ A-1

Appendix B. Technical Support Services............................................................................................................... B-1

Appendix C. SanDisk Worldwide Sales Offices .................................................................................................... C-1

Appendix D. Limited Warranty.............................................................................................................................. D-1

Table of Contents

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1. Introduction to the TriFlash with SD Interface

The SanDisk TriFlash is a very small, flash storage device, designed specifically for storage applications that put a premium on small form factor, low power and low cost. Flash is the ideal storage medium for portable, batterypowered devices. It features low power consumption and is non-volatile, requiring no power to maintain the stored data. It also has a wide operating range for temperature, shock and vibration.

TriFlash is well suited to meet the needs of small, low power, electronic devices. With a form factor as small as 10 mm by 12 mm and 1.1 mm thick, TriFlash is expected to be used in a wide variety of portable devices like mobile phones, pagers, and voice recorders.

To support this wide range of applications, the TriFlash is offered with either the MultiMediaCard (see TriFlash with MultiMediaCard Interface Product Manual) or Secure Digital (SD) interface. The SD interface product is fully compatible with SD cards, provides a 4-bit data bus for maximum performance, and, optionally, has the full SD security features. For compatibility with existing controllers, the TriFlash offers, in addition to these interfaces, an alternate communication protocol based on the SPI standard.

These interfaces allow for easy integration into any design, regardless of microprocessor used. All device and interface configuration data (such as maximum frequency and card identification) are stored on the device.

The TriFlash provides up to 1024 million bits of memory using SanDisk Flash memory chips, which were designed by SanDisk especially for use in mass storage applications. In addition to the mass storage specific flash memory chip, the TriFlash includes an intelligent controller, which manages interface protocols, and data storage and retrieval, as well as Error Correction Code (ECC) algorithms, defect handling and diagnostics, power management and clock control. Figure 1-1 is a block diagram of the TriFlash with SD Interface.

Data

In/Ou

Contro

Data

Flash

Module

SD Bus/SPI Bus

SanDisk

Single

Chip

Controlle

Interface

SanDisk TriFlash

Figure 1-1. TriFlash with SD Interface Block Diagram

1-1

Introduction to the TriFlash with SD Interface

1.1. Scope

This document describes the key features and specifications of the TriFlash with SD interface, as well as the information required to interface this product to a host system.

1.2. Product Models

The TriFlash is available in the capacities shown in Table 1-1.

Table 1-1. TriFlash Capacities

SD Model No. Capacities

SDAT2FAH-128 128 Mb

SDBT2FAH-256 256 Mb

SDBT2FCH-512 512 Mb

SDBT2FCH-1024 1024 Mb

1.3. System Features

TriFlash provides the following system features:

• Up to 1024 Mbits of data storage.

• SD Memory Card protocol compatible.

• Supports SPI Mode.

• Targeted for portable and stationary applications for secured (copyrights protected) and non-secured

data storage.

• Voltage range:

− Basic communication (CMD0, CMD15, CMD55, ACMD41): 2.0—3.6V.

− Other commands and memory access: 2.7—3.6V.

• Variable clock rate 0—25 MHz.

• Up to 12.5MByte/sec data transfer rate (using 4 parallel data lines).

• Maximum data rate with up to 10 devices or cards.

• Correction of memory field errors.

• Optional Copyrights Protection Mechanism—Complies with highest security of SDMI standard.

• Built-in write protection features (permanent and temporary).

• Application specific commands.

• Comfortable erase mechanism.

• Standard footprint across all capacities.

Introduction to the TriFlash with SD Interface

The performance of the communication channel is described in Table 1-2.

Table 1-2. SD Bus/SPI Bus Comparison

TriFlash Using SD Bus TriFlash Using SPI Bus

Six-wire communication channel (clock, command, 4 data lines).

Error-protected data transfer. Optional non-protected data transfer mode available.

Single or multiple block oriented data transfer. Single or multiple block oriented data transfer.

Three-wire serial data bus (Clock, dataIn, dataOut) + card specific CS signal (hardwired card selection).

1.4. SD Memory Card Standard

The SanDisk TriFlash is fully compatible with the SD Memory Card Physical Layer Specification standard listed below:

The SD Memory Card Physical Layer System Specification Version 1.01

This specification may be obtained from:

SD Card Association 53 Muckelemi St. P.O. Box 189 San Juan Bautista, CA 95045-0189 USA Phone: 831-623-2107 Fax: 831-623-2248 Email: rcreech@sdcard.org

http://www.sdcard.org

1.5. Functional Description

The SanDisk TriFlash contains a high level, intelligent subsystem as shown in the block diagram, Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities not found in other types of devices. These capabilities include:

• Host independence from details of erasing and programming flash memory.

• Sophisticated system for managing defects (analogous to systems found in magnetic disk drives).

• Sophisticated system for error recovery including a powerful error correction code (ECC).

• Power management for low power operation.

1-3

Introduction to the TriFlash with SD Interface

1.5.1. Flash Technology Independence

The 512-byte sector size of the TriFlash is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the TriFlash. This command contains the address. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the TriFlash uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the TriFlash today will be able to access future SanDisk TriFlash devices built with new flash technology without having to update or change host software.

1.5.2. Defect and Error Management

The TriFlash contains a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. The TriFlash does a read after write under margin conditions to verify that the data is written correctly. In the rare case that a bit is found to be defective, the TriFlash replaces this bad bit with a spare bit within the sector header. If necessary, the TriFlash will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.

The TriFlash device’s soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, the TriFlash has innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ a powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.

These defect and error management systems coupled with the solid-state construction give the TriFlash unparalleled reliability.

1.5.3. Endurance

The SanDisk TriFlash has an endurance specification for each sector of 300,000 or 100,000 writes (reading a logical sector is unlimited) under typical conditions (depending on the model, refer to Table 2-4). This is far beyond what is needed in nearly all applications of TriFlash devices. Even very heavy use of the TriFlash in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 34 years to wear out an area on the TriFlash on which a file of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.

With typical applications, the endurance limit is not of any practical concern to the vast majority of users.

1.5.4. Wear Leveling

The SanDisk TriFlash does not require or perform a Wear Level operation.

Introduction to the TriFlash with SD Interface

1.5.5. Using the Erase Command

The Erase command provides the capability to substantially increase the write performance of the TriFlash. Once a sector has been erased using the Erase command, a write to that sector will be much faster. This is because a normal write operation includes a separate sector erase prior to write.

1.5.6. Automatic Sleep Mode

A unique feature of the SanDisk TriFlash (and other SanDisk products) is automatic entrance and exit from sleep mode. Upon completion of an operation, the TriFlash will enter the sleep mode to conserve power if no further commands are received within 5 msec. The host does not have to take any action for this to occur. In most systems, the TriFlash is in sleep mode except when the host is accessing it, thus conserving power.

When the host is ready to access the TriFlash and it is in sleep mode, any command issued to the TriFlash will cause it to exit sleep and respond.

1.5.7. TriFlash—SD Bus Mode

The following sections provide valuable information for TriFlash in SD Bus Mode.

1.5.7.1. TriFlash Standard Compliance

The TriFlash is fully compliant with the SD Memory Card Physical Layer Standard Specification V1.01. The structure of the Card Specific Data (CSD) register is compliant with CSD Structure 1.0.

1.5.7.2. Negotiating Operation Conditions

The TriFlash supports the operation condition verification sequence defined in the SD Memory Card Standard Specifications. Should the TriFlash host define an operating voltage range, which is not supported by the TriFlash, it will put itself in an inactive state and ignore any bus communication. The only way to get the TriFlash out of the inactive state is by powering it down and up again.

In addition, the host can explicitly send the TriFlash to the inactive state by using the GO_INACTIVE_STATE command.

1.5.7.3. Device Acquisition and Identification

The SD bus is a single master (TriFlash host application) and multi-slaves (devices) bus. The Clock and Power lines are common to all devices on the bus. During the identification process, the host accesses each device separately through its own command lines. The TriFlash device’s CID register is pre-programmed with a unique card identification number, which is used during the identification procedure.

1-5

Introduction to the TriFlash with SD Interface

In addition, the TriFlash host can read the device’s CID register using the READ_CID command. The CID register is programmed during the TriFlash testing and formatting procedure, on the manufacturing floor. The TriFlash host can only read this register and not write to it.

An internal pull-up resistor on the DAT3 line may be used for device detection (insertion/removal). The resistor can be disconnected during data transfer (using ACMD42).

1.5.7.4. Device Status

The device status is separated into two fields: CardStatus and SD_Status.

• CardStatus is stored in a 32 bit status register which is sent as the data field in the card response to

host commands. Status register provides information about the device’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.

• SD_Status is stored in 512 bits, which are sent as a single data block after it was requested by the host

using the SD_STATUS (ACMD13) command. SD_STATUS contains extended status bits that relate to BUS_WIDTH, security related bits and future specific applications.

1.5.7.5. Memory Array Partitioning

The basic unit of data transfer to/from the TriFlash is one byte. All data transfer operations which require a block size always define block lengths as integer multiples of bytes. Some special functions need other partition granularity.

For block-oriented commands, the following definition is used:

• Block—The unit that is related to the block oriented read and write commands. Its size is the number

of bytes that will be transferred when one block command is sent by the host. The size of a block is either programmable or fixed. The information about allowed block sizes and the programmability is stored in the CSD.

The granularity of the erasable units is in general not the same as for the block-oriented commands:

• Sector—The unit that is related to the erase commands. Its size is the number of blocks that will be

erased in one portion. The size of a sector is fixed for each device. The information about the sector size (in blocks) is stored in the CSD.

For devices that include write protection, the following definition is used:

• WP Group—The minimal unit that may have individual write protection. Its size is the number of

groups that will be write protected by one bit. The size of a WP-group is fixed for each device. The information about the size is stored in the CSD.

Introduction to the TriFlash with SD Interface

TriFlash

WP Group 0

Sector 1

Block

Sector 2

Sector 3

Sector n

WP Group 1

WP Group n

Protected Area (Copyright protection)

Sector 1

Block

Sector n

Figure 1-2. Memory Array Partitioning

Table 1-3. Memory Array Structures Summary

Part Number Block Size

(Byte)

SDBT2FCH-1024 512 -- 250, 880

SDBT2FCH-512 512 -- 125,440

SDBT2FAH-256 512 -- 62,720

SDAT2FAH-128 512 -- 31,360

All measurements are in units per card.

The part of the TriFlash with separate DOS partitioning that includes sectors and blocks. The card write protection mechanism

does not affect this area.

Protected Area

Size (Blocks)

User Area

(Blocks)

1-7

Introduction to the TriFlash with SD Interface

1.5.7.6. Read and Write Operations

The TriFlash supports two read/write modes as shown in Figure 1-3.

Multiple Block Mode

Memory Sectors

Address

Start

Memory Sectors

Stop StopStart

Memory Sectors

ReadWrite

Memory Sectors

Single Block Mode Misalignment Error

Memory Sectors

Start

Address

(Read)

Memory Sectors

Start

Address

(Write)

Memory Sectors

Figure 1-3. Data Transfer Formats

Memory Sectors

Start

Address

(Read/Write)

Memory Sectors

Single Block Mode

In this mode the host reads or writes one data block in a pre-specified length. The data block transmission is protected with 16-bit CRC, which is generated by the sending unit and checked by the receiving unit.

The block length, for read operations, is limited by the device sector size (512 bytes) but can be as small as a single byte. Misalignment is not allowed. Every data block must be contained in a single physical sector.

The block length for write operations must be identical to the sector size and the start address aligned to a sector boundary.

Multiple Block Mode

This mode is similar to the single block mode, but the host can read/write multiple data blocks (all have the same length), which will be stored or retrieved from contiguous memory addresses starting at the address specified in the command.

The operation is terminated with a stop transmission command.

Misalignment and block length restrictions apply to multiple blocks as well and are identical to the single block read/write operations.

Introduction to the TriFlash with SD Interface

1.5.7.7. Data Transfer Rate

The TriFlash can be operated using either a single data line (DAT0) or four data lines (DAT0-DAT3) for data transfer. The maximum data transfer rate for a single data line is 25 Mb per second and for four data lines it is 100 Mb (12.5 MB) per second.

1.5.7.8. Data Protection

Every sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.

1.5.7.9. Erase

The smallest erasable unit in the TriFlash is a sector. In order to speed up the erase procedure, multiple sectors can be erased at the same time.

To facilitate selection, a first command with the starting address is followed by a second command with the final address, and all sectors within this range will be selected for erase.

1.5.7.10. Write Protection

Two device level write protection options are available: permanent and temporary. Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared. This feature is implemented in the TriFlash controller firmware and not with a physical OTP cell.

1.5.7.11. Optional Copyright Protection

A detailed description of the optional Copyright Protection mechanism and related security commands can be found in the SD Memory Card Security Specification document from the SD Card Association. All TriFlash security related commands operate in the data transfer mode.

As defined in the SDMI specification, the data content that is saved in the device is saved already encrypted and it passes transparently to and from the device. No operation is done on the data and there is no restriction to read the data at any time. Associated with every data packet (song, for example) that is saved in the unprotected memory there is a special data that is saved in a protected memory area. For any access (any Read, Write or Erase command) from/to the data in the protected area. For an authentication procedure is done between the TriFlash and the connected device, either the LCM (PC for example) or the PD (portable device, such as SD player). After the authentication process passes, the TriFlash is ready to accept or give data from/to the connected device. While the TriFlash is in the secured mode of operation (after the authentication succeeded) the argument and the associated data that is sent to the TriFlash or read from the TriFlash are encrypted. At the end of the Read, Write or Erase operation, the TriFlash automatically gets out of its secured mode.

1-9

Introduction to the TriFlash with SD Interface

1.5.7.12. Copy Bit

The content of a TriFlash can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared. The Copy bit of the TriFlash is programmed (during test and formatting on the manufacturing floor) as a copy. The TriFlash can be purchased with the copy bit set (copy) or cleared, indicating the TriFlash is a master. This feature is implemented in the TriFlash controller firmware and not with a physical OTP cell.

1.5.7.13. The CSD Register

All the configuration information of the TriFlash is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contain the host controlled data, the card Copy, write protection and the user file format indication.

The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.

1.5.8. TriFlash—SPI Mode

The SPI mode is a secondary communication protocol for TriFlash devices. This mode is a subset of the SD Bus protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.

1.5.8.1. Negotiating Operating Conditions

The operating condition negotiation function of the SD Bus is supported differently in SPI mode by using the READ_OCR (CMD58) command. The host shall work within the valid voltage range (2.7 to 3.6 volts) of the device or put the device in an inactive state by sending a GO_INACTIVE command to the device.

1.5.8.2. Card Acquisition and Identification

The host must know the number of devices currently connected on the bus. Specific device selection is done via the CS signal. The internal pull-up resistor on the CD line may be used for device detection (insertion/removal).

1.5.8.3. Card Status

In SPI mode, only 16 bits (containing the errors relevant to SPI mode) can be read out of the 32-bit TriFlash status register. The SD_STATUS can be read using ACMD13, the same as in SD Bus mode.

1.5.8.4. Memory Array Partitioning

Memory partitioning in SPI mode is equivalent to SD Bus mode. All read and write commands are byte addressable with the limitations given in section 1.5.7.5 above.

Introduction to the TriFlash with SD Interface

1.5.8.5. Read and Write Operations

In SPI mode, both single and multiple block data transfer modes are supported.

1.5.8.6. Data Transfer Rate

In the SPI mode, only one data line is used for each direction. The SPI mode data transfer rate is the same as the SD Bus mode data transfer rate when using one data line only (up to 25Mbits per second).

1.5.8.7. Data Protection in the TriFlash

Same as for the SD Bus mode.

1.5.8.8. Erase

Same as in SD Bus mode.

1.5.8.9. Write Protection

Same as in SD Bus mode.

1-11

Introduction to the TriFlash with SD Interface

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2. Product Specifications

For the specifications in the following sections, values are defined at ambient temperature and nominal supply voltage unless otherwise stated.

2.1. System Environmental Specifications

Table 2-1. System Environmental Specifications

Temperature Operating:

Humidity Operating:

ESD Protection ± 2kV, Human body model

Vibration Operating:

Shock Operating:

Altitude (relative to sea level) Operating:

2.2. Typical Power Requirements

Table 2-2. Power Requirements

VDD (ripple: max, 60 mV peak to peak) 2.7 V—3.6 V

(Ta = -25 – 85C)

@ VDD = 2.7V @ VDD = 3.6V

Operating current (maximum rates) Fclk = 25 MHz, 0.5 Mbyte/s Read/Write speed

Non-Operating:

Read: 30 mA Write: 35 mA

-25° C to 85° C

-40° C to 85° C

8% to 95%, non-condensing 8% to 95%, non-condensing

15 G peak to peak max. 15 G peak to peak max.

1,000 G max. 1,000 G max.

80,000 feet max. 80,000 feet max.

Read: 40 mA Write: 45 mA

(Ta = -25 – 85C)

Typical Maximum

@ 2.7 V 40 uA 120 uA

Sleep Current

@3.3 V 50 uA 150 uA

2-1

Product Specifications

2.3. System Performance

Table 2-3. System Performance1

Typical Maximum

Block Read Access Time 1.5 msec 100 msec

CMD1 to Ready (after power up) 50 msec 100 msec

Sleep to Ready 1 msec 2 msec

2.4. System Reliability and Maintenance

Table 2-4. System Reliability and Maintenance Specifications

MTBF > 1,000,000 hours

Preventive Maintenance None

Data Reliability < 1 non-recoverable error in 1014 bits read

Endurance SDxT2FAH-xxx ≥ 300,000 erase/program cycles per block typical

Endurance SDxT2FCH-xxx ≥ 100,000 erase/program cycles per block typical

All values quoted are under the following conditions: a) Voltage range: 2.7 V to 3.6 V. b) Temperature range: -25° C to 85° C. c) Are independent of the TriFlash clock frequency.

Product Specifications

2.5. Physical Specifications

The SanDisk TriFlash is a 44- and 56-pin Thin Fine-Pitched Ball Grid Array (TFBGA). See Figure 2-1 (56-pin) and Figure 2-2 (44-pin) for the physical specifications and dimensions. See Figure 2-3 for a top view of the pin definitions.

A B

aaa

"B"

(NOTE 6)

1 2 3

4 5 6 7 8

aaa

bbb C

"A"

Dimension in mm Dimension in inch Symbol MIN NOM MAX Min NOM MAX A --- --- 1.10 --- --- 0.043 A1 0.32 0.35 0.38 0.013 0.014 0.015 A2 0.62 0.67 0.72 0.024 0.026 0.028 D 17.90 18.00 18.10 0.705 0.709 0.713 E 11.90 12.00 12.10 0.469 0.472 0.476 D1 --- 7.00 --- --- 0.276 -- D2 --- 11.00 --- --- 0.433 -- D3 --- 13.00 --- --- 0.512 -- E1 --- 7.00 --- --- 0.276 -- e --- 1.00 --- --- 0.039 -- b 0.40 0.45 0.50 0.016 0.018 0.020 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.15 0.006 eee 0.25 0.010 fff 0.10 0.004 MD/ME 12/11 12/11

Figure 2-1. TriFlash Physical Specifications—18 X 12mm Package

ABCDEFGH

ddd C

D1D3D2

(NOTE 3)

DETAIL: B

C A B

Oeee M

O fff M

Non-functional

balls (12 places)

Cavity

Solder Ball

Seating Plane

(NOTE 2)

DETAIL: A

NOTE:

1. Controlling Dimension: Millimeter.

2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.

3. Dimensions b is measured at the maximum solder ball diameter, parallel to Primary Datum C.

4. There shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge.

5. Reference document: JEDEC MO-205.

6. The pattern of Pin 1 Fiducial is for reference only.

7. All numbers are in mm.

8. All numbers are typical unless otherwise stated.

2-3

Product Specifications

H G F E D C B A

"A"

"B"

12345678

aaa

bbb C

aaa

ddd C

Cavity

Solder Ball

Seating Plane

(NOTE 2)

DETAIL: A

C A B

Oeee M O fff M

(NOTE 6)

(NOTE 3)

DETAIL: B

Dimension in mm Dimension in inch Symbol MIN NOM MAX Min NOM MAX A --- --- 1.10 --- --- 0.043 A1 0.32 0.35 0.38 0.013 0.014 0.015 A2 0.62 0.67 0.72 0.024 0.026 0.028 D 11.90 12.00 12.10 0.469 0.472 0.476 E 9.90 10.00 10.10 0.390 0.394 0.398 D1 --- 7.00 --- --- 0.276 -- E1 --- 7.00 --- --- 0.276 -- e --- 1.00 --- --- 0.039 -- b 0.40 0.45 0.50 0.016 0.018 0.020 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.15 0.006 eee 0.25 0.010 fff 0.10 0.004 MD/ME 8/8 8/8

Figure 2-2. TriFlash Physical Specifications—12 X 10mm Package

NOTE:

1. Controlling Dimension: Millimeter.

2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.

3. Dimensions b is measured at the maximum solder ball diameter, parallel to Primary Datum C.

4. There shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge.

5. Reference document: JEDEC MO-205.

6. The pattern of Pin 1 Fiducial is for reference only.

Product Specifications

GND

RSTB

GND

VDD

DAT2

VDD

CSB_DAT3

WPSB

CMD

SEL_B

DAT1

SEL_A

GND

DAT0

RDY/BSY

VDD

CLK

VDD

GND

VDD

GND

NOTE: DU=Don't Use.

Pin A1 ID

Figure 2-3. TriFlash Pinout (Top View)

2-5

Product Specifications

This page intentionally left blank.

3. TriFlash Interface Description

3.1. General Description of Pins and Registers

The TriFlash is a TFBGA package with 44 core balls (see Figure 2-3). The host is connected to the TriFlash using the 11 interface connections shown on following 2 tables, plus power and ground balls.

3.1.1. Pin Assignments in SD Bus Mode

Table 3-1. SD Bus Mode Pad Definition

Pin # Name Type1 Function Comment

H6, F1, C1, A2, A6 VDD S Supply Voltage

H7, H2, D1, B1, A7 VSS S Supply Voltage Ground

G2 DAT0 I/O Data Line [Bit 0]

G3 DAT12 I/O Data Line [Bit 1]

G6 DAT2 I/O Data Line [Bit 2]

G5 DAT3 I/O3 Data Line [Bit 3]

G1 CLK I Clock

G4 CMD I/O Command/Response

B5 WPB I Write Protect (Active Low)

G7 RSTB I Reset (Active Low)

B2 RDY/BSY O Ready/Busy Interrupt

B3 SEL_A I Defines I/F Pull up to VDD

B4 SEL_B I Defines I/F Pull up to VDD

S=power supply; I=input; O=output using push-pull drivers.

The extended DAT lines (DAT1-DAT3) are inputs on power up. They start to operate as DAT lines after the

SET_BUS_WIDTH command.

After power up, this line is input with 50KOhm pull-up (can be used for device detection or SPI mode selection). The pull-up

should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.

3-1

TriFlash Interface Description

3.1.2. Pin Assignments in SPI Mode

Table 3-2. SPI Bus Mode Pad Definition

H6, F1, C1, A2, A6 VDD S Supply Voltage

H7, H2, D1, B1, A7 VSS S Supply Voltage Ground

G2 DataOut I/O Device to Host Data and Status

G3 DAT1 I/O Unused Pull up to VDD

G6 DAT2 I/O Unused Pull up to VDD

G5 CS I Chip Select (Active low)

G1 CLK I Clock

G4 DataIn I Host to Device Commands and Data

B5 WPB I Write Protect (Active low)

G7 RSTB I Reset (Active low)

B2 RDY/BSY O Ready/Busy Interrupt

B3 SEL_A I Defines I/F Pull up to VDD

B4 SEL_B I Defines I/F Pull up to VDD

3.1.3. Registers

Pin # Name Type

Function Comment

Each device has a set of information registers. A detailed description is given in Section 3.5.

Table 3-3. TriFlash Registers

Name Width Description

CID 128 Card identification number: individual card number for identification.

RCA5 16 Relative card address: local system address of a device, dynamically

suggested by the device and approved by the host during initialization.

CSD 128 Card specific data: information about the device operation conditions.

SCR 64 SD Configuration Register: information about the TriFlash’s special

features capabilities.

OCR 32 Operation Condition Register.

The host may reset the devices by switching the power supply off and on again, or toggling the Reset pin. The device has its own power-on detection circuitry, which puts the device into an idle state after the power-on. The device can also be reset by sending the GO_IDLE (CMD0) command.

S=power supply; I=input; O=output using push-pull drivers.

The RCA register is not used (not available) in SPI Mode.

TriFlash Interface Description

DAT2 CD/DAT3 CMD RDY/BSY VDD CLK RSTB WPB DAT0 DAT1

Interface Driver

OCR[31:0] CID[127:0] RCA[15:0] DSR[15:0] CSD[127:0]

Card Interface

Controller

reset

SCR[63:0]

Memory Core Interface reset

Memory Core

Figure 3-1. TriFlash Architecture

3.2. SD Bus Topology

The SD bus has six communication lines and three supply lines:

• CMD—Command is a bi-directional signal. (Host and device drivers are operating in push pull mode.)

• DAT0-3—Data lines are bi-directional signals. (Host and device drivers are operating in push pull

mode.)

• CLK—Clock is a host to devices signal. (CLK operates in push pull mode.)

• VDD—VDD is the power supply line for all devices.

• VSS—VSS are ground lines.

Power Connection

3-3

TriFlash Interface Description

Figure 3-2 shows the bus topology of several devices with one host in SD Bus mode.

HOST

CLK

Vdd Vss

D0-3(A), CMD(A)

D0-3(B), CMD(B)

D0-3(C)

CMD(C)

D0-D3, CMD

D0, CS, CMD

Figure 3-2. TriFlash System Bus Topology

CLK

Vdd

Vss

CLK

Vdd

Vss

CLK

Vdd

Vss

TriFlash (A)

SD Memory

Card (B)

MultiMediaCard

(C)

D1&D2 Not

Connected

During the initialization process, commands are sent to each device individually, allowing the application to detect the devices and assign logical addresses to the physical slots. Data is always sent to each device individually. However, to simplify the handling of the card stack, after initialization, all commands may be sent concurrently to all devices. Addressing information is provided in the command packet.

The SD Bus allows dynamic configuration of the number of data lines. After power-up, by default, the TriFlash will use only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines). This feature allows an easy trade off between hardware cost and system performance.

TriFlash Interface Description

CLK

TriFlash

Host

DAT

C1C2C

CMD DAT 0-3

Figure 3-3. SD Bus Circuitry Diagram

and R

DAT

are pull-up resistors protecting the CMD and the DAT line against bus floating when all device

CMD

drivers are in a hi-impedance mode. Refer to Table 3-5 for the component values and conditions. C1, C2 and C3 are the equivalent load capacitance (CL) of each line in the bus.

3.3. SPI Bus Topology

The TriFlash SPI interface is compatible with SPI hosts available on the market. As with any other SPI device the TriFlash SPI channel consists of the following 4 signals:

• CS—Host to device Chip Select signal.

• CLK—Host to device clock signal

• DataIn—Host to device data signal.

• DataOut—Device to host data signal.

Another SPI common characteristic, which is implemented in the TriFlash as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal.

The SPI standard defines the physical link only and not the complete data transfer protocol. In SPI Bus mode, the TriFlash uses a subset of the SD protocol and command set.

The TriFlash identification and addressing algorithms are replaced by a hardware Chip Select (CS) signal. A device (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 3-4).

The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception is device programming time. At this time the host can de-assert the CS signal without affecting the programming process.

The bi-directional CMD and DAT lines are replaced by uni-directional DataIn and DataOut signals. This eliminates the ability of executing commands while data is being read or written. An exception is the multi read/write operations. The Stop Transmission command can be sent during data read. In the multi block write operation a Stop Transmission token is sent as the first byte of the data block.

3-5

TriFlash Interface Description

Power Supply

SPI Bus (CLK, DataIN, DataOut)

TriFlash

Card

Figure 3-4. SPI Bus System

SPI

Card

SPI Bus Master

CS CS

3.4. Electrical Interface

The following sections provide valuable information on TriFlash’s electrical interface.

3.4.1. Power-up

The power up of the bus is handled locally in each TriFlash and in the bus master.

TriFlash Interface Description

Logic working level

Supply voltage

Supply ramp u p time

Bus mas ter sup ply vol tage

ACMD

VDD max

Valid voltage range for commands CMD0, 15, 55 and ACMD41.

Valid v oltage

range for all other com-

mands and memory access.

Power up time

Initialization del ay: The maximum of

CMD2

1 msec, 7 4 clock cycles and suppl y ramp up time.

Initialization sequence

ACMD

VDD min

time

Time out value for initialization process = 100 msec.

Optional repetitions of ACMD41 until no cards are responding with busy bit set.

Figure 3-5. Power-up Diagram

After power up the TriFlash enters the idle state. During this state the TriFlash ignores all bus transactions until ACMD41 is received (ACMD command type shall always precede with CMD55).

ACMD41 is a special synchronization command used to negotiate the operation voltage range and to poll the devices until they are out of their power-up sequence. Besides the operation voltage profile of the devices, the response to ACMD41 contains a busy flag, indicating that the device is still working on its power-up procedure and is not ready for identification. This bit informs the host that the device is not ready. The host has to wait (and continue to poll the devices, each one on his turn) until this bit is cleared. The maximum period of power up procedure of single device shall not exceed 1 second.

Getting individual devices, as well as the whole TriFlash system, out of idle state is up to the responsibility of the bus master. Since the power up time and the supply ramp up time depend on application parameters such as the maximum number of TriFlash devices, the bus length and the power supply unit, the host must ensure that the power is built up to the operating level (the same level which will be specified in ACMD41) before ACMD41 is transmitted.

After power up, the host starts the clock and sends the initialising sequence on the CMD line. This sequence is a contiguous stream of logical ‘1’s. The sequence length is the maximum of 1msec, 74 clocks or the supply-ramp-uptime. The additional 10 clocks (over the 64 clocks after what the device should be ready for communication) are provided to eliminate power-up synchronization problems.

Every bus master shall have the capability to implement ACMD41 and CMD1. CMD1 will be used to ask the TriFlash to send their Operation Conditions. In any case the ACMD41 or the CMD1 shall be send separately to each device accessing it through its own CMD line.

3-7

TriFlash Interface Description

3.4.2. Bus Operating Conditions

SPI Mode bus operating conditions are identical to SD mode bus operating conditions. The CS (chip select) signal timing is identical to the input signal timing (see Figure 3-7).

Table 3-4. Power Supply Voltage

General

Parameter Symbol Min. Max. Unit Remark

Peak voltage on all lines -0.3 VDD+0.3 V

All Inputs

Input Leakage Current -10 10

µA

All Outputs

Output Leakage Current -10 10

µA

Power Supply Voltage

Parameter Symbol Min. Max. Unit Remark

Supply Voltage VDD 2.0 3.6 V CMD0, 15, 55, ACMD41

commands

Supply Voltage 2.7 3.6 V Except CMD0, 15, 55,

ACMD41 commands

Supply voltage differentials (V

, V

) -0.3 0.3 V

SS1

SS2

Power up Time 250 mS From 0V to VDD Min.

Bus Signal Line Load

The total capacitance CL of the CLK line of the bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each device connected to this line:

CL = CHOST + CBUS + N∗CCARD

where N is the number of connected devices. Requiring the sum of the host and bus capacitances not to exceed 30 pF for up to 10 devices, and 40 pF for up to 30 devices, the values in Table 3-5 must not be exceeded.

Table 3-5. Signal Line’s Load

Parameter Symbol Min. Max. Unit Remark

Pull-up resistance

CMD

DAT

Bus signal line capacitance CL 250 pF fPP ≤ 5 MHz,

Bus signal line capacitance CL 100 pF fPP ≤ 25 MHz,

Single card capacitance C

10 pF

CARD

Maximum signal line inductance 16 nH fPP ≤ 25 MHz

Pull-up resistance inside device (pin 1) R

10 90

DAT3

10 100

kΩ

To prevent bus floating

21 devices

7 devices

May be used for card detection

TriFlash Interface Description

3.4.3. Bus Signal Levels

As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.

Figure 3-6. Bus Signal Levels

To meet the requirements of the JEDEC specification JESD8-1A, the device input and output voltages shall be within the specified ranges listed in Table 3-6 for any VDD of the allowed voltage range.

Table 3-6. Input and Output Voltages

Parameter Symbol Min. Max. Unit Conditions

Output HIGH voltage VOH

0.75∗VDD

Output LOW voltage VOL

Input HIGH voltage VIH

0.625∗VDD

Input LOW voltage VIL VSS-0.3

0.125∗VDD

VDD + 0.3 V

0.25∗VDD

IOH=-100 µA

(min.)

IOL=100 µA

(min.)

3-9

TriFlash Interface Description

3.4.4. Bus Timing

0.7

0.2

Clock

Input

THL

TLH

ISU

Output

O DLY (max)

O DLY

(min)

Shaded areas are not valid.

Figure 3-7. Timing Diagram Data Input/Output Referenced to Clock

TriFlash Interface Description

Table 3-7. Bus Timing

Parameter Symbol Min. Max. Unit Remark

Clock CLK–All values are referred to min. (VIH) and max. (VIL)6

Clock Frequency Data Transfer Mode fPP 0 25 MHz

Clock Frequency Identification Mode (The low frequency is required for MultiMediaCard compatibility)

fOD 0

(1)

100KHz

400 kHz

Clock Low Time tWL 10 ns

Clock High Time tWH 10 ns

Clock Rise Time t

Clock Fall Time t

10 ns

TLH

10 ns

THL

Clock Low Time tWL 50 ns

Clock High Time tWH 50 ns

Clock Rise Time t

Clock Fall Time t

50 ns

TLH

50 ns

THL

Inputs CMD, DAT (referenced to CLK)

Input set-up time t

5 ns

ISU

Input hold time tIH 5 ns

Outputs CMD, DAT (referenced to CLK)

Output delay time during Data Transfer Mode t

Output delay time during Identification Mode t

0 14 ns

ODLY

0 50 ns

ODLY

≤ 100 pF

(7 cards)

≤ 250 pF

(21 cards)

≤ 100 pF

(7 cards)

≤ 100 pF

(7 cards)

≤ 100 pF

(10 cards)

≤ 100 pF

(7 cards)

≤ 250 pF

(21 cards)

≤ 250 pF

(21 cards)

≤ 250 pF

(21 cards)

≤ 250 pF

(21 cards)

≤ 25 pF

(1 cards)

≤ 25 pF

(1 card)

≤ 25 pF

(1 card)

≤ 25 pF

(1 card)

0 Hz stops the clock. The given minimum frequency range is for cases where a continuous clock is required.

3-11

TriFlash Interface Description

3.4.5. TriFlash-Specific Functions

The following sections list the TriFlash-specific functions.

3.4.5.1. Ready/Busy Function [Output]

The RDY/BSY pin indicates ”0” if the TriFlash is in “Busy” condition. Busy condition is a period where the Data paths of the TriFlash are not ready to get new data. The Busy condition, as defined in the SD Physical Specification, may occur after or within the block transfer of any write or erase operations. After a host command is sent, the host shall expect to get a Busy indication in any case that response of type R1b is expected. The RDY/BSY_B indication is basically the same as the Busy indication that is indicated by DAT0 (as given in the SD/MMC Specs).

3.4.5.2. Write Protect Function [Input + Pullup]

This line shall be set to “0” (or maximum 10KOhm pull down resistor) in order to eliminate any write operations to the TriFlash memory. An attempt to write to the TriFlash in that condition will set the WP_VIOLATION status bit (bit [26] in the Card Status).

3.4.5.3. Reset Function [Input + Pullup]

If input is set to “0” (or maximum 10KOhm pull down resistor) it will force a Hardware RESET to the TriFlash.

3.5. TriFlash Registers

There is a set of seven registers within the device interface. The OCR, CID, CSD and SCR registers carry the device configuration information. The RCA register holds the device relative communication address for the current session. The card status and SD status registers hold the communication protocol related status of the device.

3.5.1. Operating Conditions Register (OCR)

The 32-bit operation conditions register stores the VDD voltage profile of the device. The TriFlash is capable of executing the voltage recognition procedure (CMD1) with any standard TriFlash host using operating voltages form 2 to 3.6 Volts.

Accessing the data in the memory array, however, requires 2.7 to 3.6 Volts. The OCR shows the voltage range in which the device data can be accessed. The structure of the OCR register is described in Table 3-8.

TriFlash Interface Description

Table 3-8. OCR Register Definition

OCR Bit VDD Voltage Window

0-3 Reserved

4 1.6-1.7

5 1.7-1.8

6 1.8-1.9

7 1.9-2.0

8 2.0-2.1

9 2.1-2.2

10 2.2-2.3

11 2.3-2.4

12 2.4-2.5

13 2.5-2.6

14 2.6-2.7

15 2.7-2.8

16 2.8-2.9

17 2.9-3.0

18 3.0-3.1

19 3.1-3.2

20 3.2-3.3

21 3.3-3.4

22 3.4-3.5

23 3.5-3.6

24-30 Reserved

31 Card power up status bit (busy)

The level coding of the OCR register is as follows:

• Restricted voltage windows=LOW

• Card busy=LOW (bit 31)

The least significant 31 bits are constant and will be set as shown in Figure 3-8. If set, bit 32, the busy bit, informs the host that the device power up procedure is finished.

3-13

TriFlash Interface Description

24 16 8 7 4 3 0

00h FFh 80h 00 00

Reserve Operating

Voltage Range

2.7 to 3.6 volt Reserved Busy Bit

Figure 3-8. OCR Structure

3.5.2. Card Identification (CID) Register

The CID register is 16 bytes long and contains a unique card identification number as shown in the table below. It is programmed during device manufacturing and cannot be changed by TriFlash hosts. Note that the CID register in the TriFlash with the SD interface has a different structure than the CID register in the MultiMediaCard.

Table 3-9. CID Fields

Name Field Width (bits) CD-Slice CID Value

Manufacture ID MID 8 127:120 0x03

OEM/Application ID OID 16 119:104 SD ASCII Code 0x53, 0x44

Product Name PNM 40 103:64 ST128, ST064, ST032, ST016

Product Version7 PRV 8 63:56 Product Revision (30)

Product Serial number PSN 32 55:24 Product serial number

Reserved 4 23:20

Manufacture date MDT 12 19:8 Manufacture date

CRC7 Checksum8 CRC 7 7:1 CRC7

Not used always 1 1 0:0

3.5.3. CSD Register

The Card Specific Data (CSD) register contains configuration information required in order to access the device data.

The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an “n.m” revision

number. The “n” is the most significant nibble and the “m” is the least significant nibble. Example: The PRV binary value filed for product revision “6.2” will be: 0110 0010.

The CRC Checksum is computed by the following formula: CRC Calculation: G(x)=x7+3+1 M(x)=(MID-MSB)*x119+...+(CIN-LSB)*x0 CRC[6...0]=Remainder[(M(x)*x7)/G(x)]

TriFlash Interface Description

In Table 3-10, the cell type column defines the CSD field as Read only (R), One Time Programmable (R/W) or erasable (R/W/E). For each field, the value in “real world” units and coded according to the CSD structure. The

Model dependent column marks (with a check mark—√) the CSD fields, which are model dependent. Note that the

CSD register in the TriFlash with the SD interface has a different structure than the CSD in the MultiMediaCard.

Table 3-10. CSD Register

Name Field Width Cell Type CSD-Slice CSD Value CSD Code

CSD structure CSD_STRUCTURE 2 R [127:126] 1.0 00b

Reserved - 6 R [125:120] - 000000b

data read access-time-1 TAAC 8 R [119:112] 1.5mS 00100110b

data read access-time-2 in CLK cycles (NSAC*100)

max. data transfer rate TRAN_SPEED 8 R [103:96] 25MHz 00110010b

card command classes CCC 12 R [95:84] All (include WP,

max. read data block length READ_BL_LEN 4 R [83:80] 512byte 1001b

partial blocks for read allowed READ_BL_PARTIAL 1 R [79:79] Yes 1b

write block misalignment WRITE_BLK_MISALIGN 1 R [78:78] No 0b

read block misalignment READ_BLK_MISALIGN 1 R [77:77] No 0b

DSR implemented DSR_IMP 1 R [76:76] No 0b

Reserved - 2 R [75:74] - 00b

device size C_SIZE 12 R [73:62] ST064=3919

max. read current @VDD min VDD_R_CURR_MIN 3 R [61:59] 25mA 100b

max. read current @VDD max VDD_R_CURR_MAX 3 R [58:56] 25mA 011b

max. write current @VDD min VDD_W_CURR_MIN 3 R [55:53] 25mA 100b

max. write current @VDD max VDD_W_CURR_MAX 3 R [52:50] 35mA 100b

device size multiplier C_SIZE_MULT 3 R [49:47] ST128=3

NSAC 8 R [111:104] 0 00000000b

1F5h

Lock/unlock)

F4Fh ST032=1959 ST016=979

ST064=3 ST032=3 ST016=3

7A7h

3D3h

011b

erase single block enable ERASE_BLK_EN 1 R [46:46] Yes 1b

erase sector size SECTOR_SIZE 7 R [45:39] 32 blocks 0011111b

write protect group size WP_GRP_SIZE 7 R [38:32] 128 sectors 1111111b

write protect group enable WP_GRP_ENABLE 1 R [31:31] Yes 1b

Reserved for MultiMediaCard compatibility 2 R [30:29] - 00b

write speed factor R2W_FACTOR 3 R [28:26] X16 100b

max. write data block length WRITE_BL_LEN 4 R [25:22] 512byte 1001b

partial blocks for write allowed WRITE_BL_PARTIAL 1 R [21:21] No 0

Reserved - 5 R [20:16] - 00000b

3-15

TriFlash Interface Description

Name Field Width Cell Type CSD-Slice CSD Value CSD Code

File format group FILE_FORMAT_GRP 1 R/W(1) [15:15] 0 0b

copy flag (OTP) COPY 1 R/W(1) [14:14] Not Original 1b

permanent write protection PERM_WRITE_PROTECT 1 R/W(1) [13:13] Not Protected 0b

temporary write protection TMP_WRITE_PROTECT 1 R/W [12:12] Not Protected 0b

File format FILE_FORMAT 2 R/W(1) [11:10] HD w/partition 00b

Reserved 2 R/W [9:8] - 00b

CRC CRC 7 R/W [7:1] - CRC7

not used, always’1’ - 1 - [0:0] - 1b

The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first.

CSD_STRUCTURE—describes the version of the CSD structure.

Table 3-11. CSD Register Structure

CSD_STRUCTURE CSD Structure Version Valid for SD Physical Specification Version

0 CSD version No. 1.0 Version 1.0-1.01

1-3 Reserved

TAAC—Defines the asynchronous part (relative to the TriFlash clock (CLK)) of the read access time.

Table 3-12. TAAC Access Time Definition

TAAC Bit Position Code

2:0 time unit:

0=1ns, 1=10ns, 2=100ns, 3=1µms, 4=10µms, 5=100µms, 6=1ms, 7=10ms

6:3 time value:

0=Reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0

7 Reserved

NSAC—Defines the worst case for the clock dependent factor of the data access time. The unit for NSAC is 100 clock cycles. Therefore, the maximal value for the clock dependent part of the read access time is 25.5k clock cycles.

The total read access time N

as expressed in Table 4-18 is the sum of TAAC and NSAC. It has to be computed by

the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first data bit of a data block from the end bit on the read commands.

TRAN_SPEED—Table 3-13 defines the maximum data transfer rate TRAN_SPEED.

TriFlash Interface Description

Table 3-13. Maximum Data Transfer Rate Definition

TRAN_SPEED Bit Code

2:0 transfer rate unit:

0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s, 3=100Mbit/s, 4... 7=Reserved

6:3 time value:

0=Reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0

7 Reserved

CCC—The TriFlash command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this device. A value of ‘1’ in a CCC bit means that the corresponding command class is supported. Refer to Table 3-14 for command class definitions.

Table 3-14. Supported Card Command Classes

CCC Bit Supported Card Command Class

0 class 0

1 class 1

......

11 class 11

READ_BL_LEN—The maximum read data block length is computed as 2

READ_BL_LEN

. The maximum block length might therefore be in the range 512...2048 bytes. Note that in the TriFlash, the WRITE_BL_LEN is always equal to READ_BL_LEN.

Table 3-15. Data Block Length

READ_BL_LEN Block Length

0-8 Reserved

9 29 = 512 Bytes

......

11 211 = 2048 Bytes

12-15 Reserved

READ_BL_PARTIAL— READ_BL_PARTIAL is always set to 1 in the TriFlash. Partial Block Read is always allowed in the TriFlash. It means that smaller blocks can be used as well. The minimum block size is one byte.

READ_BL_PARTIAL=0 means that only the READ_BL_LEN block size can be used for block oriented data transfers.

READ_BL_PARTIAL=1 means that smaller blocks can be used as well. The minimum block size will be equal to minimum addressable unit (one byte).

WRITE_BLK_MISALIGN—Defines if the data block to be written by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in WRITE_BL_LEN.

WRITE_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.

WRITE_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.

3-17

TriFlash Interface Description

READ_BLK_MISALIGN—Defines if the data block to be read by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in READ_BL_LEN.

READ_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.

READ_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.

DSR_IMP—Defines if the configurable driver stage is integrated on the device. If set, a driver stage register (DSR) must be implemented also.

Table 3-16. DSR Implementation Code Table

DSR_IMP DSR Type

0 No DSR implemented

1 DSR implemented

C_SIZE (Device Size)—This parameter is used to compute the device capacity (does not include security protected area). The memory capacity of the device is computed from the entries C_SIZE, C_SIZE_MULT and READ_BL_LEN as follows:

memory capacity = BLOCKNR * BLOCK_LEN

Where:

BLOCKNR = (C_SIZE+1) * MULT

MULT = 2

BLOCK_LEN = 2

C_SIZE_MULT+2

READ_BL_LEN

(C_SIZE_MULT < 8)

(READ_BL_LEN < 12)

Therefore, the maximum capacity that can be coded is 4096*512*2048 = 4 GBytes. Example: A four MByte device with BLOCK_LEN = 512 can be coded with C_SIZE_MULT = 0 and C_SIZE = 2047.

VDD_R_CURR_MIN, VDD_W_CURR_MIN—The maximum values for read and write currents at the minimal VDD power supply are coded as follows:

Table 3-17. V

VDD_R_CURR_MIN

VDD_W_CURR_MIN

2:0 0=0.5mA; 1=1mA; 2=5mA; 3=10mA; 4=25mA;

Minimum Current Consumption

Code For Current Consumption @ VDD

5=35mA; 6=60mA; 7=100mA

VDD_R_CURR_MAX, VDD_W_CURR_MAX—The maximum values for read and write currents at the maximum VDD power supply are coded as follows:

Table 3-18. V

VDD_R_CURR_MAX

VDD_W_CURR_MAX

2:0 0=1mA; 1=5mA; 2=10mA; 3=25mA; 4=35mA;

Maximum Current Consumption

Code For Current Consumption @ VDD

5=45mA; 6=80mA; 7=200mA

C_SIZE_MULT (Device Size Multiplier)—This parameter is used for coding a factor MULT for computing the total device size (see ‘C_SIZE’). The factor MULT is defined as 2

C_SIZE_MULT+2

TriFlash Interface Description

Table 3-19. Multiply Factor For The Device Size

C_SIZE_MULT MULT

0 22 = 4

1 23 = 8

2 24 = 16

3 25 = 32

4 26 = 64

5 27 = 128

6 28 = 256

7 29 = 512

ERASE_BLK_EN—defines whether erase of one write block (see WRITE_BL_LEN) is allowed (other than SECTOR_SIZE given below). If ERASE_BLK_EN is 0, the host can erase a unit of SECTOR_SIZE. If ERASE_BLK_EN is 1, the host can erase either a unit of SECTOR_SIZE or a unit of WRITE_BLK_LEN.

SECTOR_SIZE—The size of an erasable sector. The contents of this register are a 7-bit binary coded value, defining the number of write blocks (see WRITE_BL_LEN). The actual size is computed by increasing this number by one. A value of zero means 1 write block, 127 means 128 blocks.

WP_GRP_SIZE—The size of a write protected group. The contents of this register are a 7-bit binary coded value, defining the number of Erase Groups (see SECTOR_SIZE). The actual size is computed by increasing this number by one. A value of zero means 1 erase group, 127 means 128 erase groups.

WP_GRP_ENABLE—A value of ‘0’ means no group write protection possible.

R2W_FACTOR—Defines the typical block program time as a multiple of the read access time. The following

table defines the field format.

Table 3-20. R2W_FACTOR

R2W_FACTOR Multiples of Read Access Time

0 1

1 2 (write half as fast as read)

2 4

3 8

4 16

5 32

6, 7 Reserved

WRITE_BL_LEN—The maximum write data block length is computed as 2

WRITE_BL_LEN

. The maximum block length might therefore be in the range from 512 up to 2048 bytes. A Write Block Length of 512 bytes is always supported. Note that in the TriFlash, the WRITE_BL_LEN is always equal to READ_BL_LEN.

3-19

TriFlash Interface Description

Table 3-21. Data Block Length

WRITE_BL_LEN Block Length

0-8 Reserved

9 29 = 512 Bytes

….

11 211 = 2048 Bytes

12-15 Reserved

WRITE_BL_PARTIAL—Defines whether partial block sizes can be used in block write commands.

WRITE_BL_PARTIAL=‘0’ means that only the WRITE_BL_LEN block size, and its partial derivatives in resolution of units of 512 blocks, can be used for block oriented data write.

WRITE_BL_PARTIAL=‘1’ means that smaller blocks can be used as well. The minimum block size is one byte.

FILE_FORMAT_GROUP—Indicates the selected group of file formats. This field is read-only for ROM. The usage of this field is shown in Table 3-22.

COPY—This bit marks the device as an original (‘0’) or non-original (‘1’). Once set to non-original, this bit cannot be reset to original. The definition of “original” and “non-original” is application dependent and changes no device characteristics.

PERM_WRITE_PROTECT—Permanently protects the whole device content, except the secured protected area, against overwriting or erasing (all write and erase commands for this device are permanently disabled). The default value is ‘0’, i.e., not permanently write protected.

TMP_WRITE_PROTECT—Temporarily protects the whole device content, except the secured protected area, from being overwritten or erased (all write and erase commands for this device are temporarily disabled). This bit can be set and reset. The default value is ‘0’ (i.e., not write protected).

FILE_FORMAT—Indicates the file format on the device. This field is read-only for ROM. The following formats are defined.

Table 3-22. FILE_FORMAT

FILE_FORMAT_GRP FILE_FORMAT Type

0 0 Hard disk-like file system with partition table

0 1 DOS FAT (floppy-like) with boot sector only (no partition table)

0 2 Universal File Format

0 3 Others/Unknown

1 0, 1, 2, 3 Reserved

CRC—The CRC field carries the checksum for the CSD contents. The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD contents.

TriFlash Interface Description

3.5.4. SCR Register

In addition to the CSD register, there is another configuration register that is named SD CARD Configuration Register (SCR). SCR provides information on the TriFlash device's special features that were configured into the given device. The size of SCR register is 64 bit. This register shall be set in the factory by the TriFlash manufacturer. The following table describes the SCR register content.

Table 3-23. SCR Fields

Description Field Width Cell Type SCR Slice SCR Value9 SCR Code

SCR Structure SCR_STRUCTURE 4 R [63:60] Ver 1.0 0

SD Memory Card—Spec. Version SD_SPEC 4 R [59:56] Ver 1.0 0

data_status_after erases DATA_STAT_AFTER_ERASE 1 R [55:55] 0 0

SD Security Support SD_SECURITY 3 R [54:52] Prot 2

(Ver 1.0)

DAT Bus widths supported SD_BUS_WIDTHS 4 R [51:48] 1, 4 0101b

Reserved - 16 R [47:32] -

Reserved for manufacturer usage - 32 R [31:0] - 0

SCR_STRUCTURE—Version number of the related SCR structure in the SD Memory Card Physical Layer Specification.

Table 3-24. SCR Register Structure Version

CSD_STRUCTURE CSD structure version Valid for SD Physical Layer

Specification Version

0 SCR version No. 1.0 Version 1.0-1.01

1-15 Reserved

SD_SPEC—Describes the SD Memory Card Physical Layer Specification version supported by this card.

Table 3-25. SD Memory Card Physical Layer Specification Version

SPEC_VERS Physical Layer Specification Version Number

0 Version 1.0-1.01

1-15 Reserved

DATA_STAT_AFTER_ERASE—Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent).

SD_SECURITY—Describes the security algorithm supported by the device.

SCR (31:0) values might be changed because of this product’s internal improvement.

3-21

TriFlash Interface Description

Table 3-26. SD Supported Security Algorithm

SD_SECURITY Supported Algorithm

0 No security

1 Security protocol 1.0

(Security Spec Ver 0.96)

2 Security protocol 2.0

(Security Spec Ver 1.0-1.01)

3 .. 7 Reserved

SD_BUS_WIDTHS—Describes all the DAT bus widths that are supported by this device.

Table 3-27. SD Supported Bus Widths

SD_BUS_WIDTHS Supported Bus Widths

Bit 0 1 bit (DAT0)

Bit 1 Reserved

Bit 2 4 bit (DAT0-3)

Bit 3 [MSB] Reserved

Since TriFlash shall support at least the two bus modes 1bit or 4bit width then any TriFlash shall set at least bits 0 and 2 (SD_BUS_WIDTH=0101).

3.5.5. Status Register

The TriFlash supports the following two card status fields:

• Card Status—This status field is compatible to the MultiMediaCard protocol.

• SD_Status—This extended status field of 512 bits supports special features unique to the SD-interface

TriFlash and future application specific features.

The TriFlash status registers’ structures are defined in the following tables. The Type and Clear-Condition fields in the table are coded as follows:

Type:

• E—Error bit.

• S—Status bit.

• R—Detected and set for the actual command response.

• X—Detected and set during command execution. The host must poll the card by sending status

command in order to read these bits.

Clear Condition:

• A—According to the card current state.

• B—Always related to the previous command. Reception of a valid command will clear it (with a delay

of one command).

• C—Clear by read.

TriFlash Interface Description

Table 3-28. Device Status

Bits Identifier Type Value Description Clear

Cond.

31 OUT_OF_RANGE E R X ’0’= no error ’1’= error The command’s argument was out of the allowed range

for this device.

30 ADDRESS_ERROR E R ’0’= no error ’1’= error A misaligned address that did not match the block length

was used in the command.

29 BLOCK_LEN_ERROR E R ’0’= no error ’1’= error The transferred block length is not allowed for this device,

or the number of transferred bytes does not match the block length.

28 ERASE_SEQ_ERROR E R ’0’= no error ’1’= error An error in the sequence of erase commands occurred. C

27 ERASE_PARAM E R X ’0’= no error ’1’= error An invalid selection of write-blocks for erase occurred. C

26 WP_VIOLATION E R X ’0’= not protected

Attempt to program a write-protected block. C

’1’= protected

25 CARD_IS_LOCKED S X ‘0’ = card unlocked

When set, signals that the device is locked by the host. A

‘1’ = card locked

24 LOCK_UNLOCK_FAIL ED E R X ‘0’ = no error

‘1’ = error

Set when a sequence or password error has been detected in lock/unlock card command or if there was an attempt to access a locked device.

23 COM_CRC_ERROR E R ’0’= no error ’1’= error The CRC check of the previous command failed. B

22 ILLEGAL_COMMAND E R ’0’= no error ’1’= error Command not legal for the card state. B

21 CARD_ECC_FAILED E R X ’0’= success ’1’= failure Card internal ECC was applied but failed to correct the

data.

20 CC_ERROR E R X ’0’= no error ’1’= error Internal card controller error. C

19 ERROR E R X ’0’= no error ’1’= error A general or an unknown error occurred during the

operation.

18 Reserved

17 Reserved

16 CID/ CSD_OVERWRITE E R X ’0’= no error ’1’= error Can be either one of the following errors:

- The CID register has been already written and cannot be overwritten.

- The read only section of the CSD does not match the device content.

- An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made.

15 WP_ERASE_SKIP S X ’0’= not protected

’1’= protected

14 CARD_ECC_DISABLED S X ’0’= enabled ’1’= disabled The command has been executed without using the

Only partial address space was erased due to existing write protected blocks.

internal ECC.

13 ERASE_RESET S R ’0’= cleared ’1’= set An erase sequence was cleared before executing

C because an out of erase sequence command was received.

3-23

TriFlash Interface Description

Bits Identifier Type Value Description Clear

Cond.

12:9 CURRENT_STATE S X 0 = idle

1 = ready 2 = ident 3 = stby 4 = tran 5 = data 6 = rcv 7 = prg 8 = dis 9-15 = Reserved

8 READY_FOR_DATA S X ’0’= not ready ’1’= ready Corresponds to buffer empty signalling on the bus. A

7:6 Reserved

5 APP_CMD S R ‘0’ = Disabled

‘1’ = Enabled

4 Reserved

3 AKE_SEQ_ERROR

(TriFlash app. spec.)

2 Reserved for application specific commands

1, 0 Reserved for manufacturer test mode

E R ‘0’ = no error ‘1’ = error Error in the sequence of authentication process. C

The state of the device when receiving the command. If the command execution causes a state change, it will be visible to the host in the response to the next command.

The four bits are interpreted as a binary coded between 0 and 15.

The device will expect ACMD, or indication that the command has been interpreted as ACMD.

number

3.5.6. SD Status

The SD Status contains status bits that are related to the SD bus proprietary features and may be used for future application specific usage. The size of the SD Status is one data block of 512 bits. The content of this register is transmitted to the host over the DAT bus along with 16 bits CRC. The SD Status is sent to the host over the DAT bus if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a device only in ‘tran_state’ (card selected). The SD Status structure is described in Table 3-29. The same abbreviations for ‘type’ and ‘clear condition’ were used as for the Card Status above.

Table 3-29. SD Status

Bits Identifier Typ

511:

DAT_BUS_WIDTH S R ‘00’=1 (default)

510

509 SECURED_MODE S R ‘0’=not in the mode

508: 496

495:

SD_CARD_TYPE S R ‘00xxh’=SD bus devices as

480

479: SIZE_OF_PROTECTED_AREA S R Size of protected area (in Shows the size of the protected area. The A

‘01’=Reserved ‘10’=4 bit width ‘11’=Reserved

‘1’=in secured mode

defined in Physical Spec. Ver. 1 (‘x’=do not care).

Value Description Clear

Cond.

Shows the currently defined data bus width that was defined by the SET_BUS_WIDTH command.

Device is in Secured Mode of operation (refer to the SD Security Specifications document).

Reserved

In the future, the 8 LSBs will be used to define different variations of an SD bus device (each bit will define different SD types). The 8 MSBs will be used to define SD Cards that do not comply with the SD as defined in the Specification Ver. 1.

TriFlash Interface Description

Bits Identifier Typ

448 units of

MULT*BLOCK_LEN refer to CSD register.

447: 312

311: 0 Reserved for Manufacturer

Value Description Clear

Cond.

actual area=(SIZE_OF_PROTECTED_ AREA) * MULT * BLOCK_LEN.

Reserved

3.5.7. RCA Register

The 16-bit relative card address register carries the device address that is published by the device during the card identification. This address is used for the addressed host-device communication after the card identification procedure.

3.5.8. TriFlash Registers in SPI Mode

In SPI mode, all the device’s registers are accessible. Their format is identical to the format in the SD mode. However, a few fields are irrelevant in SPI mode.

In SPI mode, the card status register has a different, shorter, format as well. Refer to the SPI Protocol section for more details.

3.6. Standard Data Interchange Format and Card Sizes

In general, TriFlash data is structured by means of a file system. The SD Memory Card File System Specification, published by the SD Association, describes the file format system that is implemented in the SD-interface TriFlash. Since the SD-TriFlash does not contain Security Protected Area, the formatted size is slightly larger than the SD Memory Card. Table 3-30 shows the parameter associated with different capacities.

Table 3-30. Parameters for SD-TriFlash DOS Image

Capacity Total

LBAs

128 Mb 31,360 39 31,303 31,264 16,007,168

256 Mb 62,720 45 62,669 62,624 32,063,488

512 Mb 125,440 57 125,401 125,344 64,176,128

1024 Mb 250,880 95 250,783 250,688 128,352,256

3.6.1. Data Interchange Format and Card Sizes with Optional Security

No. of Partition

Sys. Area Sectors

Total Partition

Sectors

User Data

Sectors

User Data

Bytes

In general, TriFlash data is structured by means of a file system. The SD Memory Card File System Specification, published by the SD Association, describes the file format system that is implemented in the SD-interface TriFlash. In general, each TriFlash is divided into two separate DOS-formatted partitions as follows:

3-25

TriFlash Interface Description

• The User Area—used for secured and non-secured data storage and can be accessed by the user with

regular read/write commands.

• Security Protected Area—used by copyright protection applications to save security related data and

can be accessed by the host using the secured read/write command after doing authentication as defined in the SD Security Specification. The security protected area size is defined by SanDisk as approximately one percent of the total size of the device. Tables 3-31 and 3-32 describe the user and protected areas for all SanDisk TriFlash devices.

Table 3-31. Parameters for User Area DOS Image

Capacity Total

LBAs

128 Mb 28,800 39 28,743 28,704 14,696,448

256 Mb 59,776 45 59,725 59,680 30,556,160

512 Mb 121,856 57 121,817 121,760 62,341,120

1024 Mb 246,016 95 245,919 245,824 125,861,888

No. of Partition

Sys. Area Sectors

Total Partition

Sectors

User Data

Sectors

User Data

Bytes

Table 3-32. Parameters for Protected Area DOS Image

Capacity Total

LBAs

128 Mb 352 35 351 316 161,792

256 Mb 736 37 733 696 356,352

512 Mb 1,376 37 1,373 1,336 684,032

1024 Mb 2,624 35 2,611 2,576 1,318,912

No. of Partition

Sys. Area Sectors

Total Partition

Sectors

User Data

Sectors

User Data

Bytes

4. Secure Digital (SD) Bus Protocol Description

4.1. SD Bus Protocol

Communication over the SD bus is based on command and data bit streams, which are initiated by a start bit and terminated by a stop bit. The SD bus protocol is as follows:

• Command—a command is a token that starts an operation. A command is sent from the host either to

a single device (addressed command) or to all connected devices (broadcast command). A command is transferred serially on the CMD line.

• Response—a response is a token that is sent from an addressed device, or (synchronously) from all

connected devices, to the host as an answer to a previously received command. A response is transferred serially on the CMD line.

• Data—data can be transferred from the device to the host or vice versa. Data is transferred via the data

lines.

From

host to

card(s)

CMD

DAT

Command

Operation (no response)

From

host to

card

Command Response

Operation (no data)

From

card to

host

Figure 4-1. “No Response” and “No Data” Operations

Device addressing is implemented using a session address that is assigned to the device during the initialization phase. The basic transaction on the SD bus is the command/response transaction (refer to Figure 4-1). This type of bus transaction transfers their information directly within the command or response structure. In addition, some operations have a data token.

Data transfers to/from the TriFlash are done in blocks. Data blocks are always followed by CRC bits. Single and multiple block operations are defined. Note that the Multiple Block operation mode is better for faster write operation. A multiple block transmission is terminated when a stop command follows on the CMD line. Data transfer can be configured by the host to use single or multiple data lines (as long as the device supports this feature).

4-1

Secure Digital (SD) Bus Protocol Description

From host to card(s)

CMD

DAT

Command

Block read operation

From

card to

host

Response

Data block crc Data block crcData block crc

Multiple block read operation

Data from

card to host

Stop command

stops data transfer

Command Response

Data stop operation

Figure 4-2. Multiple Block Read Operation

The block write operation uses a simple busy signaling of the write operation duration on the DAT0 data line (see Figure 4-3) regardless of the number of data lines used for transferring the data.

From host to

card

CMD

DAT

Command

From

card to

host

Response

Data block crc Data block crcBusy

Block write operation

Data

from card

to host

crc OK response and busy

from card

Command Response

Data stop operation

Stop

command

stops data

transfer

Busy

Multiple block write operation

Figure 4-3. Multiple Block Write Operation

Command tokens have coding scheme shown in Figure 4-4.

Transmitter bit:

'1'=host command

Start bit

always '0'

0 1 Content CRC 1

Command content: command and address information or parameter,

protected by 7 bit CRC checksum

End bt:

always '1'

Total length = 48 bits

Figure 4-4. Command Token Format

Each command token is preceded by a start bit (‘0’) and succeeded by an end bit (‘1’). The total length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated.

Response tokens have four coding schemes depending on their content. The token length is either 48 or 136 bits. The CRC protection algorithm for block data is a 16-bit CCITT polynomial. All used CRC types are described in Section 4.6.

Secure Digital (SD) Bus Protocol Description

Response content: mirrored command and status

information (R1 response), OCR register (R3 response)

or RCA (R6) protected by 7 bit CRC checksum

Total length = 48 bits

Total length = 136 bits

End bt:

always '1'

End bt:

always '1'

'0'=card response

Start bit

always '0'

R1, R3, R6

Transmitter bit:

0 0 Content 1

0 0 Content = CID or CSD CRC 1

Figure 4-5. Response Token Format

In the CMD line, the MSB bit is transmitted first, whereas the LSB bit is transmitted last.

When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 4-6). Start and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are calculated and checked for every DAT line individually. The CRC status response and Busy indication will be sent by the device to the host on DAT0 only (DAT1-DAT3 during that period are “do not care”).

MSB (4095)

Start bit

always '0'

LSB (0)

End bt:

always '1'

Standard busy

(only DAT0 used):

Start bit

always '0'

Wide bus (all four

data lines used):

DAT3

DAT2

DAT1

DAT0

0 CRC 1

Block length

MSN

0 4095 3 CRC 1

0 4094 2 CRC 1

0 4093 1 CRC 1

0 4092 0 CRC 1

Block length /4

LSN

Figure 4-6. Data Packet Format

End bt:

always '1'

4-3

Secure Digital (SD) Bus Protocol Description

All timing diagrams use the schematics and abbreviations listed in Table 4-1.

Table 4-1. Timing Diagram Abbreviations

H Signal is high (logical ‘1’)

L Signal is low (logical ‘0’)

X Do not care

Z High impedance state (-> = 1)

* Repeater

Busy Busy Token

Command Command token

Response Response token

Data block Data token

4.2. Protocol’s Functional Description

All communication between the host and TriFlash devices is controlled by the host (master). The host sends commands of two types: broadcast and addressed (point-to-point) commands.

• Broadcast Commands—Broadcast commands are intended for all TriFlash devices and SD cards.

Some of these commands require a response.

• Addressed (Point-to-Point) Commands—The addressed commands are sent to the addressed

TriFlash and cause a response to be sent from this device.

A general overview of the command flow is shown in Figure 4-7 for the Card Identification Mode and in Figure 4-8 for the Data Transfer Mode. The commands are listed in the command tables (Table 4-4 through Table 4-11). The dependencies between the current SD bus state, received command and following state are listed in Table 4-2. In the following sections, the different device operation modes will be described first. Thereafter, the restrictions for controlling the clock signal are defined. All SD bus commands together with the corresponding responses, state transitions, error conditions and timings are presented in the following sections.

Two operation modes are defined for SD bus devices:

• Card Identification Mode—The host will be in card identification mode after reset and while it is

looking for new devices on the bus. TriFlash devices will be in this mode after reset until the SEND_RCA command (CMD3) is received.

• Data Transfer Mode—TriFlash devices will enter data transfer mode once their RCA is first

published. The host will enter data transfer mode after identifying all of the devices on the bus.

Secure Digital (SD) Bus Protocol Description

Table 4-2 shows the dependencies between operation modes and card states. Each state in the SD bus state diagrams (Figure 4-7 and Figure 4-8) is associated with one operation mode.

Table 4-2. Overview of Card States versus Operation Modes

Card State Operation Mode

Inactive State Inactive

Idle State

Ready State Card Identification Mode

Identification State

Stand-by State

Transfer State

Sending-data State Data Transfer Mode

Receive-data State

Programming State

Disconnect State

4.3. Card Identification Mode

While in Card Identification Mode, the host resets all the devices that are in Card Identification Mode, validates operation voltage range, identifies devices and asks them to publish Relative Card Address (RCA). This operation is done to each device separately on its own CMD line. All the data communication in the Card Identification Mode uses only the command line (CMD).

4-5

Secure Digital (SD) Bus Protocol Description

Power on

SPI Operation

Mode

No Response (Non valid command) Must be a MultiMediaCard

Start MultiMediaCard

initialization process

starting at CMD1

Card-identification mode

Data-transfer mode

CMD0 CS Asserted "0"

Card is busy or host omitted voltage range

Card responds with new RCA

Idle State

(idle)

ACMD41

Ready State

(ready)

CMD2

Identification State (ident)

CMD3

Stand-by-State

(stby)

CMD0

Inactive State

(ina)

Cards with non-compatible voltage range

CMD3

From all states except (ina)

CMD15

From all states in data-transfer mode

Figure 4-7. SD Bus State Diagram (Card Identification Mode)

4.3.1. Reset

GO_IDLE_STATE (CMD0) is the software reset command and sets each TriFlash to Idle State regardless of the current device state. TriFlash devices in Inactive State are not affected by this command.

After power-on by the host, all TriFlash devices are in Idle State, including the devices that were in Inactive State. Note that at least 74 clock cycles are required prior to starting bus communication.

After power-on or CMD0, all TriFlash devices’ CMD lines are in input mode, waiting for the start bit of the next command. The devices are initialized with a default relative card address (RCA=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability).

Secure Digital (SD) Bus Protocol Description

4.3.2. Operating Voltage Range Validation

The SD Physical Specification standard requires that all SD Memory Cards will be able to establish communication with the host using any operating voltage between V

-min and VDD-max. As with all SD Memory Cards, TriFlash

follows the SD Physical Specification standard requiring the ability to establish communication with the host using any operating voltage between V values for

are defined in the operation condition register (OCR) and may not cover the whole range. TriFlash

VDD

hosts are expected to read the card’s OCR register and select proper

-min and VDD-max. However, during data transfer, minimum and maximum

values or reject the device.

VDD

TriFlash devices that store the CID and CSD data in the payload memory can communicate this information only under data-transfer V

conditions. This means if host and device have non-compatible V

ranges, the device will

not be able to complete the identification cycle, nor to send CSD data.

SD_SEND_OP_COND (ACMD41) is designed to provide TriFlash hosts with a mechanism to identify and reject devices that do not match the host’s desired V

range. This is accomplished by the host sending the required V

voltage window as the operand of this command. TriFlash devices that cannot perform data transfer in the specified range must discard themselves from further bus operations and go into Inactive State.

Note that ACMD41 is an

application-specific command. Therefore, APP_CMD (CMD55) will always precede ACMD41. The RCA to be used for CMD55 in idle_state will be the card’s default RCA = 0x0000.

The MultiMediaCard will not respond to ACMD41 (actually it will not respond to APP_CMD—CMD55, that precedes it). The MultiMediaCard will be initialized as per the MultiMediaCard spec, using SEND_OP_COND command (CMD1 of MultiMediaCard). The host should ignore an ILLEGAL_COMMAND status in the MultiMediaCard response to CMD3, since it is a residue of ACMD41, which is invalid in the MultiMediaCard (CMD0, 1, 2 do not clear the status register). Actually, ACMD41 and CMD1 will be used by the host to distinguish between MultiMediaCards and SD-interface TriFlash devices in a system.

By omitting the voltage range in the command, the host can query each device and determine if there are any noncompatibilities before sending out-of-range devices into the Inactive State. This query should be used if the host can select a common voltage range or wants to notify the application of non-usable devices in the stack.

The busy bit in the ACMD41 response can be used by a device to tell the host that it is still working on its powerup/reset procedure (e.g., downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat ACMD41 until the busy bit is set.

During the initialization procedure, the host is not allowed to change the OCR values. Changes in the OCR content will be ignored by the TriFlash. If there is a real change in the operating conditions, the host must reset the card stack (using CMD0) and begin the initialization procedure once more. However, for accessing the devices already in Inactive State, a hard reset must be done by switching the power supply off and on.

GO_INACTIVE_STATE (CMD15) can also be used to send an addressed TriFlash into the Inactive State. This command is used when the host explicitly wants to deactivate a device (e.g., host is changing V

into a range

which is known to be not supported by this device).

4-7

Secure Digital (SD) Bus Protocol Description

4.3.3. Device Identification Process

The host starts the device identification process with the identification clock rate fOD (refer to Table 3-7). In TriFlash, the CMD line output drives are push-pull drivers.

After the bus is activated, the host will request the devices to send their valid operation conditions (ACMD41 preceding with APP_CMD—CMD55 with RCA=0x0000). The response to ACMD41 is the operation condition register of the device. The same command shall be send to all of the new devices in the system. Incompatible devices are sent into Inactive State. The host then issues the command ALL_SEND_CID (CMD2) to each device to get its unique card identification (CID) number. A device that is unidentified (i.e., which is in Ready State) sends its CID number as the response (on the CMD line). After the CID was sent by the device, it goes into Identification State. Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asking the device to publish a new relative card address (RCA), which is shorter than CID and which will be used to address the device in the future data transfer mode (typically with a higher clock rate than f

). Once the RCA is received, the device state changes to

the Stand-by State. At this point, if the host wants the device to have another RCA number, it may ask the device to publish a new number by sending another SEND_RELATIVE_ADDR command to the device. The last published RCA is the actual RCA number of the device.

The host repeats the identification process, i.e., the cycles with CMD2 and CMD3 for each device in the system.

After all the SD-interface devices are initialized, the host will initialize the MultiMediaCards that are in the system (if any), using the CMD2 and CMD3 as given in the MultiMediaCard spec. Note that in the SD system all the devices are connected separately so each MultiMediaCard will be initialized individually.

4.4. Data Transfer Mode

Until the content of all CSD registers is known by the host, the fPP clock rate must remain at fOD because some devices may have operating frequency restrictions. The host issues SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), e.g., block length, card storage capacity, maximum clock rate.

Secure Digital (SD) Bus Protocol Description

Card Identification

mode

Data-transfer

mode

"Operation

complete"

CMD3

Stand-by state

(stby)

CMD4,

9, 10

Disconnect

state (dis)

CMD15 CMD0

From all states in

data-transfer mode

CMD13, CMD55

No state transition

in data-transfer mode

CMD28,

29, 38

CMD7

"Operation

complete"

Programming

state (prg)

Sending-data

CMD12 "operation complete"

state (tran)

Figure 4-8. SD Bus State Diagram (Data Transfer Mode)

state (data)

CMD17, 18, 30, 56(r)

ACMD51

Transfer

CMD24, 25, 26,

27, 42, 56(w)

Receive-data

state (rcv)

CMD12 or

"transfer end"

CMD 16, 32...37

ACMD6, 13, 42

ACMD 22,23

CMD7 is used to select one TriFlash and place it in the Transfer State. Only one TriFlash or card can be in the Transfer State at a given time. If a previously selected TriFlash or card is in the Transfer State, its connection with the host is released and it will move back to the Stand-by State. When CMD7 is issued with the reserved relative device address “0x0000,” all devices transfer back to Stand-by State. (Note that it is the responsibility of the Host to reserve the RCA=0 for device de-selection—refer to Table 4-4, CMD7 description). This may be used before identifying new devices without resetting other already registered devices. Devices that already have an RCA do not respond to identification commands (ACMD41, CMD2, CMD3) in this state.

NOTE: The device de-selection is done if a certain device gets CMD7 with un-matched RCA. That happens

automatically if selection is done to another device and the CMD lines are common. So, in the SD bus system, it will be the responsibility of the host either:

• To work with the common CMD line (after initialization is done). In this case the device de-selection

will be done automatically (as in MultiMediaCard bus system).

• If the CMD lines are separate, to be aware of the necessity to de-select devices.

All data communication in the Data Transfer Mode is point-to point between the host and the selected TriFlash (using addressed commands). All addressed commands are acknowledged with a response on the CMD line.

4-9

Secure Digital (SD) Bus Protocol Description

The relationship between the various data transfer modes is summarized in the device state diagram Figure 4-8, and in the following paragraphs:

• All data read commands can be aborted any time by the stop command (CMD12). The data transfer

will terminate and the device will return to the Transfer State. The read commands are: block read (CMD17), multiple block read (CMD18), send write protect (CMD30), send scr (ACMD51) and general command in read mode (CMD56).

• All data write commands can be aborted any time by the stop command (CMD12). The write

commands must be stopped prior to deselecting the device by CMD7. The write commands are: block write (CMD24 and CMD25), write CID (CMD26), write CSD (CMD27), lock/unlock command (CMD42) and general command in write mode (CMD56).

• As soon as the data transfer is completed, the device will exit the data write state and move either to

the Programming State (transfer is successful) or Transfer State (transfer failed).

• If a block write operation is stopped and the block length and CRC of the last block are valid, the data

will be programmed.

• The device may provide buffering for block write. This means that the next block can be sent to the

device while the previous is being programmed. If all write buffers are full, and as long as the device is in Programming State (see SD bus state diagram Figure 4-8), the DAT0 line will be kept low (BUSY).

• There is no buffering option for write CSD, write CID, write protection and erase. This means that

while the device is busy servicing any one of these commands, no other data transfer commands will be accepted. DAT0 line will be kept low as long as the device is busy and in the Programming State. Actually if the CMD and DAT0 lines of the devices are kept separated and the host keeps the busy DAT0 line disconnected from the other DAT0 lines (of the other devices), the host may access the other devices while the device is in busy.

• Parameter set commands are not allowed while the device is programming. Parameter set commands

are: set block length (CMD16), erase block start (CMD32) and erase block end (CMD33).

• Read commands are not allowed while the device is programming.

• Moving another device from Stand-by to Transfer State (using CMD7) will not terminate erase and

programming operations. The device will switch to the Disconnect State and will release the DAT line.

• A device can be reselected while in the Disconnect State, using CMD7. In this case the device will

move to the Programming State and reactivate the busy indication.

• Resetting a device (using CMD0 or CMD15) will terminate any pending or active programming

operation. This may destroy the data contents on the device. It is the host’s responsibility to prevent this.

4.4.1. Wide Bus Selection/Deselection

Wide Bus (4 bit bus width) operation mode may be selected/deselected using ACMD6. The default bus width after power up or GO_IDLE (CMD0) is 1 bit bus width. ACMD6 command is valid in ‘tran state‘ only. That means that the bus width may be changed only after a device was selected (CMD7).

4.4.2. Data Read Format

The DAT bus line is high when no data is transmitted. A transmitted data block consists of a start bit (LOW), followed by a continuous data stream. The data stream contains the net payload data (and error correction bits if an off-device ECC is used). The data stream ends with an end bit (HIGH). The data transmission is synchronous to the clock signal.

Secure Digital (SD) Bus Protocol Description

The payload for block-oriented data transfer is preserved by a CRC checksum. The generator polynomial is a standard CCITT polynomial:

16+x12+x5

The code is a shortened BCH code with d=4 and is used for payload length of up to 2048 Bytes. Note that the CRC checksum is calculated and attached to each DAT line at the end of the block. In the case of a wide bus operation (DAT0-DAT3), the 16-bit CRC is calculated separately for each DAT line.

Block Read

A block read is a block-oriented data transfer. The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). Smaller blocks whose starting and ending address are wholly contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) starts a block read, and after a complete transfer the device goes back to Transfer State. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Blocks will be continuously transferred until a stop command is issued. The stop command has an execution delay due to the serial command transmission. The data transfer stops after the end bit of the stop command.

If the host uses partial blocks whose accumulated length is not block aligned, the device will, at the beginning of the first misaligned block, detect a block misalignment error, set the ADDRESS_ERROR error bit in the status register, abort transmission and wait (in the Data State) for a stop command.

4.4.3. Data Write Format

The data transfer format is similar to the data read format. For block-oriented write data transfer, the CRC check bits are added to each data block. The device performs a CRC check for each data line at the end of each received data block prior to a write operation. (The polynomial is the same one used for a read operation.) With this mechanism, writing of erroneously transferred data can be prevented.

Block Write

During block write (CMD24—27,42,56

(w)), one or more blocks of data are transferred from the host to the device,

with CRC appended to the end of each block by the host. The SanDisk TriFlash is able to accept a block of data defined by WRITE_BL_LEN of 512 bytes. If the CRC fails, the device shall indicate the failure on the DAT line (see below); the transferred data will be discarded and not written, and all further transmitted blocks (in multiple block write mode) will be ignored.

Multiple block write command shall be used rather than continuous single write commands to make faster write operation.

Partial block writes (blocks smaller than 512 bytes) are not allowed in the SanDisk TriFlash.

The write operation will be aborted if the host tries to write over a write-protected area. In this case, the device sets the WP_VIOLATION bit in the status register, and while ignoring all further data transfer, waits in the Receive- data-State for a stop command.

Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corresponding part of the receive buffer. If this match fails, then the device will report an error and not change any register contents.

4-11

Secure Digital (SD) Bus Protocol Description

After receiving a block of data and completing the CRC check, the device will begin writing and hold the DAT0 line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the device with a SEND_STATUS command (CMD13) at any time, and the device will respond with its status. The status bit READY_FOR_DATA indicates whether the device can accept new data or whether the write process is still in progress. The host may deselect the device by issuing CMD7 (to select a different device), which will displace the device into the Disconnect State and release the DAT line without interrupting the write operation. When reselecting the device, it will reactivate busy indication by pulling DAT to low if programming is still in progress and the write buffer is unavailable. Actually, the host may perform simultaneous write operations to several devices by using an interleaving process. The interleaving process can be done by accessing each device separately while other devices are in busy. This process can be done by proper CMD and DAT0-3 line manipulations (disconnection of busy devices).

Pre-erase Setting Prior to a Multiple Block Write Operation

Setting a number of write blocks to be pre-erased (ACMD23) will make a following Multiple Block Write operation faster compared to the same operation without preceding ACMD23. The host will use this command to define how many write blocks are going to be sent in the next write operation. If the host terminates the write operation (using stop transmission) before all the data blocks are sent to the device, the content of the remaining write blocks is undefined (can be either erased or still have the old data). If the host sends a greater number of write blocks than are defined in ACMD23, the device will erase blocks one by one (as new data is received). This number will be reset to the default (=1) value after Multiple Blocks Write operation.

It is recommended to use this command preceding CMD25, so that SanDisk’s TriFlash will be faster for Multiple Write Blocks operation. Note that the host must send ACMD23 just before the WRITE command if the host wants to use the pre-erase feature. If not, pre-erase-count might be cleared automatically when another command (ex: Security Application Commands) is executed.

Send Number of Written Blocks

Systems that use the PipeLine mechanism for data buffers management are, in some cases, unable to determine which block was the last to be well written to the flash if an error occurs in the middle of a Multiple Blocks Write operation. The device will respond to ACMD22 with the number of well-written blocks.

Erase

It is desirable to erase many write blocks simultaneously in order to enhance the data throughput. Identification of these write blocks is accomplished with the ERASE_WR_BLK_START(CMD32), ERASE_WR_BLK_END(CMD33) commands.

The host must adhere to the following command sequence: ERASE_WR_BLK_START, ERASE_WR_BLK_END and ERASE (CMD38).

If an erase (CMD38) or address setting (CMD32, 33) command is received out of sequence, the device shall set the ERASE_SEQ_ERROR bit in the status register and reset the whole sequence.

If an out of sequence command (except SEND_STATUS) is received, the device shall set the ERASE_RESET status bit in the status register, reset the erase sequence and execute the last command.

If the erase range includes write protected sectors, they shall be left intact and only the non-protected sectors shall be erased. The WP_ERASE_SKIP status bit in the status register shall be set.

The address field in the address setting commands is a write block address in byte units. The device will ignore all LSB’s below the WRITE_BLK_LEN (see CSD) size.

Secure Digital (SD) Bus Protocol Description

As described above for block write, the device will indicate that an erase is in progress by holding DAT0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the device or perform device disconnection, as described in the Block Write section, above.

The data at the device after an erase operation is either ‘0’ or ‘1’, depending on the device vendor.

The SCR register bit DATA_STAT_AFTER_ERASE (bit 55) defines whether it is ‘0’ or ‘1’.

4.4.4. Write Protect Management

Two write protect methods are supported in the TriFlash as follows:

• Device internal write protect (device’s responsibility).

• Password protection device lock operation.

4.4.4.1. Device’s Internal Write Protection (Optional)

Device data may be protected against either erase or write. The entire device may be permanently write protected by the manufacturer or content provider by setting the permanent or temporary write protect bits in the CSD.

4.4.5. Card Lock/Unlock

The Card Lock and Unlock features of the Secure Digital Card have been implemented in the TriFlash. Details on how to use this feature are given in section 4.4.5 of the SD Memory Card Physical Layer Specification, version

1.01.

4.4.6. Application Specific Commands

The SD bus is defined to be protocol forward compatible to the MultiMediaCard Standard.

The SD bus system is designed to provide a standard interface for a variety application types. In order to keep future compatibility to the MultiMediaCard standard together with new SD specific commands, the SD bus uses the Application Specific commands feature to implement its proprietary commands. Following is a description of APP_CMD and GEN_CMD as they were defined in the MultiMediaCard Specification.

Application Specific Command—APP_CMD (CMD55)

This command, when received by the device, will cause the device to interpret the following command as an application specific command (ACMD). The ACMD has the same structure as regular MultiMediaCard standard commands and it may have the same CMD number. The device will recognize it as ACMD by the fact that it appears after APP_CMD.

The only effect of the APP_CMD is that if the command index of the immediately following command has an ACMD overloading it, the non-standard version will be used. For example, a device has a definition for ACMD13 but not for ACMD7. Therefore, if Command 13 is received immediately after APP_CMD command, it would be interpreted as the non-standard ACMD13, whereas command 7, similarly received, would be interpreted as the standard CMD7. In order to use one of the manufacturer specific ACMDs the host will:

4-13

Secure Digital (SD) Bus Protocol Description

• Send APP_CMD. The response will have the APP_CMD bit (new status bit) set signaling to the host

that ACMD is now expected.

• Send the required ACMD. The response will have the APP_CMD bit set, indicating that the accepted

command was interpreted as ACMD. If a non-ACMD is sent then it will be respected by the card as normal SD command and the APP_CMD bit in the Card Status stays clear.

If an invalid command is sent (neither ACMD nor CMD) then it will be handled as a standard SD illegal command error.

From the SD bus protocol point of view the ACMD numbers will be defined by the manufacturers with some restrictions. The following ACMD numbers are reserved for the SD proprietary applications and may not be used by any TriFlash manufacturer:

ACMD6, ACMD13, ACMD17-25, ACMD38-49, ACMD51.

General Command—GEN_CMD (CMD56)

The bus transaction of the GEN_CMD is the same as the single block read or write commands (CMD24 or CMD17). The difference is that the argument denotes the direction of the data transfer (rather than the address) and the data block is not memory payload data but has a vendor specific format and meaning. The device shall be selected (‘tran_state’) before sending CMD56. The data block size is the BLOCK_LEN that was defined with CMD16. The response to CMD56 will be R1.

Currently, there are no defined commands or usage for CMD56 in SanDisk’s TriFlash, but new commands may be easily defined and tailored for OEM application specific requirements (upon request to SanDisk).

4.5. Clock Control

The SD Bus clock signal can be used by the TriFlash host to set the devices to energy saving mode or to control the data flow on the bus. The host is allowed to lower the clock frequency or shut it down.

There are a few restrictions the TriFlash host must follow:

• The bus frequency can be changed at any time (under the restrictions of maximum data transfer

frequency, defined by the TriFlash and the identification frequency).

• An exception to the above is ACMD41(SD_APP_OP_COND). After issuing command ACMD41, the

following 1 or 2 procedures shall be done by the host until the device becomes ready.

− Issue continuous clock in frequency range of 100KHz-400KHz.

− If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50ms

intervals.

Secure Digital (SD) Bus Protocol Description

1) CLK CMD

2) CLK CMD

100KHz-400KHz Clocks

1st

2nd

3rd

(ACMD41)

Polling less than 50ms interval

<50ms

1st

2nd

(ACMD41)

Figure 4-9. Host Procedures Waiting for Device to be Ready

• It is an obvious requirement that the clock must be running for the TriFlash to output data or response

tokens. After the last SD Bus transaction, the host is required to provide eight (8) clock cycles for the device to complete the operation before shutting down the clock. Following is a list of various SD Bus transactions:

− A command with no response—eight clocks after the host command end bit.

− A command with response—eight clocks after the device response end bit.

− A read data transaction—eight clocks after the end bit of the last data block.

− A write data transaction—eight clocks after the CRC status token.

• The host is allowed to shut down the clock of a “busy” device. The TriFlash will complete the

programming operation regardless of the host clock. However, the host must provide a clock edge for the device to turn off its busy signal. Without a clock edge the TriFlash (unless previously disconnected by a deselect command -CMD7) will force the DAT0 line down, permanently.

<50ms

3rd

4.6. Cyclic Redundancy Codes (CRC)

The Cyclic Redundancy Check (CRC) is intended for protecting TriFlash commands, responses and data transfer against transmission errors on the SD Bus. One CRC is generated for every command and checked for every response on the CMD line. For data blocks, CRC is generated for each DAT line per transferred block. The CRC is generated and checked as described in the following:

CRC7

The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers. The CRC7 is a 7-bit value and is computed as follows:

generator polynomial: G(x) = x

M(x) = (first bit) * x

+ (second bit) * x

CRC[6...0] = Remainder [(M(x) * x7) / G(x)]

The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).

+ x3 + 1.

n-1

+...+ (last bit) * x0

4-15

Secure Digital (SD) Bus Protocol Description

Figure 4-10. CRC7 Generator/Checker

CRC16

When one DAT line is used (as in the MultiMediaCard bus), the CRC16 is used for payload protection in block transfer mode. The CRC checksum is a 16-bit value and is computed as follows:

generator polynomial G(x) = x

M(x) = (first bit) * x

+ (second bit)* x

CRC[15...0] = Remainder [(M(x) * x

+ x12 +x5 +1

n-1

) / G(x)]

+...+ (last bit) * x0

The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes the number of bits of the data block decreased by one. For example, n = 4,095 for a block length of 512 bytes. The generator polynomial G(x) is a standard CCITT polynomial. The code has a minimal distance d = 4 and is used for a payload length of up to 2,048 bytes (n <

16,383). The same CRC16 method is used in a single DAT line mode and in wide

bus mode. In wide bus mode, the CRC16 is done on each line separately.

Figure 4-11. CRC16 Generator/Checker

Secure Digital (SD) Bus Protocol Description

4.7. Error Conditions

The following sections provide valuable information for TriFlash error conditions.

4.7.1. CRC and Illegal Command

All commands are protected by CRC bits. If the addressed TriFlash device’s CRC check fails, the device does not respond and the command is not executed. The TriFlash does not change its state, and COM_CRC_ERROR bit is set in the status register.

Similarly, if an illegal command has been received, a TriFlash shall not change its state, shall not respond and shall set the ILLEGAL_COMMAND error bit in the status register. Only the non-erroneous state branches are shown in the state diagrams (Figure 4-7 and Figure 4-8). Table 4-12 contains a complete state transition description.

There are different kinds of illegal commands:

• Commands that belong to classes not supported by the TriFlash (e.g., write commands in read-only

devices).

• Commands not allowed in the current state (e.g., CMD9 in Transfer State).

• Commands that are not defined (e.g., CMD5).

4.7.2. Read, Write and Erase Time-out Conditions

The times after which a time-out condition for Read operations occur are (device independent) either 100 times longer than the typical access times for these operations given below or 100ms. The times after which a time-out

condition for Write/Erase operations occur are (device independent) either 100 times longer than the typical program times for these operations given below or 250ms. A device shall complete the command within this time period, or give up and return an error message. If the host does not get any response with the given time-out it should assume the device is not going to respond anymore and try to recover (e.g., reset the device, power cycle, reject). The typical access and program times are defined as follows:

• Read—The read access time is defined as the sum of the two times given by the CSD parameters

TAAC and NSAC. These device parameters define the typical delay between the end bit of the read command and the start bit of the data block.

• Write—The R2W_FACTOR field in the CSD is used to calculate the typical block program time

obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g., SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands).

• Erase—The duration of an erase command will be (order of magnitude) the number of write blocks

(WRITE_BL) to be erased multiplied by the block write delay.

4.8. Commands

The following sections provide valuable information for TriFlash commands.

4-17

Secure Digital (SD) Bus Protocol Description

4.8.1. Command Types

There are four kinds of commands defined to control the TriFlash:

• Broadcast Commands (bc), no response—The broadcast feature is applicable only if all the CMD

lines are connected together in the host. If they are separated then each device will accept it separately on his turn.

• Broadcast Commands with Response (bcr)—response from all devices simultaneously. Since there

is no Open Drain mode in TriFlash, this type of command is used only if all the CMD lines are separated. The command will be accepted and responded to by every device separately.

• Addressed (point-to-point) Commands (ac)—no data transfer on DAT.

• Addressed (point-to-point) Data Transfer Commands (adtc)—data transfer on DAT.

All commands and responses are sent over the CMD line of the TriFlash. The command transmission always starts with the left bit of the bit string corresponding to the command code word.

4.8.2. Command Format

The Command length is 48 bits, 1.92 µs @ 25 MHz.

0 1 bit 5...bit 0 bit 31...bit 0 bit 6...bit 0 1

start bit host command argument CRC71 end bit

Commands and arguments are listed in Table 4-4 through Table 4-11.

7-bit CRC Calculation: G(x) = x

+ x3 + 1

M(x) = (start bit)∗x39 + (host bit)∗x38 +...+ (last bit before CRC)∗x CRC[6...0] = Remainder[(M(x)∗x

)/G(x)]

4.8.3. Command Classes

The command set of the TriFlash is divided into several classes (refer to Table 4-3). Each class supports a set of SD functions.

The supported Card Command Classes (CCC) are coded as a parameter in the card specific data (CSD) register of each device, providing the host with information on how to access the device.

7-bit Cyclic Redundancy Check.

Secure Digital (SD) Bus Protocol Description

Table 4-3. Card Command Classes (CCCs)

0 1 2 3 4 5 6 7 8 9-11

Supported

Commands

Basic

Reserved

Block

Read

CMD0 +

CMD2 +

CMD3 +

CMD4 +

CMD7 +

CMD9 +

CMD10 +

CMD12 +

CMD13 +

CMD15 +

CMD16 + + +

CMD17 +

Reserved

Block Write

Erase Write

Protection

Lock Card

Application

Specific

Reserved

CMD18 +

CMD24 +

CMD25 +

CMD27 +

CMD28 +

CMD29 +

CMD30 +

CMD32 +

CMD33 +

CMD38 +

CMD42 +

CMD55 +

CMD56 +

ACMD6 +

ACMD13 +

ACMD22 +

ACMD23 +

ACMD41 +

ACMD42 +

ACMD51 +

4-19

Secure Digital (SD) Bus Protocol Description

4.8.4. Detailed Command Description

Tables 4-4 through 4-10 define in detail the SD Bus commands.

Table 4-4. Basic Commands (Class 0 And Class 1)

Cmd

Index

CMD0 bc [31:0] Stuff Bits=‘0’ - GO_IDLE_STATE Resets all devices to Idle State.

CMD1 Reserved

CMD2 bcr [31:0] Stuff Bits=‘0’ R2 ALL_SEND_CID Asks any device to send their CID numbers on

CMD3 bcr [31:0] Stuff Bits=‘0’ R6 SEND_RELATIVE_

CMD42 Not Supported

CMD5 Reserved

CMD6 Reserved

CMD7 ac [31:16] RCA

CMD8 Reserved

CMD9 ac [31:16] RCA

CMD10 ac [31:16] RCA

CMD11 Reserved

CMD12 ac [31:0] Stuff Bits=‘0’ R1b3 STOP_

CMD13 ac [31:16] RCA

CMD14 Reserved

CMD15 ac [31:16] RCA

Type Argument Resp Abbreviation Command Description

the CMD line. (Any device that is connected to the host will respond.)

Asks the device to publish a new relative address

[15:0] Stuff Bits=‘0’

(only from the selected device)

ADDR

SELECT/DESELECT_ CARD

(RCA).

Command toggles a device between the Stand-by and Transfer states or between the Programming and Disconnect state.

In both cases the device is selected by its own relative address and deselected by any other address; address 0 deselects all. When the RCA equals 0, the host may do one of the following: —use other RCA number to perform device deselection or —resend CMD3 to change its RCA number to other then 0 and then use CMD7 with RCA=0 for device de-selection.

R2 SEND_CSD Addressed device sends its card-specific data

[15:0] Stuff Bits=‘0’

(CSD) on the CMD line.

R2 SEND_CID Addressed device sends its card identification

[15:0] Stuff Bits=‘0’

(CID) on the CMD line.

Terminates a multiple block read/write operation.

TRANSMISSION

R1 SEND_STATUS Addressed device sends its status register.

[15:0] Stuff Bits=‘0’

- GO_INACTIVE_

STATE

Sets the device to inactive state.

The DSR option (as well as the SET_DSR command) is not supported by the SanDisk TriFlash.

The device may become busy after this command. Refer to Figure 4-25 for more details.

Secure Digital (SD) Bus Protocol Description

Table 4-5. Block Read Commands (Class 2)

Cmd

Type Argument Resp Abbreviation Command Description

Index

CMD16 ac [31:0] block length R1 SET_BLOCKLEN Selects a block length (in bytes) for all following

block commands (read and write).

CMD17 adtc [31:0] data address R1 READ_SINGLE_

BLOCK

Reads a block of the size selected by the SET_BLOCKLEN command.

CMD18 adtc [31:0] data address R1 READ_MULTIPLE_BLOCK Continuously send blocks of data until interrupted

by a stop transmission command.

CMD19 –

Reserved

CMD23

Table 4-6. Block Write Commands (Class 4)

Cmd

Index

CMD24 adtc [31:0] data address R1 WRITE_BLOCK Writes a block of the size selected by the

CMD25 adtc [31:0] data address R1 WRITE_MULTIPLE_

CMD26 Not Applicable

CMD27 adtc [31:0] Stuff Bits =‘0’ R1 PROGRAM_CSD Programming of the programmable bits of the CSD.

Type Argument Resp Abbreviation Command Description

SET_BLOCKLEN command.

Continuously writes blocks of data until a

BLOCK

STOP_TRANSMISSION follows.

Table 4-7. Write Protection* (Class 6)

Cmd

Index

CMD28 ac [31:0] data address R1b SET_WRITE_PROT This command sets the write protection bit of the

CMD29 ac [31:0] data address R1b CLR_WRITE_PROT This command clears the write protection bit of

CMD30 adtc [31:0] write protect

CMD31 Reserved

The default block length is as specified in the CSD (512 bytes). A set block length of less than 512 bytes will cause a write

error. The only valid write set block length is 512 bytes. CMD16 is not mandatory if the default is accepted.

The data transferred must not cross a physical block boundary.

All data blocks are responded to with a data response token followed by a busy signal. The data transferred must not cross a

physical block boundary.

Type Argument Resp Abbreviation Command Description

addressed group. The properties of write protection are coded in the card specific data (WP_GRP_SIZE).

the addressed group.

data address

R1 SEND_WRITE_

PROT

This command asks the device to send the status of the write protection bits.

4-21

Secure Digital (SD) Bus Protocol Description

Table 4-8. Commands (Class 5)

Cmd

Type Argument Resp Abbreviation Command Description

Index

CMD32 ac [31:0] data

address

CMD33 ac [31:0] data

address

CMD34

Reserved

R1 ERASE_WR_BLK_START Sets the address of the first write block to be

erased.

R1 ERASE_WR_BLK_END Sets the address of the last write block of the

continuous range to be erased.

… CMD37

CMD38 ac [31:0] Stuff Bits =‘0’ R1b ERASE Erases all previously selected write blocks.

CMD39

Reserved … CMD41

Table 4-9. Lock Card Commands (Class 7)

Cmd

Index

CMD16 ac [31:0] block length R1 SET_BLOCKLEN Selects a block length (in bytes) for all following block

CMD42 adtc [31:0] Stuff Bits =‘0’ R1b LOCK_UNLOCK Used to set/reset the password or lock/unlock the

CMD43

….

CMD54

Type Argument Resp Abbreviation Command Description

commands (read and write).

card. The size of the data block is set by the SET_BLOCK_LEN command.

Reserved

Table 4-10. Application Specific Commands (Class 8)

CMD

INDEX

CMD55 ac [31:16] RCA [15:0]

CMD56 adtc [31:1] Stuff Bits

CMD57 ... CMD59

CMD60 -63 Reserved for Manufacturer

The default block length is as specified in the CSD (512 bytes). A set block length of less than 512 bytes will cause a write

error. The only valid write set block length is 512 bytes. CMD16 is not mandatory if the default is accepted.

RD/WR: “1” = the host gets a block of data from the device. “0” = the host sends a block of data to the device.

Type Argument Resp. Abbreviation Command Description

R1 APP_CMD Indicates to the device that the next command is

Stuff Bits =‘0’

an application specific command rather than a standard command

R1 GEN_CMD Used either to transfer a data block to the device =‘0’. [0]: RD/ WR

or to get a data block from the device for general purpose/application specific commands. The size of the data block shall be set by the SET_BLOCK_LEN command.

Reserved

Secure Digital (SD) Bus Protocol Description

Table 4-11 describes all the application specific commands supported/reserved by the SD bus. All the following ACMDs shall be preceded with APP_CMD command (CMD55)

Table 4-11. Application Specific Commands Used/Reserved by SD Bus

ACMD

Type Argument Resp. Abbreviation Command Description

INDEX

ACMD6 ac [31:2] Stuff Bits =‘0’

[1:0]bus width

R1 SET_BUS_WIDTH Defines the data bus width (’00’=1bit or ’10’=4 bits

bus) to be used for data transfer.

ACMD13 adtc [31:0] Stuff Bits =‘0’ R1 SD_STATUS Send the TriFlash status. The status fields are given

in Table 3-28.

ACMD17 Reserved

ACMD18 -- -- -- -- Reserved for SD security applications9

ACMD19 to

Reserved

ACMD21

ACMD22 adtc [31:0] Stuff Bits =‘0’ R1 SEND_NUM_WR_

BLOCKS

ACMD23 ac [31:23] Stuff Bits =‘0’

[22:0]Number of

R1 SET_WR_BLK_

ERASE_COUNT

blocks

Send the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.

Set the number of write blocks to be pre-erased before writing (to be used for faster Multiple Block WR command). “1”=default (one write block)

ACMD24 Reserved

ACMD25 -- -- -- -- Reserved for SD security applications

ACMD26 -- -- -- -- Reserved for SD security applications

ACMD38 -- -- -- -- Reserved for SD security applications

ACMD39 to

Reserved

ACMD40

ACMD41 bcr [31:0]OCR

without busy

R3 SD_APP_OP_COND Asks the accessed device to send its operating

condition register (OCR) content in the response on the CMD line.

ACMD42 ac [31:1] Stuff Bits =‘0’

[0]set_cd

R1 SET_CLR_CARD_

DETECT

Connect[1]/Disconnect[0] the 50KOhm pull-up resistor on CD/DAT3 (pin 1) of the device. The pull-up may be used for device detection.

ACMD43

-- -- -- -- Reserved for SD security applications

ACMD49

ACMD51 adtc [31:0] staff bits R1 SEND_SCR Reads the SD Configuration Register (SCR).

Refer to SD Memory Card Security Specification for detailed explanation about the SD Security Features.

The start address and block length must be set so that the data transferred does not cross a physical block boundary.

4-23

Secure Digital (SD) Bus Protocol Description

4.9. Card State Transition Table

Table 4-12 defines the TriFlash state transitions in dependency of the received command.

Table 4-12. Card State Transition Table

Current State

idle ready ident stby tran data rcv prg dis ina

Command Changes to

Class Independent

CRC error - - - - - - - - - -

command not sup ported - - - - - - - - - -

Class 0

CMD0 idle idle idle idle idle idle idle idle idle -

CMD2 - ident - - - - - - - -

CMD3 - - stby stby - - - - - -

CMD4 - - - stby - - - - - -

CMD7, device is addressed - - - tran - - - - prg -

CMD7, device is not addressed - - - stby stby stby - dis - -

CMD9 - - - stby - - - - - -

CMD10 - - - stby - - - - - -

CMD12 - - - - - tran prg - - -

CMD13 - - - stby tran data rcv prg dis -

CMD15 - - - ina ina ina ina ina ina -

Class 2

CMD16 - - - - tran - - - - -

CMD17 - - - - data - - - - -

CMD18 - - - - data - - - - -

Class 4

CMD16 See Class 2

CMD24 - - - - rcv - - - - -

CMD25 - - - - rcv - - - - -

CMD27 - - - - rcv - - - - -

Class 6

CMD28 - - - - prg - - - - -

CMD29 - - - - prg - - - - -

CMD30 - - - - data - - - - -

Secure Digital (SD) Bus Protocol Description

Current State

idle ready ident stby tran data rcv prg dis ina

Command Changes to

Class 5

CMD32 - - - - tran - - - - -

CMD33 - - - - tran - - - - -

CMD38 - - - - prg - - - - -

Class 7

CMD16 See Class 2

CMD42 This is an SDA optional command that is not currently supported by the SanDisk TriFlash.

Class 8

CMD55 idle - - stby tran data rcv prg dis -

CMD56; RD/WR = 0 - - - - rcv - - - - -

CMD56; RD/WR = 1 - - - - data - - - - -

ACMD6 - - - - tran - - - - -

ACMD13 - - - - tran - - - - -

ACMD22 - - - - tran - - - - -

ACMD23 - - - - tran - - - - -

ACMD18, 25, 26, 38, 43, 44, 45, 46, 47, 48, 49

ACMD41, device VDD range

Refer to SD Memory Card Security Specification for an explanation of the SD Security Features. The SanDisk TriFlash with security supports all the security related commands as explained in the specification.

ready - - - - - - - - -

compatible

ACMD41, device is busy idle - - - - - - - - -

ACMD41, device VDD range

ina - - - - - - - - -

not compatible

ACMD42 - - - - rcv - - - - -

ACMD51 - - - - data - - - - -

class 9-11

CMD41; CMD43...CMD54,

Reserved

CMD57-CMD59

CMD60...CMD63 Reserved for manufacturer

4-25

Secure Digital (SD) Bus Protocol Description

4.10. Responses

All responses are sent via the CMD line. The response transmission always starts with the MSB. The response length depends on the response type.

A response always starts with a start bit (always ‘0’), followed by the bit indicating the direction of transmission (card = ‘0’). A value denoted by ‘x’ in the tables below indicates a variable entry. All responses except for the type R3 (see below) are protected by a CRC. Every response is terminated by the end bit (always ‘1’).

There are four types of responses that are supported in the SanDisk TriFlash. Their formats are defined as follows:

R1 (standard response): response length 48 bit.

Bits 45:40 indicate the index of the command to which it is responding. The status of the device is coded in 32 bits. Note that when a data transfer to the device is involved, a busy signal may appear on the data line after the transmission of each block of data. The host will check for busy after the data block transmission.

Table 4-13. Response R1

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1

Value ‘0’ ‘0’ x x x ‘1’

Description Start bit Transmission bit Command index Card status CRC7 End bit

R1b is identical to R1 with an optional busy signal transmitted on the data line. The device may become busy after receiving these commands based on its state prior to the command reception. The host will check for busy at the response.

R2 (CID, CSD register): response length 136 bits.

The content of the CID register is sent as a response to CMD2 and CMD10. The content of the CSD register is sent as a response to CMD9. Only bits [127...1] of the CID and CSD are transferred, bit [0] of these registers is replaced by the end bit of the response.

Table 4-14. Response R2

Bit Position 135 134 [133:128] [127:1] 0

Width (bits) 1 1 6 127 1

Value ‘0’ ‘0’ ‘111111’ x ‘1’

Description Start bit Transmission bit Reserved CID or CSD register incl. internal CRC7 End bit

R3 (OCR register): response length 48 bits.

The contents of the OCR register are sent as a response to ACMD41.

Table 4-15. Response R3

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1

Value ‘0’ ‘0’ ‘111111’ x ‘1111111’ ‘1’

Description Start bit Transmission bit Reserved OCR register Reserved End bit

Secure Digital (SD) Bus Protocol Description

NOTE: Responses R4 and R5 are not supported.

R6 (Published RCA response): code length 48 bits. The bits 45:40 indicate the index of the command to be

responded to—in that case it will be ‘000011’ (together with bit 5 in the status bits it means = CMD3). The 16 MSB bits of the argument field are used for the published RCA number.

Table 4-16. R6 Response

Bit Position 47 46 [45:40] [39:8] Argument Field [7:1] 0

Width (bits) 1 1 6 16 16 7 1

Value ‘0’ ‘0’ x x x x ‘1’

Description Start bit Transmission bit Command

index (‘000011’)

New published RCA [31:16] of the card

4.11. Timings

All timing diagrams use the schematics and abbreviations in Table 4-17.

Table 4-17. Timing Diagram Symbols

S Start Bit (= 0)

T Transmitter Bit (Host = 1, Device = 0)

P One-cycle Pull-up (= 1)

E End Bit (=1)

Z High Impedance State (-> = 1)

D Data Bits

X Do not care Data Bits (from Device)

* Repeater

CRC Cyclic Redundancy Check Bits (7 Bits)

Device Active

Host Active

[15:0] card status bits: 23,22,19,12:0 (refer to Table 3-28)

CRC7 End bit

The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the device respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R

respectively R

CMD

DAT

Actively-driven P-bits are less sensitive to noise. All timing values are defined in Table 4-18.

4.11.1. Command and Response

Both host command and device responses are clocked out with the rising edge of the host clock.

Card identification and card operation conditions timing

The timing for CMD2 and ACMD41 is given below. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding device. The device response to the host command starts after N

clock cycles.

4-27

Secure Digital (SD) Bus Protocol Description

CMD S T content CRC E Z Z

<-----Host command---->

<-NID cycles->

P* * *

P S T content Z Z Z

<---CID or OCR--->

Figure 4-12. Identification Timing (Card Identification Mode)

Assign a device relative address

The SEND_RELATIVE_ADDR (CMD 3) for TriFlash timing is shown in Figure 4-13. Note that CMD3 command’s content, functionality and timing are different for MultiMediaCard bus. The minimum delay between the host command and device response is N

CMD S T content CRC E Z Z

<----Host command---->

clock cycles.

<-NCR cycles->

P * * *

<--------Response-------->

P S T content CRC E Z Z Z

Figure 4-13. SEND_RELATIVE_ADDR Timing

Data transfer mode

After the device published it own RCA it will switch to data transfer mode. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding device. This timing diagram is relevant for all responded host commands except and ACMD41 and CMD2.

CMD S T content CRC E Z Z

<----Host command---->

<-NCR cycles->

P * * *

<--------Response-------->

P S T content CRC E Z Z Z

Figure 4-14. Command Response Timing (Data Transfer Mode)

Last Device Response—Next Host Command Timing

After receiving the last device response, the host can start the next command transmission after at least N

clock

cycles. This timing is relevant for any host command.

CMD S T content CRC E Z

<--------Response-------->

<-NRC cycles->

* * * * * *

<----Host command---->

Z S T content CRC E

Figure 4-15. Timing Response End to Next CMD Start (Data Transfer Mode)

Last Host Command—Next Host Command Timing

After the last command has been sent, the host can continue sending the next command after at least N

clock

periods.

CMD S T content CRC E Z

<-----Host command--->

<-NCC cycles->

* * * * * *

<----Host command---->

Z S T content CRC E

Figure 4-16. Timing of Command Sequences (All Modes)

4.11.2. Data Read

NOTE: The DAT line represents the data bus (either 1 or 4 bits).

Single Block Read

The host selects one device for data read operation by CMD7, and sets the valid block length for block oriented data transfer by CMD16. The basic bus timing for a read operation is given in Figure 4-17. The sequence starts with a single block read command (CMD17) that specifies the start address in the argument field. The response is sent on the CMD line as usual.

<----Host command---->

<-NCR cycles->

<--------Response-------->

Secure Digital (SD) Bus Protocol Description

CMD S T content CRC E Z Z

DAT Z Z Z * * * * Z Z Z Z Z Z P * * * * * * * * P S D D D * * *

P * * *

<-------NAC cycles------->

P S T content CRC E

<-Read Data->

Figure 4-17. Timing of Single Block Read

Data transmission from the device starts after the access time delay N

beginning from the end bit of the read

command. After the last data bit, the CRC check bits are suffixed to allow the host to check for transmission errors.

Multiple Block Read

In multiple block read mode, the device sends a continuous flow of data blocks following the initial host read command. The data flow is terminated by a stop transmission command (CMD12). Figure 4-18 describes the timing of the data blocks and Figure 4-19 describes the response to a stop command. The data transmission stops two clock cycles after the end bit of the stop command.

<--Host command-->

CMD S T content CRC E Z Z

DAT Z Z Z * * * Z Z Z Z Z Z P * * * * * * P S content CRC E P * * * * * * P S D D D D D

<-NCR cycles->

P *

<---NAC cycles--->

<----Response---->

P S T content CRC E Z Z P P P P P P P P P P P P P

<--Read Data-->

<-NAC cycles-> <-Read Data->

Figure 4-18. Timing of Multiple Block Read Command

CMD S T content CRC E Z Z

DAT D D D * * * * * * * D D D E Z Z * * * * * * * * * * * * * * * * * *

<–Host command–>

<–NCR cycles–>

P * * *

P S T content CRC E

<–Response–>

Figure 4-19. Timing of Stop Command (CMD12, Data Transfer Mode)

4.11.3. Data Write

Single Block Write

The host selects one device for data write operation by CMD7. The host sets the valid block length for blockoriented data transfer by CMD16.

The basic bus timing for a write operation is given in Figure 4-20. The sequence starts with a single block write command (CMD24) that determines (in the argument field) the start address. It is responded by the device on the CMD line as usual. The data transfer from the host starts N

clock cycles after the device response was received.

The data is suffixed with CRC check bits to allow the device to check it for transmission errors. The device sends back the CRC check result as a CRC status token on the DAT0 line. In the case of transmission error the device sends a negative CRC status (‘101’). In the case of non-erroneous transmission the device sends a positive CRC status (‘010’) and starts the data programming procedure. When a flash programming error occurs the device will ignore all further data blocks. In this case no CRC response will be sent to the host and, therefore, there will not be CRC start bit on the bus and the three CRC status bits will read (‘111‘).

<-Host cmnd-> <-NCR->

CMD E Z Z P * P S T Content CRC E Z Z P * * * * * * * * * * * * * * * * P P P P P P P P

DAT0 Z Z DAT1-3 Z Z

* * * * * * * * * * * *

<-Card response->

<-Write data-> S content CRC EZZ S Status E S L*L E Z S content CRC EZZ X X X X X X X X X Z

Z Z Z * * * Z Z Z Z Z Z Z * * * Z Z Z Z

<-NWR->

P * P P * P

CRC status <-Busy->

Figure 4-20. Timing of the Block Write Command

4-29

Secure Digital (SD) Bus Protocol Description

NOTE: The CRC response output is always two clocks after the end of data.

If the device does not have a free data receive buffer, the device indicates this condition by pulling down the data line to LOW. The device stops pulling down the DAT0 line as soon as at least one receive buffer for the defined data transfer block length becomes free. This signaling does not give any information about the data write status, which must be polled by the host.

Multiple Block Write

In multiple block write mode, the device expects continuous flow of data blocks following the initial host write command.

As in the case of single block write, the data is suffixed with CRC check bits to allow the device to check it for transmission errors. The device sends back the CRC check result as a CRC status token on the DAT0 line. In the case of transmission error the device sends a negative CRC status (‘101’). In the case of non-erroneous transmission the device sends a positive CRC status (‘010’) and starts the data programming procedure. When a flash programming error occurs the device will ignore all further data blocks. In this case no CRC response will be sent to the host and, therefore, there will not be CRC start bit on the bus and the three CRC status bits will read (‘111‘).

The data flow is terminated by a stop transmission command (CMD12). Figure 4-21 describes the timing of the data blocks with and without device busy signal.

<-CardRsp->

CMD E Z Z P * * * * * * * * * * * * * * * P P P P P * * * * * * * * * * * * * * * P P P P P P P P P

DAT Z Z

<-NWR->

<-Write data->

S Data+CRC E Z Z S Status E Z

P * P

CRC status <-NWR->

P * P

<-Write data->

S Data+CRC EZZ

CRC status <-Busy-> <-NWR->

S Status E S L*L E Z P*P

Figure 4-21. Timing of the Multiple Block Write Command

The stop transmission command works similar as in the read mode. Figure 4-22 to Figure 4-25 describe the timing of the stop command in different device states.

<--Host Command--> <NCX Cycles>

CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content

<--------Device is programming--------->

DAT D D D D D D D D D D E Z Z S L * * * * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z

<----Device response----> <Host Cmnd>

Figure 4-22. Stop Transmission During Data Transfer from the Host

The card will treat a data block as successfully received and ready for programming only if the CRC data of the block was validated and the CRC status token sent back to the host. Figure 4-23 is an example of an interrupted (by a host stop command) attempt to transmit the CRC status block. The sequence is identical to all other stop transmission examples. The end bit of the host command is followed, on the data line, with one more data bit, end bit and two Z clock for switching the bus direction. The received data block, in this case is considered incomplete and will not be programmed.

<--Host Command--> <-Ncr Cycles-> CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content <Data block> CRC Status11 <--------Card is programming--------> DAT D D D D D Z Z S Status E Z Z S L * * * * * * ** * * * * * * * * * * * * E Z Z Z Z Z Z Z Z

<-----Card response-----> <Host Cmnd>

Figure 4-23. Stop Transmission During CRC Status Transfer from the Device

The card CRC status response was interrupted by the host.

Secure Digital (SD) Bus Protocol Description

All previous examples dealt with the scenario of the host stopping the data transmission during an active data transfer. The following two diagrams describe a scenario of receiving the stop transmission between data blocks. In the first example the device is busy programming the last block while in the second the device is idle. However, there are still unprogrammed data blocks in the input buffers. These blocks are being programmed as soon as the stop transmission command is received and the device activates the busy signal.

<--Host Command--> <Ncr Cycles> CMD S T content CRC E Z Z P * * * P S T content CRC E S T Content <----------Device is programming----------> DAT S L * * * * * * * * * * * * * * * * * * * * * * * ** ** * * * * * * * * * L E Z Z Z Z Z Z Z Z

<----Device response----> <Host Cmnd>

Figure 4-24. Stop Transmission Received After Last Data Block. Device is Busy Programming

<--Host Command--> <Ncr Cycles> CMD S T content CRC E Z Z P * * * P S T content CRC E S T Content <----------Device is programming----------> DAT Z Z Z Z Z Z Z Z Z Z Z S L * * * * * * * * * * * * * * * * * * * * * * * * L E Z Z Z Z Z Z Z Z

<----Device response----> <Host Cmnd>

Figure 4-25. Stop Transmission Received After Last Data Block. Device becomes Busy

Erase, Set and Clear Write Protect Timing

The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be erased. The erase command (CMD38), once issued, will erase all the selected write blocks. Similarly, set and clear write protect commands start a programming operation as well. The device will signal “busy” (by pulling the DAT line low) for the duration of the erase or programming operation. The bus transaction timings are the same as given for stop tran command.

Reselecting a Busy Device

When a busy device, which is currently in the dis state, is reselected it will reinstate its busy signaling on the data line. The timing diagram for this command/response/busy transaction is the same as given for stop tran command.

4.11.4. Timing Values

Table 4-18 defines all timing values.

Table 4-18. Timing Values

Min. Max. Unit

maximum value shall be calculated using the following equation: MIN [([TAAC ∗ f + NSAC ∗ 100] ∗ 100), (100ms ∗ f)].

2 64 Clock Cycles

5 5 Clock Cycles

See footnote

8 - Clock Cycles

2 - Clock Cycles

Clock Cycles

4-31

5. SPI Protocol Definition

5.1. SPI Bus Protocol

While the SD channel is based on command and data bit-streams, which are initiated by a start bit and terminated by a stop, bit, the SPI channel is byte oriented. Every command or data block is built of eight bit bytes and is byte aligned (multiples of eight clocks) to the CS signal.

Similar to the SD Bus protocol, the SPI messages are built from command, response and data-block tokens. All communication between host and devices is controlled by the host (master). The host starts every bus transaction by asserting the CS signal low.

The response behavior in SPI Bus mode differs from the SD Bus mode in the following three ways:

• The selected device always responds to the command.

• An 8- or 16-bit response structure is used.

• When the device encounters a data retrieval problem, it will respond with an error response (which

replaces the expected data block) rather than time-out as in the SD Bus mode.

In addition to the command response, every data block sent to the device during write operations will be responded with a special data response token. A data block may be as big as one device write block (WRITE_BL_LEN) and as small as a single byte.

5.1.1. Mode Selection

The TriFlash wakes up in the SD Bus mode. It will enter SPI mode if the CS signal is asserted (negative) during the reception of the reset command (CMD0). If the device recognizes that the SD Bus mode is required it will not respond to the command and remain in the SD Bus mode. If SPI mode is required, the device will switch to SPI mode and respond with the SPI mode R1 response.

The only way to return to the SD Bus mode is by power cycling the device. In SPI mode, the SD Bus protocol state machine is not observed. All the SD commands supported in SPI mode are always available.

The default command structure/protocol for SPI mode is that CRC checking is disabled. Since the device powers up in SD Bus mode, CMD0 must be followed by a valid CRC byte (even though the command is sent using the SPI structure). Once in SPI mode, CRCs are disabled by default.

CMD0 is a static command and always generates the same 7-bit CRC of 4Ah. Adding the “1,” end bit (bit 0) to the CRC creates a CRC byte of 95h. The following hexadecimal sequence can be used to send CMD0 in all situations for SPI mode, since the CRC byte (although required) is ignored once in SPI mode. The entire CMD0 sequence appears as 40 00 00 00 00 95 (hexadecimal).

The default block length is as specified in the CSD (512 bytes). A set block length of less than 512 bytes will cause a write

error. The only valid write set block length is 512 bytes. CMD16 is not mandatory if the default is accepted.

5-1

SPI Protocol Definition

5.1.2. Bus Transfer Protection

Every TriFlash token transferred on the bus is protected by CRC bits. In SPI mode, the TriFlash offers a nonprotected mode, which enables systems built with reliable data links to exclude the hardware or firmware required for implementing the CRC generation and verification functions.

In the non-protected mode the CRC bits of the command, response and data tokens are still required in the tokens however, they are defined as “do not cares” for the transmitters and ignored by the receivers.

The SPI interface is initialized in the non-protected mode. The host can turn this option on and off using CRC_ON_OFF command (CMD59).

The CRC7/CRC16 polynomials are identical to that used in SD Bus mode. Refer to this section in the SD Bus Mode Section.

5.1.3. Data Read

SPI mode supports single block and multiple block read operations (CMD17 or CMD18). Upon reception of a valid read command the device will respond with a response token followed by a data token in the length defined in a previous SET_BLOCK_LENGTH (CMD16) command (see Figure 5-1).

Data from Card to Host

Next Command

Command

DataIn

DataOut

From Ho st to Card

Command

From Card t o Host

Response

Data Block CRC

Figure 5-1. Single Block Read Operation

A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial:

16+x12+x5

+1.

The maximum block length is 512 bytes as defined by READ_BL_LEN (CSD parameter). Block lengths can be any number between 1 and READ_BL_LEN.

The start address can be any byte address in the valid address range of the device. Every block, however, must be contained in a single physical device sector.

In case of data retrieval error, the device will not transmit any data. Instead, a special data error token will be sent to the host. Figure 5-2 shows a data read operation that terminated with an error token rather than a data block.

SPI Protocol Definition

From Host to Card

DataIn

DataOut

Command

From Card to Host

Response

Data Error Token from Card to Host

Data Error

Next Command

Command

Figure 5-2. Read Operation—Data Error

In the case of a Multiple Block Read operation, every transferred block has a 16-bit CRC suffix. The Stop Transmission command (CMD12) will actually stop the data transfer operation (the same as in SD Bus mode).

Stop

From host to card(s)

DataIn

DataOut

Command

Response

From

card to

host

Data block crc Data block crc

Data from

card to host

Transmission

Command

From

card to

host

Response

Figure 5-3. Multiple Block Read Operation

5.1.4. Data Write

In SPI mode, the TriFlash supports single block or multiple block write operations. Upon reception of a valid write command (CMD24 or CMD25), the device will respond with a response token and will wait for a data block to be sent from the host. CRC suffix and start address restrictions are identical to the read operation (refer to Figure 5-4). The only valid block length, however, is 512 bytes. Setting a smaller block length will cause a write error on the next write command.

Data Response and Busy From Card

Command

Busy

New Command from Host

DataIn

DataOut

From Host to Card

Command

From Card to Host

Response

Start Block Token

Data Block

Data From Host to Card

Data_

Response

Figure 5-4. Single Block Write Operation

Every data block has a prefix or ‘start block’ token (one byte). After a data block is received the device will respond with a data-response token, and if the data block is received with no errors, it will be programmed. As long as the device is busy programming, a continuous stream of busy tokens will be sent to the host (effectively holding the dataOut line low).

5-3

SPI Protocol Definition

Once the programming operation is completed, the host must check the results of the programming using the SEND_STATUS command (CMD13). Some errors (e.g., address out of range, write protect violation) are detected during programming only. The only validation check performed on the data block and communicated to the host via the data-response token is CRC and general Write Error indication.

In Multiple Block write operation the stop transmission will be done by sending ’Stop Tran’ token instead of ’Start Block’ token at the beginning of the next block. In case of Write Error indication (on the data response) the host shall use SEND_NUM_WR_BLOCKS (ACMD22) in order to get the number of well written write blocks. The data token’s description is given in Section 5.2.4.

DataIn

DataOut

From Host to Card

Command

From Card to Host

Response

Start Block Token

Data Block

Data From Host to Car

Data_

Response

Data Response and Busy From Card

Busy

Stop Tran Token

Busy

From Host to Card

Command

Figure 5-5. Multiple Block Write Operation

Resetting the CS signal while the device is busy, will not terminate the programming process. The device will release the dataOut line (tristate) and continue to program. If the device is reselected before the programming is done, the dataOut line will be forced back to low and all commands will be rejected.

Resetting a device (using CMD0) will terminate any pending or active programming operation. This may destroy the data formats on the device. It is the host’s responsibility to prevent it.

5.1.5. Erase and Write Protect Management

The erase and write protect management procedures in the SPI mode are identical to the SD Bus mode. While the device is erasing or changing the write protection bits of the predefined sector list it will be in a busy state and will hold the dataOut line low. Figure 5-6 illustrates a “no data” bus transaction with and without busy signaling.

Figure 5-6. “No Data” Operations

SPI Protocol Definition

5.1.6. Read CID/CSD Registers

Unlike the SD Bus protocol (where the register contents are sent as a command response), reading the contents of the CSD and CID registers in SPI mode is a simple read-block transaction. The device will respond with a standard response token followed by a data block of 16 bytes suffixed with a 16-bit CRC.

The data time-out for the CSD command cannot be set to the device TAAC since this value is stored in the CSD. Therefore, the standard response time-out value (N

) is used for read latency of the CSD register.

5.1.7. Reset Sequence

The TriFlash requires a defined reset sequence. After power on reset or CMD0 (software reset), the device enters an idle state. At this state, the only legal host commands are CMD1 (SEND_OP_COND), ACMD41 (SD_SEND_OP_COND), CMD59 (CRC_ON_OFF) and CMD58 (READ_OCR).

The host must poll the device (by repeatedly sending CMD1) until the ‘in-idle-state’ bit in the device response indicates (by being set to 0) that the device completed its initialization processes and is ready for the next command.

In SPI mode, however, CMD1 has no operands and does not return the contents of the OCR register. Instead, the host can use CMD58 (SPI Mode Only) to read the OCR register. It is the responsibility of the host to refrain from accessing devices that do not support its voltage range.

The use of CMD58 is not restricted to the initialization phase only, but can be issued at any time. The host must poll the device (by repeatedly sending CMD1) until the ‘in-idle-state’ bit in the device response indicates (by being set to 0) that the device has completed its initialization process and is ready for the next command.

5.1.8. Clock Control

The SPI bus clock signal can be used by the SPI host to set the devices to energy-saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to change the clock frequency or shut it down.

There are a few restrictions the SPI host must follow:

• The bus frequency can be changed at any time (under the restrictions of maximum data transfer

frequency, defined by the TriFlash devices).

• It is an obvious requirement that the clock must be running for the TriFlash to output data or response

tokens. After the last SPI bus transaction, the host is required to provide 8 (eight) clock cycles for the device to complete the operation before shutting down the clock. Throughout this 8-clock period, the state of the CS signal is irrelevant. It can be asserted or de-asserted. Following is a list of the various SPI bus transactions:

− A command/response sequence. Eight clocks after the device response end bit. The CS signal can

be asserted or de-asserted during these 8 clocks.

− A read data transaction. Eight clocks after the end bit of the last data block.

− A write data transaction. Eight clocks after the CRC status token.

5-5

SPI Protocol Definition

• The host is allowed to shut down the clock of a “busy” device. The TriFlash will complete the

programming operation regardless of the host clock. However, the host must provide a clock edge for the device to turn off its busy signal. Without a clock edge, the TriFlash (unless previously disconnected by de-asserting the CS signal) will force the dataOut line down, permanently.

5.1.9. Error Conditions

The following sections provide valuable information for TriFlash error conditions.

5.1.9.1. CRC and Illegal Commands

Unlike the SD Bus protocol, in SPI mode the device will always respond to a command. The response indicates acceptance or rejection of the command. A command may be rejected in any one of the following cases:

• It is sent while the device is in read operation (except CMD12 which is legal).

• It is sent while the device is in Busy.

• Device is locked and it is other than Class 0 or 7 commands.

• It is not supported (illegal opcode).

• CRC check failed.

• It contains an illegal operand.

• It was out of sequence during an erase sequence.

NOTE: In case the host sends command while the device sends data in read operation then the response with an

illegal command indication may disturb the data transfer.

5.1.9.2. Read, Write and Erase Time-out Conditions

The times after which a time-out condition for read operations occur are (device independent) either 100 times longer than the typical access times for these operations given below or 100ms. The times after which a time-out

• Read—The read access time is defined as the sum of the two times given by the CSD parameters

TAAC and NSAC. These device parameters define the typical delay between the end bit of the read command and the start bit of the data block.

• Write—The R2W_FACTOR field in the CSD is used to calculate the typical block program time

obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g., SET (CLEAR)_WRITE_PROTECT, PROGRAM_CSD (CID) and the block write commands).

• Erase—The duration of an erase command will be (order of magnitude) the number of write blocks

(WRITE_BL) to be erased multiplied by the block write delay.

5.1.10. Memory Array Partitioning

Same as for SD Bus mode.

SPI Protocol Definition

5.1.11. Card Lock/Unlock

The Card Lock/Unlock feature is currently not supported in the SanDisk TriFlash.

5.1.12. Application Specific Commands

The Application Specific commands are identical to SD Bus mode with the exception of the APP_CMD status bit (refer to Section 3.5.5), which is not available in SPI.

5.1.13. Copyright Protection Commands

All the special Copyright Protection ACMDs and security functionality are the same as for SD Bus mode.

5.2. SPI Command Set

The following sections provide valuable information for TriFlash’s SPI command set.

5.2.1. Command Format

All the TriFlash commands are 6 bytes long and transmitted MSB first.

Byte 1 Bytes 2—5 Byte 6

7 6 5 0 31 0 7 0

0 1 Command Command Argument CRC 1

Commands and arguments are listed in Table 5-2.

7-bit CRC Calculation: G(x) = x

+ x3 + 1

M(x) = (start bit)∗x39 + (host bit)∗x38 +...+ (last bit before CRC)∗x CRC[6...0] = Remainder[(M(x)∗x

)/G(x)]

5.2.2. Command Classes

As in SD mode, the SPI commands are divided into several classes (See Table 5-1). Each class supports a set of device functions. A TriFlash device will support the same set of optional command classes in both communication modes (there is only one command class table in the CSD register). The available command classes, and the supported commands for a specific class, however, are different in the SD Bus and the SPI communication mode.

NOTE: Except the classes that are not supported in SPI mode (class 1, 3 and 9), the mandatory required classes for

the SD mode are the same for the SPI mode.

5-7

SPI Protocol Definition

Table 5-1. Command Classes in SPI Mode

Class Description

(CCC)

class 0 Basic + + + + + + + +

class 1 Not supported in SPI

class 2 Block read + + +

class 3 Not supported in SPI

class 4 Block write + + +

class 5 Erase + + +

class 6 Write-protection (Optional) + + +

class 7 Lock Card (Optional)2 +

class 8 Application specific + +

class 9 Not supported in SPI

class 10-11 Reserved

0 1 9 10 12 13 16 17 18 24 25 27 28 29 30 32 33 38 42 55 56 58 59

Supported Commands Card CMD Class

5.2.2.1. Detailed Command Description

The following table provides a detailed description of the SPI bus commands. The responses are defined in Section

5.2.3. The table below lists all TriFlash commands. A “yes” in the SPI mode column indicates that the command is supported in SPI mode. With these restrictions, the command class description in the CSD is still valid. If a command does not require an argument, the value of this field should be set to zero. The reserved commands are reserved in SD Bus mode as well.

The binary code of a command is defined by the mnemonic symbol. As an example, the content of the Command field for CMD0 is (binary) ‘000000’ and for CMD39 is (binary) ‘100111.’

The Lock Card command is currently not supported in the TriFlash.

SPI Protocol Definition

Table 5-2. Description of SPI Bus Commands

CMD

INDEX

SPI

Mode

Argument Resp Abbreviation Command Description

CMD0 Yes None R1 GO_IDLE_STATE Resets the TriFlash

CMD1 Yes None R1 SEND_OP_COND Activates the device’s initialization process.

CMD2 No

CMD3 No

CMD4 No

CMD5 Reserved

CMD6 Reserved

CMD7 No

CMD8 Reserved

CMD9 Yes None R1 SEND_CSD Asks the selected device to send its card-

specific data (CSD).

CMD10 Yes None R1 SEND_CID Asks the selected device to send its card

identification (CID).

CMD11 No

CMD12 Yes None R1b STOP_

TRANSMISSION

Forces the device to stop transmission during a multiple block read operation.

CMD13 Yes None R2 SEND_STATUS Asks the selected device to send its status

CMD14 No

CMD15 No

CMD16 Yes [31:0] block length R1 SET_BLOCKLEN Selects a block length (in bytes) for all following

block commands (read and write).

CMD17 Yes [31:0] data address R1 READ_SINGLE_

BLOCK

CMD18 Yes [31:0] data address R1 READ_MULTIPLE_

BLOCK

Reads a block of the size selected by the SET_BLOCKLEN command.

Continuously transfers data blocks from card to host until interrupted by a STOP_

TRANSMISSION command.

CMD19 Reserved

CMD20 No

CMD21 ... CMD23

CMD24 Yes [31:0] data address R15 WRITE_BLOCK Writes a block of the size selected by the

Reserved

SET_BLOCKLEN command.

CMD25 Yes [31:0] data address R1 WRITE_MULTIPLE_BLOCK Continuously writes blocks of data until a stop

transmission token is sent (instead of ‘start block’).

The only valid block length for write is 512 bytes. The valid block length for read is 1 to 512 bytes. A set block length of less

than 512 bytes will cause a write error. The device has a default block length of 512 bytes. CMD16 is not mandatory if the default is accepted.

The start address and block length must be set so that the data transferred will not cross a physical block boundary.

Data followed by data response plus busy.

The start address must be aligned on a sector boundary; the block length is always 512 bytes.

5-9

SPI Protocol Definition

CMD

INDEX

SPI

Mode

Argument Resp Abbreviation Command Description

CMD26 No

CMD27 Yes None R1 PROGRAM_CSD Programming of the programmable bits of the

CSD.

CMD28 Yes [31:0] data address R1b SET_WRITE_PROT If the device has write protection features, this

command sets the write protection bit of the addressed group. The properties of write protection are coded in the card specific data (WP_GRP_SIZE).

CMD294 Yes [31:0] data address R1b CLR_WRITE_PROT If the device has write protection features, this

command clears the write protection bit of the addressed group.

CMD30 Yes [31:0] write protect

data address

R1 SEND_WRITE_

PROT

If the device has write protection features, this command asks the device to send the status of the write protection bits.

CMD31 Reserved

CMD32 Yes [31:0] data address R1 ERASE_WR_BLK_START_

ADDR

CMD33 Yes [31:0] data address R1 ERASE_WR_BLK_END_AD

CMD34

Reserved

Sets the address of the first write block to be erased.

Sets the address of the last write block in a continuous range to be erased.

…. CMD37

CMD38 Yes [31:0] do not care8 R1b ERASE Erases all previously selected write blocks.

CMD39 No

CMD40 No

CMD41 Reserved

CMD42 Yes [31:0] stuff bits R1b LOCK_UNLOCK Set/reset the password or lock/unlock the card.

The size of the data block is defined by the SET_BLOCK_LEN command.

CMD43

Reserved

CDM54

CMD55 Yes [31:0] stuff bits R1 APP_CMD Notifies the device that the next command is an

application specific command rather than a standard command.

CMD56 Yes [31:0] stuff bits

[0]: RD/WR.

R1 GEN_CMD Used either to transfer a Data Block to the card

or to get a Data Block from the device for general purpose/application specific commands. The size of the Data Block is defined with SET_BLOCK_LEN command.

CMD57 Reserved

CMD58 Yes None R3 READ_OCR Reads the OCR register of a device.

32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits are

transferred in a payload format via the data line.

Do not care=The bit places must be filled but the values are irrelevant.

RD/WR_: “1”=the host will get a block of data from the card. “0”=the host sends a block of data to the card.

SPI Protocol Definition

CMD

INDEX

CMD59 Yes [31:1] do not care

SPI

Mode

Argument Resp Abbreviation Command Description

R1 CRC_ON_OFF Turns the CRC option on or off. A ‘1’ in the CRC

[0:0] CRC option

option bit will turn the option on, a ‘0’ will turn it off.

CMD60-

Table 5-3 describes all the application specific commands supported or reserved by the TriFlash. All the following commands should be preceded with APP_CMD (CMD55).

Table 5-3. Application Specific Commands Used or Reserved by the TriFlash SPI Mode

CMD

INDEX

ACMD6 No

ACMD13 yes [31:0] stuff bits R2 SD_STATUS Send the TriFlash status. The status fields are given

ACMD17 Reserved

ACMD18 yes -- -- -- Reserved for SD security applications.10

ACMD19 to ACMD21

SPI Mode Argument Resp Abbreviation Command Description

in Table 3-29.

Reserved

ACMD22 yes [31:0] stuff bits R1 SEND_NUM_WR_

BLOCKS

ACMD23 yes [31:23] stuff bits

[22:0]Number of blocks

R1 SET_WR_BLK_

ERASE_COUNT

Send the numbers of the well-written (without errors) blocks. Responds with 32bit+CRC data block.

Set the number of write blocks to be pre-erased before writing (to be used for faster Multiple Block write command). “1”=default (one write block).

ACMD24 Reserved

ACMD25 yes -- -- -- Reserved for SD security applications.

ACMD26 yes -- -- -- Reserved for SD security applications.

ACMD38 yes -- -- -- Reserved for SD security applications.

ACMD39

Reserved to ACMD40

ACMD41 yes None R1 SEND_OP_

Activates the device’s initialization process.

COND

ACMD42 yes [31:1] stuff bits

[0]set_cd

R1 SET_CLR_CARD_

DETECT

Connect[1]/Disconnect[0] the 50KOhm pull-up resistor on CD/DAT3 (pin 1) of the device. The pull-up may be used for card detection.

ACMD43

yes -- -- -- Reserved for SD security applications. ... ACMD49

ACMD51 yes [31:0] staff bits R1 SEND_SCR Reads the SD Configuration Register (SCR).

Refer to SD Memory Card Security Specification for detailed explanation about the SD Security Features.

The start address and block length must be set so that the data transferred will not cross a physical block boundary. Command

STOP_TRAN (CMD12) shall be used to stop the transmission in Write Multiple Block whether the pre-erase (ACMD23) feature is used or not.

5-11

SPI Protocol Definition

5.2.3. Responses

There are several types of response tokens. As in the SD Bus mode, all are transmitted MSB first.

5.2.3.1. Format R1

This response token is sent by the device after every command with the exception of SEND_STATUS commands. It is 1 byte long, the MSB is always set to zero and the other bits are error indications. A ‘1’ signals error.

The structure of the R1 format is given in Figure 5-7.

• In idle state: The device is in idle state and running initializing process.

• Erase reset: An erase sequence was cleared before executing because an out of erase sequence

command was received.

• Illegal command: An illegal command code was detected.

• Communication CRC error: The CRC check of the last command failed.

• Erase sequence error: An error in the sequence of erase commands occurred.

• Address error: A misaligned address, which did not match the block length was used in the command.

• Parameter error: The command’s argument (e.g., address, block length) was out of the allowed range

for this device.

In Idle State Erase Reset Illegal Command Com CRC Error Erase_Seq_Error

Address Error Parameter Error

Figure 5-7. R1 Response Format

5.2.3.2. Format R1b

This response token is identical to R1 format with the optional addition of the busy signal. The busy signal token can be any number of bytes. A zero value indicates device is busy. A non-zero value indicates device is ready for the next command.

5.2.3.3. Format R2

This 2-bytes long response token is sent by the device as a response to the SEND_STATUS command. The format of the R2 status is given in Figure 5-8.

SPI Protocol Definition

7 Byte 1 0 7 Byte 2 0 0

Card is Locked WP Erase Skip, Lock/Unlock Cmd Failed Error CC Error Card ECC Failed WP Violation Erase Param Out of Range, CSD_Overwrite In Idle State Erase Reset Illegal Command Com CRC Error Erase Sequence Error Address Error Parameter Error

Figure 5-8. R2 Response Format

The first byte is identical to response R1. The content of the second byte is described below:

• Erase param: An invalid selection, sectors for erase.

• Write protect violation: The command tried to write a write-protected block.

• Device ECC failed: Device internal ECC was applied but failed to correct the data.

• CC error: Internal device controller error.

• Error: A general or an unknown error occurred during the operation.

• Write protect erase skip: Only partial address space was erased due to existing WP blocks.

• Card is locked: not supported by the SanDisk TriFlash.

5.2.3.4. Format R3

This response token is sent by the device when a READ_OCR command is received. The response length is 5 bytes. The structure of the first (MSB) byte is identical to response type R1. The other four bytes contain the OCR register.

39 3231 0

R1 OCR

Figure 5-9. R3 Response Format

5-13

SPI Protocol Definition

5.2.3.5. Data Response

Every data block written to the device will be acknowledged by a data response token. It is one byte long and has the following format:

76 0

x x x 0 Status 1

The meaning of the status bits is defined as follows:

• ‘010’—Data accepted

• ‘101’—Data rejected due to a CRC error

• ’110’—Data Rejected due to a Write Error

In case of any error (CRC or Write Error) during Write Multiple Block operation, the host shall stop the data transmission using CMD12. In case of Write Error (response ’110’) the host may send CMD13 (SEND_STATUS) in order to get the cause of the write problem. ACMD22 can be used to find the number of well written write blocks.

5.2.4. Data Tokens

Read and write commands have data transfers associated with them. Data is being transmitted or received via data tokens. All data bytes are transmitted MSB.

Data tokens are 4 to 515 bytes long and have the following format:

For Single Block Read, Single Block Write and Multiple Block Read:

• First byte: Start Block

7 0

11111110

• Bytes 2-513 (depends on the data block length): User data

• Last two bytes: 16 bit CRC

For Multiple Block Write operation:

• First byte of each block

If data is to be transferred then—Start Block

7 0

11111100

If Stop transmission is requested—Stop Tran

7 0

11111101

SPI Protocol Definition

NOTE: This format is used only for Multiple Block Write. In case of Multiple Block Read the stop transmission is

done using STOP_TRAN Command (CMD12).

5.2.5. Data Error Token

If a read operation fails and the device cannot provide the required data it will send a data error token, instead. This token is one byte long and is shown in Figure 5-10.

000

Figure 5-10. Data Error Token

The four least significant bits (LSB) are the same error bits as in response format R2.

5.2.6. Clearing Status Bits

As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different formats: response R1, response R2 and data error token (the same bits may exist in multiple response types—e.g., Device ECC failed).

As in the SD Bus mode, error bits are cleared when read by the host, regardless of the response format.

Error CC Error Card ECC Failed Out of Range Card is Locked

5.3. Card Registers

In SPI Mode, only the OCR, CSD and CID registers are accessible. Their format is identical to their format in the SD Bus mode. However, a few fields are irrelevant in SPI mode.

5.4. SPI Bus Timing Diagrams

All timing diagrams use the schematics and abbreviations listed in Table 5-4.

5-15

SPI Protocol Definition

Table 5-4. SPI Bus Timing Diagrams

H Signal is high (logical ‘1’)

L Signal is low (logical ‘0’)

X Do not care

Z high impedance state (-> = 1)

* repeater

Busy Busy Token

Command Command token

Response Response token

Data block Data token

The host must keep the clock running for at least NCR clock cycles after the device response is received. This restriction applied to command and data response tokens.

5.4.1. Command/Response

Host Command to Device Response—Device is Ready

CS <-NCS-> <-NEC-> DataIN <-NCR-> DataOut

H H L L L * * * * * * * * * * * * * * * * * * * L L L L H H H

X X H H H H 6 Bytes Command H H H H H * * * * * * * * * * * * * * * H H H H X X X

Z Z Z H H H H * * * * * * * * H H H H H 1 or 2 Bytes Response H H H H H Z Z

Figure 5-11. Host Command to Device Response Device is Ready

Host Command to Device Response—Device is Busy

The following timing diagram describes the command response transaction for commands when the device responds with the R1b response type (e.g., SET_WRITE_PROT and ERASE). When the device is signaling busy, the host may deselect it (by raising the CS) at any time. The device will release the DataOut line one clock after the CS going high. To check if the device is still busy it needs to be reselected by asserting (set to low) the CS signal. The device will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.

CS <-NCS-> <-NEC-> <-NDS-> <-NEC-> DataIN <-NCR-> DataOut

H L L L * * * * * * * * * * * * * * * * * * * L L L L H H H L L L L L L H H

X H H H H 6 Bytes Command H H H H H H H H H H H H H X X X H H H H H H X X

Z Z H H H H * * * * * * * * H H H H Card Response Busy L Z Z Z Busy H H H H Z

Figure 5-12. Host Command to Device Response Device is Busy

SPI Protocol Definition

Device Response to Host Command

DataIN <-NCR-> DataOut

L L L L L * * * * * * * * * * * * * * * * * * * L L H H H

H H H H H H * * * * * * * * * * * H H H H 6 Bytes Command H H H H X X X

H H H H H 1 or 2 Bytes Response H H H H * * * * * * * * * * * * * * * * * H H H H H Z Z

Figure 5-13. Device Response to Host Command

5.4.2. Data Read

The following timing diagram describes all single block read operations with the exception of SEND_CSD command.

DataIN

DataOut

H L L L * * * * * * * * * * * * * * * * * * * * * * * * * * * * L L L H H H H

<-NCS-> <-NEC->

X H H H H Read Command H H H H H * * * * * * * * * * * * * * * * * * * * * * * * * H H H X X X X

<-NCR-> <-NAC->

Z Z H H H H * * * * * * * * H H H H Card Response H H H H Data Block H H H H Z Z Z

Figure 5-14. Single Block Read Operations

The following diagram describes Stop transmission operation in case of Multiple Block Read.

CS L L L L * * * * * * * * * * * * * * * * * * * *

<-NCS->

DataIN X H H H H Stop Tran command H H H H H * * * * ** * * *

<-NCR->

DataOut Data Transfer to host H H Card Response H

<2clk>

Figure 5-15. Stop Transmission Operation

Reading the CSD Register

The following timing diagram describes the SEND_CSD command bus transaction. The timeout values for the response and the data block are N

CS H L L L * * * * * * * * * * * * * * * * * * * L L L H H H H

<-NCS-> <-NEC->

DataIN X H H H H Read Command H H H H H * * * * * * * * * * * * * * * H H H X X X X

<-NCR-> <-NCX-> DataOut Z Z H H H H * * * * * * * * H H H H Card Response H H H H Data Block H H H H Z Z Z

(since the NAC is still unknown).

Figure 5-16. SEND_CDS Command Bus Transaction

5.4.3. Data Write

The host may deselect a device (by raising the CS) at any time during the device busy period (refer to the given timing diagram). The device will release the DataOut line one clock after the CS goes high. To check if the device is still busy, it needs to be re-selected by asserting (set to low) the CS signal.

5-17

SPI Protocol Definition

The device will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.

DataIN

DataOut

H L * * * * * * * * * * * * * * * * * * * L L L L L L L L H H H L L L L

<-NCS-> <-NWR-> <-NEC-> <-NDS->

X H H H Write Command H H H H H H H Data Block H H H H H H X X X H H H H

<-NCR->

Z Z H H H * * * * * * * * H H H Card Resp H H H H H H H Data Resp Busy L Z Z Z Busy H

Figure 5-17. Data Write Operation

Figure 5-18 shows stop transmission operation in Multiple Block Write transfer.

CS L L L L L L L L L L L L L L L L L L L L L L H H H L L L L

<NWR-> <1byte-> <NBR-> <NEC-> <-NDS->

DataIn Data Block H H H H H H H H H Stop Tran

Token

DataOut H H H H Data Resp Busy H H H H H H H H H Busy12 L Z Z Z Busy H

H H H X X X H H H H

Figure 5-18. Stop Transmission Operation

5.4.4. Timing Values

Table 5-5. Timing Constants Definitions

Min Max Unit

NCS 0 - 8 Clock Cycles

NCR 0 8 8 Clock Cycles

NRC 1 - 8 Clock Cycles

NAC 1 See footnote13 8 Clock Cycles

NWR 1 - 8 Clock Cycles

NEC 0 - 8 Clock Cycles

NDS 0 - 8 Clock Cycles

NBR 0 1 8 Clock Cycles

NCX 0 8 8 Clock Cycles

5.5. SPI Electrical Interface

The SPI Mode electrical interface is identical to that of the SD Bus mode.

The Busy may appear within NBR clocks after Stop Tran Token. If there is no Busy the host may continue to the next

command.

maximum value shall be calculated using the following equation: MIN [([TAAC ∗ f + NSAC ∗ 100] ∗ 100/8), (100ms ∗

f/8)].

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