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awarded and pending.
Document 20-10-00038 Rev. 12.0
Revision History
Date Revision Description
February 2007 12.0 Merged CFlash 11.2 manual with CF ExtremeIII
v1.2 to create v12.0; updated to comply with CFA
Spec v4.0.
SanDisk CompactFlash® Memory Card products provide high capacity solid-state flash
memory that electrically complies with the Personal Computer Memory Card International
Association ATA (PC Card ATA) standard. (In Japan, the applicable standards group is
JEIDA.) The CompactFlash Memory Card Series also supports a True IDE Mode that is
electrically compatible with an IDE disk drive. The original CF form factor card can be used in
any system that has a CF slot, and with a Ty pe II PCMCIA adapter can be used in any system
that has a PCMCIA Type II or Type III socket.
CompactFlash Memory cards use SanDisk Flash memory, which was designed by SanDisk
specifically for use in mass storage applications. In addition to the mass storage-specific flash
memory chips, CompactFlash Memory cards include an on-card intelligent controller that
provides a high level interface to the host computer. This interface allows a host computer to
issue commands to the memory card to read or write blocks of memory. The host addresses the
card in 512 byte sectors. Each sector is protected by a powerful Erro r Correcting Code (ECC).
The on-card intelligent controller in the CompactFlash Memory Card manages interface
protocols, data storage and retrieval as well as ECC, defect handling and diagnostics, power
management and clock control. Once the card has been configured by the host, it appears to the
host as a standard ATA (IDE) disk drive. Additional ATA commands have been provided to
enhance system performance.
The host system can support as many cards as there are CompactFlash and PCMCIA Type II or
III card slots. The original form factor CompactFlash Memory cards require a PCMCIA Type
II Adapter to be used in a PCMCIA Type II or Type III socket.
SanDisk CompactFlash Memory cards provide the following system features:
• Up to 16 GB of mass storage data
• PC Card ATA protocol compatible
• True IDE Mode compatible
• Very low CMOS power
• Very high performance
• Very rugged
• Low weight
• Noiseless
• Low Profile
• +5 Volts or +3.3 Volts operation
• Automatic error correction and retry capabilities
• Supports power down commands and sleep modes
• Non-volatile storage (no battery required)
• MTBF >1,000,000 hours
• Minimum 10,000 insertions
1.3 Scope
This document describes the key features and specifications of CompactFlash Memory cards,
as well as the information required to interface this product to a host system. Retail
CompactFlash specifications are not covered in this manual.
1.4 CompactFlash Standard
SanDisk CompactFlash Memory cards are fully compatible with the CompactFlash
Specification published by the CompactFlash Association. Contact the CompactFlash
Association for more information.
CompactFlash Association
P.O. Box 51537
Palo Alto, CA 94303
USA
Phone: 415-843-1220
Fax: 415-493-1871
www.compactflash.org
SanDisk CompactFlash Memory cards are fully electrically compatible with the PCMCIA
specifications listed below:
•PCMCIA PC Card Standard, 7.0, February 1999
•PCMCIA PC Card ATA Specification, 7.0, February 1999
These specifications may be obtained from:
PCMCIA
2635 N. First Street, Suite 209
San Jose, CA 95131
USA
Phone: 408-433-2273
Fax: 408-433-9558
1.6 Related Documentation
ATA operation is governed by the ATA-4 specification published by ANSI. For more
information, refer to the American National Standard X3.221: AT Attachment for Interface for
Disk Drives document.
Documentation can be ordered from IHS by calling 1-800-854-7179 or accessing their Web
site: http://global.ihs.com.
1.7 Functional Description
CompactFlash Memory cards contain a high level, intelligent subsystem as shown in the block
diagram, Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities
not found in other types of memory cards. These capabilities include the following:
•Standard ATA register and command set (same as found on most magnetic disk drives).
•Host independence from details of erasing and programming flash memory.
•Sophisticated system for managing defects (analogous to systems found in magn etic disk
drives).
•Sophisticated system for error recovery including a powerful error correction code (ECC).
•Power management for low power operation.
•Implementation of dynamic and static wear-leveling to extend card’s life.
The 512-byte sector size of the CompactFlash Memory Card is the same as that in an IDE
magnetic disk drive. T o write or read a sector (or multiple sectors), the host computer software
simply issues a Read or Write command to the card. This command contains the address and
the number of sectors to write/read. The host software then waits for the command to
complete.
The host software does not get involved in the details of how the flash memory is erased,
programmed or read. This is extremely important as flash devices are expected to get more and
more complex in the future. Because the CompactFlash Memory Card Series uses an
intelligent on-board controller, the host system software will not require changing as new flash
memory evolves. In other words, systems that support CompactFlash Memory cards now, will
be able to access future SanDisk cards built with new flash technology without having to
update or change host software.
1.7.2 Defect and Error Management
CompactFlash Memory cards contain a sophisticated defect and error management system.
This system is analogous to the systems found in magnetic disk drives and in many cases
offers enhancements. If necessary, the cards will rewrite data from a defective sector to a good
sector. This is completely transparent to the host and does not consume any user data space.
The CompactFlash Memory Card soft error rate specification is much better than the magnetic
disk drive specification. In the extremely rare case a read error does occur, CompactFlash
Memory cards have innovative algorithms to recover the data by using hardware on-the-fly
Error Detection Code/Error Correction Code (EDC/ECC), based on a BCH algorithm.
These defect and error management systems, coupled with the solid state construction, give
SanDisk CompactFlash cards unparalleled reliability
1.7.3 Wear Leveling
Wear Leveling is an intrinsic part of the erase pooling functionality of SanDisk CompactFlash
using NAND memory. The CF WEAR LEVEL command is supported as a NOP operation to
maintain backward compatibility with existing software utilities. Advanced featu res of
dynamic and static wear-leveling, and automatic block management are used to ensure high
data reliability and maximize flash life expectancy.
1.7.4 Using Erase Sector and Write Commands
SanDisk CompactFlash Memory cards support the CF ERASE SECTOR and WRITE
WITHOUT ERASE commands. In some applications, write operations may be faster if the
addresses being written are first erased with the ERASE SECTOR command. WRITE
WITHOUT ERASE behaves as a normal write command and no performance gain results
from its use.
A unique feature of the SanDisk CompactFlash Memory Card is automatic entrance and exit
from sleep mode. Upon completion of a command, the card will enter sleep mode to conserve
power if no further commands are received within 5 msec. The host does not have to take any
action for this to occur. In most systems, the CompactFlash Memory Card is in sleep mode
except when the host is accessing it, thus conserving power. The delay from command
completion to entering sleep mode is adjustable.
When the host is ready to access the card and is in sleep mode, any command issued to it will
cause the card to exit sleep and respond. The host does not have to follow the ATA protocol of
issuing a reset first. It may do this if desired, but it is not needed. By not issuing the reset,
performance is improved through the reduction of overhead but this must be done only for the
SanDisk products as other ATA products may not support this feature.
1.7.6 Dynamic Adjustment of Performance vs. Power Consumption
This feature is no longer supported. This command will be treated as a NOP (No Operation) to
guarantee backward compatibility.
1.7.7 Power Supply Requirements
This is a dual voltage product, which means it will operate at a voltage range of 3.30 volts ±
5% or 5.00 volts ± 10%. Per the PCMCIA specification Section 2.1.1, the host system must
apply 0 volts in order to change a voltage range. This same procedure of providing 0 volts to
the card is required if the host system applies an input voltage outside the desired voltage by
more than 15%. This means less than 4.25 volts for the 5.00-volt range and less than 2.75 volts
for the 3.30 volt range.
NOTE: The Sleep to Write and Sleep to Read times are the times it takes the
2.5 ms maximum
20 ms maximum
50 ms typical; 400 ms maximum
20.0 MB/sec burst
25.0 MB/sec burst
CompactFlash Memory Card to exit sleep mode when any command
is issued by the host to when the card is reading or writing.
CompactFlash Memory cards do not require a reset to exit sleep
mode.
The host connects to SanDisk CompactFlash Memory cards using a standard 50-pin connector
consisting of two rows of 25 female contacts each on 50 mil (1.27 mm) centers.
3.1.1 Pin Assignments and Types
The signal/pin assignments are listed in Table 3-1. Low active signals have a "-" prefix. Pin
types are Input, Output or Input/Output. Sections 3.3.1 and 3.3.2 define the DC characteristics
for all input and output type structures..
9 -ATA SEL I I3U 34 -IORD I I3Z
10 A09 I I1Z 35 -IOWR I I3Z
11 A08 I I1Z 36 -WE I I3U
12 A07 I I1Z 37 INTRQ O OZ1
13 VCC – Power 38 VCC – Power
14 A06 I I1Z 39 -CSEL I I2U
15 A05 I I1Z 40 -VS2 O OPEN
16 A04 I I1Z 41 RESET I I2Z
17 A03 I I1Z 42 IORDY O OT1
18 A02 I I1Z 43 -DMARQ O OZ1
19 A01 I I1Z 44 -DMACK I I3U
20 A00 I I1Z 45 -DASP I/O I1U,ON1
21 D00 I/O I1Z,OZ3 46 -PDIAG I/O I1U,ON1
22 D01 I/O I1Z,OZ3 47 D08 I/O I1Z,OZ3
23 D02 I/O I1Z,OZ3 48 D09 I/O I1Z,OZ3
24 -IOCS16 O ON3 49 D10 I/O I1Z,OZ3
25 -CD2 O Ground 50 GND – Ground
Signal
Name Pin Type I/O Type Pin No.
3.2Electrical Description
Signal
Name Pin Type I/O Type
The CompactFlash Memory Card Series is optimized for operation with hosts, which support
the PCMCIA I/O interface standard conforming to the PC Card ATA specification. However,
the card may also be configured to operate in systems that support only the memory interface
standard. The CompactFlash card configuration is controlled using the standard PCMCIA
configuration registers starting at address 200h in the Attribute Memory space of the card.
Table 3-4 describes the I/O signals. Signals whose source is the host are designated as inputs
while signals that the card sources are outputs. SanDisk CompactFlash Memory Card logic
levels conform to those specified in Section 3.3 of the PCMCIA Release 2.1 Specification.
NOTE: The sleep-to-write and sleep-to-read times are the time it takes the
card to exit sleep mode when any command is issued by the host to
when the card is reading or writing. CompactFlash Memory cards do
not require a reset to exit sleep mode.
I/O 46 This signal is asserted high as the BVD1 signal
I/O 45 This output line is always driven to a high state
O 26, 25 These Card Detect pins are connected to
I 7, 32 The Card Enable input signals are used both to
I 39 This signal is not used for PC Card Memory
18, 19, 20
These address lines, along with the -REG
signal, are used to select the following: I/O port
address registers within the card, memorymapped port address registers within the card,
a byte in the card's information structure and its
configuration control and status registers.
In True IDE Mode only A[2:0] is used to select
one of eight registers in the Task File.
In True IDE Mode these remaining address
lines should be grounded by the host.
since a battery is not used with this product.
The Status Changed signal is asserted low to
alert the host to changes in the RDY/-BSY and
Write Protect states, while the I/O interface is
configured. Its use is controlled by the Card
Config. and Status Register.
In the True IDE Mode, this input/output is the
Pass Diagnostic signal in the master/slave
handshake protocol.
in Memory Mode since a battery is not required
for this product.
This output line is always driven to a high state
in I/O Mode since this product does not support
the audio function.
In the True IDE Mode, this input/output is the
Disk Active/Slave Present signal in the master/
slave handshake protocol.
ground on the card. They are used by the host
to determine if the card is fully inserted into its
socket.
select the card and to indicate to the card
whether a byte or a word operation is being
performed. -CE2 always accesses the odd
byte of the word. -CE1 accesses the even byte
or the Odd byte of the word depending on A0
and -CE2. A multiplexing scheme based on
A0, -CE1, -CE2 allows 8 bit hosts to access all
data on D0-D7.
In True IDE Mode, -CS0 is the chip select for
the Task File registers while -CS1 is used to
select the Alternate Status Register and the
Device Control Register.
This internally pulled up signal is used to
configure this device as a master or slave when
configured in the True IDE Mode. When this pin
is grounded, this device is configured as a
master. When the pin is open, this device is
configured as a slave.
These lines carry the data, commands and
status information between the host and the
controller. D00 is the LSB of the Even Byte of
the word. D08 is the LSB of the Odd Byte of the
word.
In True IDE Mode, all Task File operations
occur in byte mode on the low order bus D00D07 while all data transfers are 16 bits using
D00-D15.
The Input Acknowledge signal is asserted by
the card when it is selected and responding to
an I/O read cycle at the address that is on the
address bus. This signal is used by the host to
control the enable of any input data buffers
between the card and the CPU.
This signal is used for DMA data transfers
between host and device and is asserted by the
device when it is ready to transfer data to or
from the host. The direction of data transfer is
controlled by DIOR- and DIOW-. This signal is
used in a handshake manner with DMACK(i.e., the device waits until the host asserts
DMACK- before negating DMARQ, and
reasserting DMARQ if there is more data to
transfer).
This is an I/O read strobe generated by the
host. This signal gates I/O data onto the bus
from the card when the card is configured to
use the I/O interface.
The I/O write strobe pulse is used to clock I/O
data on the Card Data bus into the card
controller registers when the card is configured
to use the I/O interface.
The clocking will occur on the negative to
positive edge of the signal (trailing edge).
the host interface. It is used to read data from
the card in Memory Mode and to read the CIS
and configuration registers.
In PC Card I/O Mode, this signal is used to read
the CIS and configuration registers.
To enable True IDE Mode this input should be
grounded by the host.
the card is ready to accept a new data transfer
operation and held low when the card is busy.
The host memory card socket must provide a
pull-up resistor.
At power up and at reset, the RDY/-BSY signal
is held low (busy) until the card has completed
its power up or reset function. No access of any
type should be made to the card during this
time. The RDY/-BSY signal is held high
(disabled from being busy) whenever the
following condition is true: The card has been
powered up with +RESET continuously
disconnected or asserted.
I/O Operation–After the card has been
configured for I/O operation, this signal is used
as an interrupt request. This line is strobed low
to generate a pulse mode interrupt or held low
for a level mode interrupt.
In True IDE Mode, this signal is the active high
Interrupt Request to the host.
during memory cycles to distinguish between
Common Memory and Register (Attribute)
Memory accesses: High for common memory,
and low for attribute memory.
The signal must also be active (low) during I/O
cycles when the I/O address is on the bus.
O 33, 40 Voltage Sense Signals. -VS1 is grounded so
O 42 SanDisk CompactFlash Memory cards do not
I 36 This is a signal driven by the host and used for
O 24 Memory Mode–The CompactFlash Card does
This signal is used by the host in response to
DMARQ to initiate DMA transfers.
NOTE: This signal may be negated by the host
to suspend the DMS transfer in process. For
Multiword DMA transfers, the device may
negate DMARQ with the t
specified time once
L
the DMACK- is asserted and reasserted again
at a later time to resume DMA operation.
Alternatively, if the device is able to continue
the data transfer, the device may leave
DMARQ asserted and wait for the host to
reassert DMACK-.
card. The card is reset only at power-up if this
pin is left high or open from power-up. The card
is also reset when the Soft Reset bit in the Card
Configuration Option Register is set.
In the True IDE Mode this input pin is the active
low hardware reset from the host.
that the CompactFlash Card CIS can be read at
3.3 volts and VS2 is open and reserved by
PCMCIA for a secondary voltage.
assert the -WAIT signal.
SanDisk CompactFlash Memory cards do not
assert the -WAIT signal.
SanDisk CompactFlash Memory cards, except
when in UDMA modes, do not assert an IORDY
signal.
strobing memory write data to the registers of
the card when it is configured in the Memory
Interface Mode. It is also used for writing the
configuration registers.
In PC Card I/O Mode, this signal is used for
writing the configuration registers.
In True IDE Mode this input signal is not used
and should be connected to VCC by the host.
not have a write-protect switch. This signal is
held low after the completion of the reset
initialization sequence.
I/O Operation–When the card is configured for
I/O Operation, pin 24 is used for the -I/O
Selected is 16 Bit Port (-IOIS16) function. A low
signal indicates that a 16-bit or odd-byte only
operation can be performed at the addressed
port.
This output signal is asserted low when this
device is expecting a word data transfer cycle.
3.3Electrical Specification
All D.C. Characteristics for the CompactFlash Memory Card Series are defined as follows:
T ypical conditions unless otherwise stated:
= 5V +/- 10%
V
CC
= 3.3V +/- 5%
V
CC
Ta = 0 °C to 60 °C
Absolute Maximum conditions:
= -0.3V min. to 6.5V max.
V
CC
V* = 0.5V min. to V
*Voltage on any pin except V
+ 0.5V max.
CC
with respect to GND.
CC
3.3.1 Input Leakage Control and Input Characteristics
In Table 3-5, “x” refers to the characteristics described in Table 3-6. For example–"I1U"
indicates a pull-up resistor with a Type 1 input characteristic.
Table 3-5 Input Leakage Control
Type Parameter Symbol Conditions MIN MAX Unit
lxZ Input Leakage Current IL Vih=VCC/Vil=GND -1 1 uA
IxU Pull Up Resistor RPU1 VCC=5.0V 50k 500k Ohm
IxD Pull Down Resistor RPD1 VCC=5.0V 50k 500k Ohm
NOTE: The minimum pull-up resistor leakage current meets the PCMCIA
specification of 10k ohms but is intentionally higher in the
CompactFlash Memory Card Series product to reduce power use.
T able 3-6 defines the input characteristics of the parameters in Table 3-5.
Table 3-6 Input Characteristics
Min. Typ. Max. Min. Typ. Max.
Type Parameter Symbol VCC = 3.3V VCC = 5.0V Unit
1 Input Voltage Vih 2.4 4.0 V
CMOS Vil 0.6 0.8
2 Input Voltage Vih 1.5 2.0 V
CMOS Vil 0.6 0.8
3 Input Voltage Vth 1.8 2.8 V
CMOS Vtl 1.0 2.0
Schmitt Trigger
3.3.2 Output Drive Type and Characteristics
In Table 3-7 "x" refers to the characteristics desc ribed in Table 3-8. For example–"OT3" refers
to Totempole output with a Type 3 output drive characteristic.
Table 3-7 Output Drive Type
Type Output Type Valid Conditions
OTx Totempole loh & lol
OZx Tri-state N-P Channel loh & lol
OPx P-Channel Only loh only
ONx N-Channel Only loh Only
Table 3-8 Output Drive Characteristics
Type Parameter Symbol Conditions Min. Typ. Max. Unit
Figure 3-2 Power Up/Power Down Timing for Systems not supporting RESET
t
pr
V
CC
VCC Min.
V
IH
2V
Always Hi-z from system
RESET
V
CC
-CE1, -CE2
3.3.4 Common Memory Read Timing
Table 3-10 contains common memory read timing specifications for all types of memory.
NOTE: All timings measured at the CompactFlash Memory Card. Skews and
delays from the system driver/receiver to the card must be accounted
for by the system.
tSU(VCC)
Supplied by pull-up resistor
on card (if present)
t
pf
VCC Min.
t
rec
2V
-CE1, -CE2
V
IH
Table 3-10 Common Memory Read Timing Specification
100 ns
Speed Version Item Symbol
Read Cycle Time t
Address Access Time
a
Card Enable Access Time t
Output Enable Access Time t
Output Disable Time from -OE t
Output Disable Time from -CE t
Output Enable Time from -CE t
Output Enable Time from -OE t
Table 3-10 Common Memory Read Timing Specification
100 ns
Speed Version Item Symbol IEEE Symbol
Address Hold Time th (A) 15t
Card Enable Setup Time t
Card Enable Hold Time t
(CE) 0t
su
(CE) 15t
h
a. The -REG signal timing is identical to address signal timing
3.3.5 Common and Attribute Memory Write Timing
The write timing specifications for Common and Attribute memory are the same.
All timings measured at the CompactFlash Memory Card. Skews and delays from the system
driver/receiver to the card must be accounted for by the system
NOTE: SanDisk CompactFlash Memory cards do not assert the -WAIT
signal.
Table 3-11 Common and Attribute Memory Write Timing Specification
Speed Version Symbol IEEE Symbol
Write Cycle Time t
Write Pulse Width t
Address Setup Time
Address Setup Time for -WE
a
a
Card Enable Setup Time for -WE t
Data Setup Time form -WE t
Data Hold Time t
Write Recover Time t
Output Disable Time from -WE
Output Disable Time from -OE t
Output Enable Time from -WE t
Output Enable Time from -OE t
Output Enable Setup from -WE t
Output Enable Hold from -WE
Card Enable Setup Time t
Card Enable Hold Time t
a. The -REG signal timing is identical to address signal timing.