This Service Manual is a property of Samsung Electronics Co.,Ltd.
Any unauthorized use of Manual can be punished under applicable
International and/or domestic law.
ⓒ
Samsung Electronics Co.,Ltd. June. 2003
Printed in Korea.
Code No.: GH68-04326A
BASIC.
1. SGH-X100 Specification
1. GSM General Specification
GSM900
Phase 1
Freq. Band[MHz]
Uplink/Downlin k
ARFCN range1~12 40~124 & 975~1023512~885
Tx/Rx spacin g45MHz45MHz95MHz
Mod. Bit rate/
Bit Period
Time Slot Period/Frame
Period
Modulation0.3GMSK0.3GMSK0.3GMSK
MS Power33dBm~13 dBm33dBm~5dBm30dBm~0dBm
890~915
935~960
270.833k bps
3.69 2us
576.9us
4.61 5ms
EGSM 900
Phase 2
880~915
925~960
270.833k bps
3.69 2us
576.9us
4.61 5ms
DCS1800
Phase 1
1710 ~1785
1805 ~1880
270.833k bps
3.69 2us
576.9us
4.61 5ms
Power Class5pcl ~ 15pcl5pcl ~ 19pcl0pcl ~ 15pcl
Sensitivity-102 dBm-102 dBm-100 dBm
TDMA Mux888
Cell Rad ius35Km35Km2Km
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SGH-V200 Specification
2. GSM TX power class
TX Power
control level
533±2 dBm
631±2 dBm
729±2 dBm
827±2 dBm
925±2 dBm
1023±2 dBm
1121±2 dBm
GSM900
TX Power
control level
030±3 dBm
128±3 dBm
226±3 dBm
324±3 dBm
422±3 dBm
520±3 dBm
618±3 dBm
DCS1800
1219±2 dBm
1317±2 dBm
1415±2 dBm
1513±2 dBm
1611±3 dBm
179±3dBm
187±3 dBm
195±3 dBm
716±3 dBm
814±3 dBm
912±4 dBm
1010±4 dBm
118±4dBm
126±4 dBm
134±4 dBm
142±5 dBm
150±5 dBm
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2. SGH-X100 Circuit Description
1. SGH-
X100
RF Circuit Description
1) RX PART
1. ASM(U100)→Switching Tx, Rx path for GSM900, DCS1800 by logic controlling.
2. ASM Control Logic (U104, U106)→Truth Table
VC1VC2
GSM Tx ModeHL
DCS Tx ModeLH
GSM Rx ModeLL
DCS Rx ModeLL
3. FILTER
To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.
- GSM FILTER (F101)→For filtering the frequency band between 925 ~ 960 MHz
- DCS FILTER (F102)→For filtering the frequency band 1805 and 1880 MHz.
4. VC-TCXO (OSC101)
To generate the 26MHz reference clock to drive the logic and RF. After additional process, the reference clock applies to
the U103 Rx IQ demodulator and Tx IQ modulator. The oscillator for RX IQ demodulator and Tx modulator are
controlled by serial data to select channel and use fast lock mode for GPRS high class operation.
5. Transceiver (U103)
The receiver front-end converts the aerial RF signal from EGSM, DCS bands down to a low intermediate frequency (IF)
of 100 kHz. The first stages are symmetrical low noise amplifiers (LNAs). They are matched to 50 ohm. The LNAs are
followed by an I, Q down-mixer. It consists of two mixers in parallel but driven by quadrature out of phase LO signals.
The In phase (I) and Quadrature phase (Q) IF signals are low pass filtered to provide protection from high frequency
offset interferes. The low IF I and Q signals are then fed into the channel filter. The front-end low IF I and Q outputs
enter the integrated bandpass channel filter with provision for five 8 dB gain steps in front of the filter.
2) TX PART
Baseband IQ signal fed into offset PLL, this function is included inside of U103 chip. OSC100 chip generates modulator
signal which power level is about 6.5dBm and fed into Power Amplifier(U101). The PA output power and power ramping
are well controlled by Auto Power Control circuit. We use offset PLL below
GSM-35dBc
DCS-35dBc
GSM-66dBc
DCS-65dBc
GSM-75dBc
DCS-68dBc
Modulation Spectrum
200kHz offset
30 kHz bandwidth
400kHz offset
30 kHz bandwidth
600kHz ~ 1.8MHz offset
30 kHz bandwidth
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SGH-X100 Circuit Description
2. Baseband Circuit description of SGH-X100
1) PCF50601
1.1 Power Management
Ten low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system
performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0V, and 5.0V SIMs, while
self-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as RTC
module and High Voltage Charge pump, Clock generator, aid in reducing both board area and system complexity.
I2C BUS serial interface provides access to control and configuration registers. This interface gives a microprocessor full
control of the PCF50601 and enables system designers to maximize both standby and talk times. Supervisory functions.
including a reset generator, an input voltage monitor, and a temperature sensor, support reliable system design. These
functions work together to ensure proper system behavior during start-up or in the event of a fault condition(low
microprocessor voltage, insufficient battery energy, or excessive die temperature).
1.2. Backlight Brightness Modulator
The Backlight Brightness Modulator (BBM) contains a programmable Pulse-width modulator (PWM) and FET to modulate
the intensity of a series of LED or to control a DC/DC converter that drives LCD backlight. This phone (SGH-X100) is
not use PWM, but use DC CONTROL (BACKLIGHT). So "BACKLIGHT" voltage is high value, backlight is bright.
1.3. Clock Generato
The Clock Generator (CG) generates all clocks for internal and external usage. The 32768 Hz crystal oscillator provides an
accurate low clock frequency for the PCF50601 and other circuitry.
r
2) Connector
2-1. LCD Connector
LCD is consisted of main LCD(color 65K STN LCD). Chip select signals in the U304, LCD_CS can enable LCD.
LCD_CS signal is LCD select signal. This signal is from ENABLE part of OM6357.
"RESET_2V8" signal initiates the Reset process of the LCD.
16-bit data lines(HD(0)~HD(15)) transfers data and commands to LCD through by pass capacitor. Data and commands use
"RS" signal. If this signal is high, Inputs to LCD are commands. If it is low, Inputs to LCD are data. The signal which
informs the input or output state to LCD, is required. But this system is not necessary this signal. So "L_WR" signal is
used to write data or commands to LCD. Power signali for LCD is "VDD3".
2-2. Key
This is consisted of key interface pins among OM6357, KBIO(0:7). These signals compose the matrix. Result of matrix
informs the key status to key interface in the OM6357. Power on/off key is seperated from the matrix. So power on/off
signal is connected with PCF50601 to enable PCF50601. Ten key LEDs use the "VDD_KEY" supply voltage.
"VDD_KEY" signal enables LEDs with current control.
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2. SGH-X100 Circuit Description
2-3. EMI ESD Filter
This system uses the EMI ESD filter, EMIF09 to protect noise from IF CONNECTOR part.
2-4. IF connetor
It is 18-pin connector. They are designed to use VBAT, V_EXT_CHARGE, TXD0, RXD0, RTS0, CTS0, JIG_REC,
CHARGER_OK, RXD1, TXD1, AUX_MIC, AUX_SPK and GND. They connected to power supply IC, microprocessor and
signal processor IC.
3) Battery Charge Management
a complete constant-current/constant-voltage linear charger for single cell lithium-ion batteries. If ta connected to phone,
"V_EXT_CHARGE" enable charger IC and supply current to battery. when fault condition caused, "CHG_ON" signal level
change low to high and charger IC stop charging process.
4) Audio
REC_P and REC_N from OM6357 are connected to the main receiver. AUXSP is connected to the Hands free kit.
MIC_P and MIC_N are connected to the main MIC. And AUX_MIC_P and AUX_MIC_N are connected to the Hands
free kit.
YMU762MA3 is a LSI for portable telephone that is capable of playing high quality music by utilizing FM sy nthesizer
and ADPCM decorder that are included in this device. As a synthesis, YMU762MA3 is equipped 32 voices with different
tones. Since the device is capable of simultaneously generating up to synchronous with the play of the FM synthesizer,
various sampled voices can be used as sound effects. Since the play data of YMU762MA3 are interpreted at anytime
through FIFO, the length of the data(playing period) is not limited, so the device can flexibly support application such as
incoming call melody music distribution service. The hardware sequencer built in this device allows playing of the
complex music without giving excessive load to the CPU of the portable telephones. Moreover, the registers of the FM
synthesizer can be operated directly for real time sound generation, allowing, for example, utilization of various sound
effects when using the game software installed in the portable telephone. YMU762 includes a speaker amplifier with high
ripple removal rate whose maximum output is 550mW (SPVDD=3.6V). The device is also equipped with conventional
function including a vibartor and a circuit for controlling LEDs synchornous with music. For the headphone, it is provided
with a stereophonic output terminal. For the purpose of enabling YMU762MA3 to demonstrate its full capablities, Yamaha
purpose to use "SMAF:Synthetic music Mobile Application Format" as a data distribution format that is compatible with
multimedia. Since the SMAF takes a structure that sets importance on the synchronization between sound and images,
various contents can be written into it including incoming call melody with words that can be used for traning karaoke,
and commercial channel that combines texts, images and sounds, and others. The hardware sequencer of YMU762MA3
directly interprets and plays blocks relevant to systhesis (playing music and reproducing ADPCM with FM synthesizer) that
are included in data distributed in SMAF.
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SGH-X100 Circuit Description
5) Memory
Signals in the OM6357 enable two memories. They use only one volt supply voltage, VDD3 in the PCF50601. This
system uses Samsung's memory, KBB06A300M-T402. It is consisted of 128M bits flash NOR memory and 128M bits
flash NAND memory and 32M bits UtRAM. It has 16 bit data line, HD[0~15] which is connected to OM6357. It has 23
it address lines, HA[1~23]. CS_NAND and NCSRAM signals is chip select. Wrting process, HWR_N is low and it
enables writing process to flash memory and SRAM. During reading process, HRD_N is low and it enables reading
process to flash memory and SRAM. Each chip select signals in the OM6357 select memory among 2 flash memory and
UtRAM. Reading or writing procedure is processed after HWR_N or HRD_N is enabled. Memories use reset, which is
VDD3 delay from PCF50601. HA[22] signal enables lower byte of SRAM and HA[22] signal enables higher byte of
SRAM.
6) OM6357
OM6357 is consisted of ARM core and DSP core. It has 8x1Kword on-chip program/data RAM, 55 Kwords on-chip
program ROM in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted of KBS,
JTAG, EMI and UART. ARM core is consisted of EMI, PIC(Programmable Interrupt Controller), reset/power/clock unit,
DMA controller, TIC(Test Interface Controller), eripheral bridge, PPI, SSI(Synchronous Serial Interface), ACC(Asynchronous
communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface.
KBIO(0:7), address lines of DSP core and HD[0~15]. HA[1~23], address lines of ARM core and HD[0~15], data lines of
ARM core are connected to memory, YMU759.
CS_NAND, NCSRAM, NCSFLASH in the ARM core are connected to each memory. HWR_N and HRD_N control the
process of memory. External IRQ(Interrupt ReQuest) signals from each units, such as, PMU need the compatible process.
KBIO[0~7] receive the status from key and RXD0/TXD for data link cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).
It has JTAG control pins(TDI/TDO/TCK) for ARM core and DSP core. It recieves 13MHz clock in CKI pin from
external TCXO. ADC(Analog to Digital Convertor) part receives the status of temperature, battery type and battery voltage.
7) TCO-9141G(26MHz)
This system uses the 26MHz TCXO, TCO-9141G, Toyocom. AFC control signal form OM6357 controls frequency from
13MHz x-tal. It generates the clock frequency. This clock is connected to UAA3536.
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3. SGH-X100 Exploded View and its Parts list
1. Cellular phone Exploded View
1
3
2
9
10
11
12
13
4
5
6
7
8
16
14
15
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