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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
SX5437M21X-X0B0
(1/4 ” VGA C IS Camera Module)
PRELIMINARY
Preliminary Specification
Revision 1.3
May. 2004
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
DOCUMENT TITLE
1/4” Optical Size 640x480(VGA) CIS Camera Module
REVISION HISTORY
Revision No. History Draft Date Remark
0.0 Initial draft Aug 14, 2003 Preliminary
0.1 Added register map and changed timing diagram Oct. 31, 2003 Preliminary
Added module dimension
0.2 Fixed some bugs Nov. 19, 2003 Preliminary
1.0 Changed I2C timing diagram Dec. 31, 2003 Preliminary
Changed product code
(S5X437CX03-20R0 Æ SX5437M21X-X0B0)
1.1 Changed the register map Jan. 7, 2004 Preliminary
1.2 Stroke out the register map
(published a new document, ‘Register Map for 437’) Apr.29, 2004 Preliminary
1.3 Modified the optical characteristics May.4, 2004 Preliminary
PRELIMINARY
This document is a general product description and is subject to change without any notice.
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
INTRODUCTION
The SX5437M21X-X0B0 is fully functional camera module with a built-in lens. A low-noise low-power color
CMOS image sensor, S5K437CX03 and an image signal processor, S5C7323X produce high-quality digital video
output including CCIR656 format with maximum 30 frames per second for full frame readout. With SAMSUNG
0.35µm CMOS image sensor process technology which is dedicated to higher sensitivity and lower-dark level
compared to standard CMOS process, and on-chip CDS and 10-bit column ADC circuit embedded, the CMOS
image sensor provides high signal-to-noise ratio with low power consumption. This compact camera system
consists of an image sensor, a signal processor and some passive components packed with IR-cut filter and lens
units. The system works with 2.8V single power supply and a clock. All the functions are controlled with control
register setting through the standard 2-wire serial interface.
FEATURES
— Optical Size: 1/4 inch format
— Unit Pixel: 5.6 µm X 5.6 µm
— Effective Resolution: 640(H) X 480(V), VGA
— 8.5mm X 9.5mm X 6.6mm module size
— 8-bit ITU.R-656 (YCrCb) Video Output
— Programmable Gamma Correction
— Auto White Balance and Auto Exposure Control
— Horizontal and/or Vertical Mirror Output
— Standby-Mode for Power Saving
— Maximum 30 Frame per Second
— Single Power Supply Voltage: 2.8V
2
— I
C Type Control Interface
— Bad Pixel Replacement Function
— Noise Canceling Function
— Shading Correction Function
PRELIMINARY
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
BLOCK DIAGRAM
GNDC
VDDCA
Lens Unit
S5K437CA03
CMOS Image Sensor
Pixel Array
640(H) X 480(V)
VDDCD
10-bit ADC
GNDI
VDDI
S5C7323X
Image Signal Processor
Pre Processor
Line Buffer
Luminance
Signal
Processor
Timing Controller
Post Processor
RISC Processor
PRELIMINARY
(AE, AWB processor)
I2C Bus
Chroma
Signal
Processor
Output
Formatter
MCLK
VSYNC
HSYNC
PCLK
DATA[0:7]
SDA
SCL
STBY
RST
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
OPTICAL CHARACTERISTICS
Characteristic Value
Effective Pixels 640 (H) X 480 (V), VGA
Pixel Size
EFL 3.385mm
F/# 2.8
Diagonal
FOV
TV-Distortion -0.33%
Relative Illumination 54.40%
MTF
Lens Construction All Plastic Lens (2P)
Focus Range
PRELIMINARY
Horizontal
Vertical
Center
0.7 Field
5.6µm (H) X 5.6µm (V), square pixel
67.87°
56.44°
43.59°
59.90% at 80 lp/mm
72.60% at 50 lp/mm
21.30% at 80 lp/mm
42.30% at 50 lp/mm
22cm ~ ∞
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
MODULE PAD DESCRIPTION
(Module pad numbers and name can be changed as customer’s request.)
Module
Pad No.
1 VDDDI 9 Power Power supply for signal processor (digital)
2 GNDI 10 Ground Ground for signal processor
3 SCL 15 In/Out I2C serial communication clock
4 SDA 16 In/Out I2C serial communication data
5 RST 11 In Reset control (active low)
6 STBY 12 In Standby control(active low)
7 MCLK 20 In Master input clock
8 VSYNC 17 Out Vertical synchronization clock
9 HSYNC 18 Out Horizontal synchronization clock
10 PCLK 19 Out Pixel output clock
11 DATA0 8 Out
12 DATA1 7 Out
13 DATA2 6 Out
14 DATA3 5 Out
15 DATA4 4 Out
16 DATA5 3 Out
17 DATA6 2 Out
18 DATA7 1 Out
19 GNDC 13 Ground Ground for sensor circuit block
20 VDDDC 9 Power Power supply for sensor digital circuit block
21 VDDAC 14 Power Power supply for sensor analog circuit block
NOTES: (*) See [Cf] p. 32.
Name
Connector
Pin No. (*)
Type Description
8-bit digital video output
PRELIMINARY
PAD 1
PAD 21
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
MAXIMUM ABSOLUTE RATINGS
Characteristic Symbol Rating Unit
Maximum supply voltage (VDDDI, VDDAC, VDDC
supply relative to GNDI, GNDC)
DC Input voltage
*Operating temperature
*Storage temperature
NOTES: *Operating temperature and *Storage temperature are not confirmed.
V
DD
-0.3 to VDD+0.3 (Max. 3.8)
V
IN
T
OPR
T
STG
-0.3 to 3.8
*-20 to +60
*-40 to +85
V
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
= -20 to +60°C, CL = 15pF)
(T
A
Characteristics Symbol Condition Min Typ Max Unit
Operating voltage
Input voltage
(1)
Input leakage
(1)
current
PRELIMINARY
V
VIH
V
I
DD
IL
IL
High level output
V
voltage
OH
Low level output
V
I
OZ
I
STB
I
DD
OL
voltage
High-Z output
(4)
leakage current
Supply current
NOTES:
1. MCLK, RSTN, STBY, SCL, and SDA pin.
2. HSYNC, VSYNC, SCL, and SDA pin
3. PCLK, YCO0 to YCO7 pin
4. SCL and SDA pin when in High-Z output state
VDDCA, VDDCD, VDDI 2.55 2.8 3.1
- 2.05 - -
VIN = VDD to VSS
IOH = -1mA
I
= -4mA
OH
IOL = 1mA
I
= 4mA
OL
V
f
= VDD
OUT
STBY = Low (active)
All input clocks = Low
= 12MHz, 15fps
MCLK
- - - 0.8
-10 - 10
(2)
(2)
(3)
(3)
0.8V
DD
- -
- -
0.2V
DD
- - 10
- - TBD
- TBD -
V
V
µA
V
µA
µA
mA
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
Sensor Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical
operating conditions follow the recommended typical values. The control registers are set to the default values.
The ambient temperature, T
Characteristic Symbol Condition Min Typ Max Unit
(3)
(1)
(2)
(4)
(5)
Saturation level
Sensitivity (G)
Dark level
Dynamic range
Signal to noise ratio
Dark signal non-uniformity
Photo response non-
(7)
uniformity
Vertical fixed pattern noise
Horizontal fixed pattern noise
NOTES:
1. Measured minimum output level at 100lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole
pixel area to eliminate the values from defective pixels.
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values
are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 10-bit ADC limits 60dB.
5. 20 log (average output level/RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure
time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median
filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from
defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
PRELIMINARY
is 25°C if not specified.)
A
V
SAT
S - 1500 - mV/lux sec
V
DARK
DR - 60 -
(6)
S/N - 40 -
DSNU
PRNU
(8)
VFPN 4 8 %
(9)
HFPN 4 8 %
850 900 - mV
TA = 40°C
- 9 18
mV/sec
= 60°C
T
A
- 50 100
dB
T
= 60°C
A
- - 100 mV/sec
- 4 8
%
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
AC Characteristics
(V
= 2.8V ± 0.25V, V
DDH
= 1.8V ± 0.15V, Ta = -20 to + 60 °C, CL = 50pF)
DDL
Characteristic Symbol Condition Min Typ Max Unit
Main input clock frequency
Output data delay time
from PCLK
Reset input pulse width
Standby input pulse width
NOTES:
1. 8-bit ADC resolution case. If 10-bit ADC resoultion is used, the frequency should be over 12MHz.
2. The period time of main input clock, MCLK.
f
MCLK
t
DLY
t
WRST
t
WSTB
Duty = 50%
T
=0~70℃
a
RSTN=low(active) 5 - -
STBYN=low(active) 4 - -
(1)
3
24.54 30 MHz
0.7 3.5 ns
(2)
T
MCLK
(V
= 2.8V ± 0.25, Ta = 0 to + 70 °C)
DDH
Characteristic Symbol Min Typ Max Unit
Output Data Delay Time, Data [0:7] T
PCLK
VCK
Tdly
PRELIMINARY
Data [0:7]
YC9~0
0.7 - 3.5 ns
DLY
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
Setup and Hold Time
(V
= 1.8V ± 0.15, Ta = 0 to + 70 °C)
DDL
Characteristic Symbol Min Typ Max Unit
Output Data Setup Time, Data [0:7] TSU 0.217 - - ns
Output Data Hold Time, Data [0:7] THD 0.217 - - ns
DATA[0:7]
CLK
50% 50%
50%
Tsu Thd
Rise and Fall Transition Time
(V
= 1.8V ± 0.15, Ta = 0 to + 70 °C)
DDL
Characteristic Symbol Min Typ Max Unit
Output Data, Data [0:7] TR - - 4.709 ns
T
PRELIMINARY
90%
90%
10% 10%
- - 4.338 ns
F
T
R
T
F
OUTPUT IMAGE MODE
No. Mode Resolution
(H X V)
1 VGA 640 X 480
10
Data rate
(PCLK)
MCLK
Zoom Frame Rate
- 30 FPS
1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
OUTPUT DATA FORMAT
YCRCB 4:2:2 FORMAT
VSYNC
HSYNC
DATA
(Mode1)
DATA
(Mode2)
DATA
(Mode3)
DATA
(Mode4)
RGB565 FORMAT
VSYNC
HSYNC
DATA
(Mode1)
R0[4:0] / G0[5:3]
DATA
(Mode2)
Y0 CB0 Y1 Y0 Y1
Y0 Y1 Y0 Y1
Y0 Y1 Y0 Y1
CB0 CR0 CB0 CR0
Y0 Y1 Y0 Y1
RG0 GB0 RG1 GB1 RG0 GB0 RG1 GB1
PRELIMINARY
G0[2:0] / B0[4:0]
GR0 BG0 GR1BG1 GR0 BG0 GR1BG1
CR0 CB0 CR0
CB0 CB0CR0 CR0
CB0 CB0 CR0 CR0
B0[4:0] / G0[5:3] G0[2: 0] / R0[4:0]
SENSOR RAW IMAGE (BAYER MOSAIC PATTERN) FORMAT
VSYNC
HSYNC
DATA
6’b000000, D0[9:8] D0[7:0]
D0H D0L D1H D1L D0H D0L D1H D1L
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
A
A
OUTPUT TIMING DIAGRAMS
HORIZONTAL TIMING
HSY NC
HSY NC
PCLK
PCLK
DAT A [ 0:7]
DAT A [ 0:7]
VGA OUTPUT TIMING
Address: FAh[3:2]=0, F8h[7:0]=03 Address: FAh[1:0]=0, F9h[7:0]=05
Address: FAh[3:2]=0, F8h[7:0]=03 Address: FAh[1:0]=0, F9h[7:0]=05
VSYNC
VSYNC
HSY NC
HSY NC
DATA [0:7]
DATA [0:7]
Address: FAh[7:6]=0, F6h[7:0]=30
Address: FAh[7:6]=0, F6h[7:0]=30
1 row
1 row
1 row
1 row
( 640 columns )
( 640 columns )
1 frame
1 frame
ddress: FAh[5:4]=2, F7h[7:0]=B0
ddress: FAh[5:4]=2, F7h[7:0]=B0
PRELIMINARY
(480 rows )
(480 rows )
2H
2H
(525 rows )
(525 rows )
NOTES:
1. Falling and rising time of HSYNC and VSYNC can be controlled by register settings.
2. Each default value of rising and falling time control registers is described in the diagram above.
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
IMAGE PROCESSING FUNCTIONS
Function Description Remarks
Defect detection and
correction
De-mosaic The sensor produces one color component from a pixel
Color correction The spectral response of image sensor is different from that
Gamma correction Gamma correction translating the linear response of the
Horizontal mirror The output image can be mirrored in horizontal direction.
Vertical mirror The output image can be mirrored in vertical direction.
Edge enhancement Enhancing the edge component provides a clear output
Auto exposure According to the incident light level, the auto exposure
PRELIMINARY
Auto white balance The auto white balance function adjusts the gain of the
Output format conversion 4 types of output format are available.
Sub-sampling Control The user can read out the pixel data in sub-sampling rate in
If enabled, the function detects the defective pixel by
comparing its level with horizontally neighboring pixels, and
replaces it with the average value of neighboring pixels.
according to Bayer color filter array. The de-mosaic function
performs color interpolation to produce all three-color
components at each pixel location.
of human eye. To match the spectral response, the sensor
output components are pivoted by user programmable 3X3
matrix production.
sensor into the non-linear characteristics of the display. Nonlinear conversion requires a piecewise linear approximation
method based on user programmable lookup table.
image. The edge enhancement function is performed through
horizontal and vertical edge detecting and enhancing.
function controls the sensor gain and effective integration time
to maintain the proper output level. Setting the control registers
can change the sensing area used in the AE algorithm.
sensor’s red and blue channels relative to the green channel,
and compensates the spectral unbalancing of the light source.
Setting the control registers can change the sensing area used
in the AWB algorithm.
(CCIR656 format, CCIR601 format, RGB format and sensor
raw image output format)
both horizontal and vertical direction. Sub-sampling can be
done in two rates: full and 1/2. The user controls the subsampling using the Sub-sampling Control Registers, subsr and
subsc. The sub-sampling is performed only in the Bayer
space.
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
I2C SERIAL INTERFACE
The I2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave
mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are opendrain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the
SCL is input only. The I
(0101101Xb) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data
transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while
SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
SDA
SCL
2
C bus interface is composed of following parts: START signal, 7-bit slave device address
A5 A4 A3 A2 A1 A0
A7 A6
A7 A6
A5 A4 A3 A2 A1 A0
SDA
SCL
START
“0” “1” “0” “1” “1” “0” “1”
BUS ADDRESS
PRELIMINARY
D7 D6
D7 D6
D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
DATA
“0”
WRITE
ACK
ACK
REGISTER ADDRESS
STOP
I2C Bus Write Format
ACK
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
A5 A4 A3 A2 A1 A0
SDA
A7 A6
A7 A6
A5 A4 A3 A2 A1 A0
SCL
SDA
SCL
SDA
START
RESTART
“0” “1” “0” “1” “1” “0” “1”
BUS ADDRESS
“0” “1” “0” “1” “1” “0” “1”
BUS ADDRESS
“0”
WRITE
“1”
READ
ACK
ACK
D7 D6
D7 D6
REGISTER ADDRESS
D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
DATA
I2C Bus Read Format
PRELIMINARY
ACK
NO ACK
STOP
SCL
tHIGH
tHD:STA tLOW
tHD:STO tHD:BUF
tHD:BYTE tHD:STA
I2C Bus Timing
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
PARAMETER Symbol Min Max Unit
SCL clock frequency fClk 400 kHZ
Low period of the SCL clock tLOW 1.3
High period of the SCL clock tHIGH 0.6
Hold time START condition tSTA 0.6
Hold time STOP condition tSTO 0.6
Bus free time between BYTE and BYTE data tBYTE 130 tMCLK
Bus free time between a STOP and START condition tBUF 130 tMCLK
NOTES:
1. tMclk : Main clock period
µsec
µsec
µsec
µsec
PRELIMINARY
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1/4 INCH VGA CIS CAMERA MODULE PRELIMINARY SX5437M21X-X0B0
MODULE DIMENSION
PRELIMINARY
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SX5437M21X-X0B0 PRELIMINARY 1/4 VGA CIS CAMERA MODULE
PRELIMINARY
©2003 Samsung Electronics
All right reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electric or mechanical, by
photocopying, recording, or otherwise, without the prior written consent of Samsung
Electronics.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
Homepage: http://www.samsungsemi.com/
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