Samsung SGH-M2310, GT-M2310 PSPEC

Specification

2-1.

GSM General Specification

GSM850 EGSM 900 DCS1800 PCS1900

Freq. Band[MHz]

Uplink/Downlink

ARFCN range 128~251

Tx/Rx spacing 45MHz 45MHz 95MHz

Mod. Bit rate/

Bit Period

Time Slot

Period/Frame Period

GSM/

GPRS

Modulation

EDGE 8PSK 8PSK 8PSK

824~849 869~894

270.833kbps

3.692us

576.9us

4.615ms

0.3GMSK 0.3GMSK 0.3G MSK

880~915 925~960

0~124 &

975~1023

270.833kbps

3.692us

576.9us

4.615ms

270.833kbps

1710~1785 1805~1880

512~885 512~810

3.692us

576.9us

4.615ms

1850~1910 1930~1990

MHz

270.833kbps

3.692us

576.9us

4.615ms

0.3GMSK

MS Power 33dBm~5dBm 33dBm~5dBm 30dBm~0dBm 30dBm~0dBm

Power Class

Sensitivity -102dBm -102dBm -100dBm -100dBm

TDMA Mux 8 8 8 8

Cell Radius 35Km 35Km 2Km 2Km

max

(

+33

dBm)

max

(

+33

dBm)

max

(

+30

dBm)

max

(

+30

dBm)

2-1

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Specification

2-2.

GSM TX power class

TX Power

control level

5 33±2

6 31±2

7 29±2

8 27±2

9 25±2

10 23±2

GSM850 GSM900

dBm

TX Power

control

level

030±3

128±3

226±3

324±3

422±3

520±3

618±3

DCS1800

dBm

TX Power

control level

PCS1900

030±3

128±3

226±3

324±3

422±3

520±3

618±3

dBm

11 21±2

12 19±2

13 17±2

14 15±2

15 13±2

16 11±3

17 9±3

18 7±3

19 5±3

dBm

716±3

814±3

912±4

10 10±4

11 8±4

12 6±4

13 4±4

14 2±5

15 0±5

dBm

716±3

814±3

912±4

10 10±4

11 8±4

12 6±4

13 4±4

14 2±5

15 0±5

dBm

2-2

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Specification

RF Circuit Description of GT-M2310

RX PART

1-1.

RX SAW FILTER+Tx Module Intergrated Circuit

RF Saw filter passes onlyaspecific frequency&controlled by signal received from the main chip. Each Mode controlled by Tx Module Circuit. The logis is like below

BAND MODE BS1 BS2 TX_EN GSM850 Rx1 GSM900 Rx2

DCS Rx3 PCS Rx4

DCXO(OSC100)

This module generates the26MHz reference clock to drive the logic and RF. After bufferingareference clock of26MHz is supplied to the other parts of the system through the transceiver pin OUT.

TRANSCEIVER(U10

The Aero4208 transceiver isacomplete RF front end for multi-band GSM and GPRS wireless communications. The receive section interfaces between the RF bandselect SAW filters and the baseband subsystem. The Aero4208 receiver leveragesaproven, digital, low-IF architecture and enablesauniversal baseband interface without the need for complex dc offset compensation. The transmit section of Aero4208 provides

complete upconversion path from the baseband subsystem

a to the power amplifier(PA) using an offset phase-locked loop(OPLL) integrated with Silicon Laboratories` patented synthesizer technology. All sensitive components, such as TX/RF VCOs, loop filters, tuning inductors, and varactors, are completely integrated intoaSingle integrated circuit. The Aero4208 transceiver includesadigitally-controlled crystal oscillator

DCXO) and completely integrates the reference oscillator and

(

varactor functionality.

000 010 110 100

2-3

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TX PART

1-2.

The transmitter is fully differential usingadirect up conversion architecture.

It consists ofasignal side band power up mixer.

Gain is controlled by6dB via3-wire serial bus programing. The fully integrated VCO and power mixer achieve LO suppression, quadrature phase error, quadrature amplitude balance and low noise floor specification. Output

1-3.

This model support GSM(GPRS)&EDGE Rx mode. And In US, This model can support only GSM850/PCS Band. Antenna sends signal to the base station&receives the signal from the base station. It isaQuad-Band Antenna.

Baseband Circuit Description of GT-M2310

matching/balun components drive a standard 50 ohms single ended load.

Overall

Specification

PCF50615(U30

2-1.

The PCF50613isahighly integrated solution for power supply generation, and battery management and charging. Eight low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system performance and long battery life.

programmable boost converter provides support for

A whileaself-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, Clock generator, aid in reducing both board area and system complexity. I2C BUS serial interface provides access to control and configuration registers. This interface givesamicroprocessor full control of the PCF5061 and enables system designers to maximize both standby and talk times. Supervisory functions. includingareset generator, an input voltage monitor, andatemperature sensor, support reliable system design. These functions work together to ensure proper system behavior during start-up or in the event ofafault condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature).

Clock Generator

The Clock Generator(CG) generates all clocks for internal and external usage. The

32.768

for the PCF50613and other circuitry.

1.8V,3.0V

such as RTC module and High Voltage Charge pump,

kHz crystal oscillator provides an accurate low clock frequency

SIMs,

2-4

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Specification

LCD Connector

2-2.

LCD is consisted of main LCD(2. SUB LCD( BACKLIGHT signal(LCD_BL_EN) enables white LED of main LCD. These signal is from UCP200.8-bit data lines(LD(0)~LD(

and commands to LCD. Data and commands use"RS" signal. If this signal is high, Inputs to LCD are commands.

If it is low, Inputs to LCD are data. Power signals for LCD are"LCD_VDD_2.9V".

Key

2-3.

This is consisted of key interface pins KEY_ROW(0:4) and KEY_COL(0:4) in PNX6508. These signals compose the matrix. Result of matrix informs the key status to key interface in the PNX6508. Power on/off k ey is separated from the matrix. So power on/off signal is connected with PCF5061 to enable PCF50613.Key LED is consisted of two white EDs(for optical waveguide).

1.07",

CSTN

64K

colors).

0",

QQVGA,

262K

colors)

transfers data

7))

IF connector(IFC

2-4.

It is VDD_IO_HIGH_2.9V, JACK_IN, TXD1, RXD1, AUX_ON, USB_DP, USB_DM, BUS_5V_IF, TXD1_J, RXD1_J, AUX_ON_J, USB_DP_J, USB_DM_J, VBUS_5V_J and GND. They connected to power supply IC, microprocessor and signal processor IC.

2-5.

This system uses Samsung's memory, KAP29VG00B-A444. This isaMulti Chip Package Memory which combines Burst Multi Bank NOR Flash Memory and and It has16bit data line, HD[0~15] which is connected to PNX6508, also has24bit address lines, HA[1~24]. There are3chip select signals, CS0n_FLASH, CS4n_NAND, and CS1n_RAM. In the Wrting process, WEn is fallen to low and it enables writing process to operate. During reading process, OEn is fallen to low and it enables reading process to operate. Each chip select signals in the PNX6508 choose different memories.

pin connector. They are designed to use VBAT, V_EXT_CHARGE_5V_IF

20-

Memory(UME200)

Mbit Synchronous Burst UtRAM.

128

500)

256

Mbit OneNAND Flash

256

Mbit Synchronous

2-5

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PNX6508(UCP

2-6.

The PNX6508 is the GSM/GPRS applications. The IC combines the high performance digital and analog baseband functionalities for mobile terminals. The PNX6508 provides support for quadruple band, multi-slot, GSM/GPRS/EDGE operation. This is achieved by integrating the RD16024 DSP and the ARM946E-S microprocessor from ARM as well as integrating DSP and system controller memory. All required A/D and D/A converters and filters foramobile terminal baseband are also integrated. Future needs and extensions are supported with the high processing power and by the prototyping features of the IC. The PNX6508 is specified to support SW development with large part of the DSP memory map implemented with SRAM-whereas stable firmware code is stored in ROM, enough memory is provided in SRAM for new firmware modules. This baseband features state of the

lowest powe r dissipation,

implemented in advanced and stable CMOS technology of NXP Semiconductors.

200) baseband processor of NXP Semiconductors for

2.5G

art circuit implementations providing

and highest integration. The IC is fully

Specification

2-6

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