Samsung SGH-I700 Block Diagram
5. SGH-i700 Block Diagrams
5-1. SGH-i700 Main Block Diagram
U 201
MA[1..12]
MD[0..15]
DD[0..15]
DA[0..12]
U 202,204
MA[2..24]
MD[0..31]
FLASH _C TRL
nRESET_IN
FLA SH MEMORY
U203
MA[10..24]
MD[0..31]
SDRAM_CTRL
SDRAM
U 603
MD[0..15]
MA[0..3]
ETHER_CTRL
JTA G _C T R L
ETHERNET
C N 601
SD_CTRL
SDCARD
C N 503, U 502
LDD[0..15]
TLCD_CTRL
LCD CON
LED601
IrDA_CTRL
IrD A
CAM_CTRL
CAM ERA
U 112
MA[1..1]
MD[0..7]
YMU_CTRL
Y M U 762 MA
MA[0..25]
MD[0..31]
FLASH _CTR L
nRESET_O UT
SDRAM_CTRL
ETHER_CTRL
JTA G _C T R L
SD_CTRL
LDD[0..15]
TLCD_CTRL
IrDA_CTRL
CAM_CTRL
YMU_CTRL
CO TULLA
3.6864M H z
O S C 101
U 108
PEXTAL
PW R_EN
O S C 102
M DPR AM _CTRL
W AKEUP_TR
PDA_ACTIVE
n34VD ET
nG P IO _RESET
nRESET_IN
n32VD ET
nPO W ER
nPO W ER _FA IL
nVDD_FAULT
SEND_END
JA C K _S
nAM P _E N
nRCV_EN
MO TOR_CTRL
SPK_SEL
AUDIO_EN
nACRESET
PENDET
SYNC
BITCLK
SDATA_IN
SDATA_OUT
PDA_D+
PDA_D-
USB_SLEEP
DETECT
UART-SEL
SYNC_DE
FF_TXD
FF_RXD
TXTAL
TEXTAL
32K H z
C_F
ID T 70V 24V L 5
U 604
PDA_D+
PDA_D-
USB_SLEEP
W M 9705EF
USB_D+
USB_D-
U SB U F 01W 6
U 602
SW ITCH
M DPR AM _CTRL
DDPRAM_CTRL
RESET SIGNAL
PO W ER Circuit
AUDIO CIRCUIT
MIC2
MIC1
RESETB CDR
PENDET
SYNC
CITCLK
SDATA_IN
SDATAOU T
DETECT
C_F
RXD_C
TXD _C
VBUS
FFTXD
FFRX D
IF CO NNECTOR
HPOUTL
U 403
LINEOUTL
Y+/VIDR
HPOUTR
LINEOUTR
Y+/VIDR
X-/VIDR
LCD
USB_D-
USB_D+
C N 605
MONOOUT
LINEINR
LINEINL
Y-/VIDR
AUTO_PW R
5-1
CDL
AND GATE
U 111
EAR 401
EAR-MIC
U 112
DDPRAM_CTRL
W AKEUP_TR
PDA_ACTIVE_O
PHO NE_ACTIVE
DSP_AB[0..8]
DSP_DB[0..15]
DSP_CTRL
TR09W QTED 17IN2B-DT
PHO NE_M IC
AOU TAP
AOU TAN
DSP_CTRL
DSP_DB[0..15]
DSP_AB[0..8]
C SP 1093
U 801
U 901C N 501
TX_EN
DD[0..15]
DA[0..22]
MEM_CTRL
DD[0..15]
DA[0..22]
MEM_CTRL
C N 605
MEMORY
C N 705
SIM_CTRL
PW R_KEEP
RTCALARM
UP_CTRL
VREF
SIM_CTRL
PW R_KEEP
RTCALARM
UP_CTRL
VREF
EN_VRF
EN_VPAC
XOEN A
U 701
VSIM
SIM_CTRL
SIM_CLK
SIM_RST
SIM_IO
VCCA
VCCB
VOSC
VRF
VPAC
VC C _1.8A
VCCD
VRTC
AUTO_PW R
SIM CON
VCCA
VCCB
VOSC
VRF
VPAC
VC C _1.8A
VCCD
VRTC
PSC 2106
EN_VRF
EN_VPAC
SERCLK
SERDAT
SERLE
SI_EN
XOEN A
SYN_EN
RXIP
RXIN
RXQP
RXQN
TXIP
TXIN
TXQ P
TXQ N
SERCLK
SERDAT
SERLE
SI_EN
XOEN A
SYN_EN
RXIP
RXIN
RXQP
RXQN
TXIP
TXIN
TXQ P
TXQ N
U 1001~1003
G SM _LN A_IN_P
DCS_LNA_IN_P
C LK 13M _R F
G SM _LN A_IN_N
DCS_LNA_IN_N
PCS_LN A_IN_P
PCS_LN A_IN_N
DPCS_PAM_IN
GSM _PAM_IN
SI_LA B
TX_BAN D_SEL
AFC
TX_PO W ER
1
TX_PO W ER
TX_BAN D_SEL
GSM_TX_EN
DCS_TX_EN
PCS_TX_EN
U1004,F1001
GSM _PAM_IN
DPCS_PAM_IN
PCS_LN A_IN_P
G S M _LN A_IN_P
DCS_LNA_IN_P
DCS_LNA_IN_N
PCS_LN A_IN_N
G S M _LN A_IN_N
ANTTX_EN
ANT1
1
PCS_TX_EN
GSM_TX_EN
DCS_TX_EN
TRANSM ITTER & RECEV IER
SAM SUNG Proprietary-Contents may change without notice
This Document can not be used without Samsung's authorization
SGH-I700 Block Diagrams
2. SGH-i700 PDA Block Diagram
SD Card
SD Card
SD Card
SD Card
SD Card
SD Card
C am era
C am era
C am era
C am era
C am era
C am era
Key Matrix
Key Matrix
Key Matrix
Key Matrix
Key Matrix
Key Matrix
W M 9705
W M 9705
W M 9705
W M 9705
G en eral P urpose I/O
G en eral P urpose I/O
RTC
RTC
OS Timer
OS Timer
PW M (2)
PW M (2)
In t.
In t.
Controller
Controller
Clocks &
Clocks &
P ow er Man.
P ow er Man.
AC97
AC97
I2C
I2C
P erip h eral Bus
P erip h eral BusP erip h eral Bus
DM A Controller and Bridge
DM A Controller and Bridge
LCD
LCD
LCD
LCD
Timing Controller
Timing Controller
Timing Controller
Timing Controller
Color or
Color or
Grayscale
Grayscale
LCD
LCD
Controller
Controller
System Bus
System Bus
Memory
Memory
Controller
Controller
Dynam ic
Dynam ic
Memory
Memory
Control
Control
Variable
Variable
Latency I/O
Latency I/O
Control
Control
SDRAM
SDRAM
SDRAM
SDRAM
Eth erN et
Eth erN et
Eth erN et
Eth erN et
Flash
Flash
Flash
Flash
Memory
Memory
Memory
Memory
UART
UART
UART
UART
IrD A
IrD A
IrD A
IrD A
USB
USB
USB
USB
PX A 255
PX A 255 PX A 255
I2S
I2S
UART1
UART1
UART2
UART2
Fast IrD A
Fast IrD A
Slow IrD A
Slow IrD A
SSP
SSP
MMC
MMC
USB
USB
Client
Client
Megacell
Megacell
3.6864
3.6864
MHz
MHz
Osc
Osc
Core
Core
32.768
32.768
KHz
KHz
Osc
Osc
PC M C IA
PC M C IA
& CF
& CF
Control
Control
Static
Static
Memory
Memory
Control
Control
JT A G
JT A G
Test & D ubugging
Test & D ubugging
Dual Port
Dual Port
Dual Port
Dual Port
Memory
Memory
Memory
Memory
Melody
Melody
Melody
Melody
JT A G
JT A G
JT A G
JT A G
5-2
SAM SUNG Proprietary-C ontents may change without notice
This Document can not be used without Samsung's authorization
5-3. SGH-i700 Phone Block Diagram
Dual Port
Dual Port
Dual Port
Dual Port
Memory
Memory
Memory
Memory
ROM
ROM
ROM
ROM
D SP 16000 CORE
D SP 16000 CORE
PM IC
PM ICPM IC
CODEC
CODEC
Auto Pow er
Auto Pow er
Auto Pow er
Auto Pow er
SIM
SIM
SIM
SIM
SGH-i700 Block Diagrams
RAM
RAM
RAM
RAM
JT A G
JT A G
JT A G
JT A G
UART
UART
UART
UART
DUAL PO RT RAM
DUAL PO RT RAM
DUAL PO RT RAM
512 * 16
512 * 16
512 * 16
IC P /IP D P
IC P /IP D P
IC P /IP D P
ARM7TDMI CORE
ARM7TDMI CORE
W M 9705
W M 9705
W M 9705
W M 9705
13 MHz
13 MHz
PAM
PAM
PAM
PAM
Osc
Osc
Si LAB
Si LAB
Si LAB
Si LAB
Diplexer
Diplexer
Diplexer
Diplexer
TRIDENT Ⅱ
TRIDENT ⅡTRIDENT Ⅱ
5-3
SAM SUNG Proprietary-C ontents may change without notice
This Document can not be used without Samsung's authorization
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