2. Circuit Description
2-1 RF Part
2-1-1 Frequency Generator
The 13MHz reference clock (VCTCXO) drives the logic and RF part. The 13 MHz reference is controlled by the
logic (10bits DAC minimum) and is kept to a frequency error less than ±0.1 ppm after synchronization with the
GSM network.
A 540 MHz oscillator is divided by 2 to generate a fixed 270 MHz VHF LO used in the TX I,Q modulator and
mixed by 270 MHz. The UHF LO for the first RX down conversion and the TX offset mixing works in
superheterodyne mode to reduce the relative bandwidth and to be able to work at a frequency greater than 1
GHz.
2-1-2 Transmitter
The baseband GSM chipset (Kernel5) generates I and Q baseband signals for the transmit vector modulator.
The modulator provides more than 40dBc of carrier and unwanted side-band rejection and produces GMSK
modulated signal, the ÔreferenceÕ signal at 270 MHz which passes to the offset phase-locked loop block (OPLL).
The OPLL consists of a down-converter, phase detector, loop filter and transmit VCO operating at the final RF
output frequency. The down converter mixes the UHF LO (eg. 1172 MHz) with the transmit VCO signal to
generate a ÔfeedbackÕ signal at 270 MHz. The ÔfeedbackÕ signal passes via a limiter to one port of the phase
detector. The GMSK ÔreferenceÕ signal from the vector modulator passes via a second limiter to the other input
port of the phase detector. The phase detector generates an error current proportional to the phase difference
between the ÔfeedbackÕ signal from the down-converter and the ÔreferenceÕ signal from the vector modulator.
This error current is filtered by a second order low-pass filter to generate an output voltage which depends on
the GMSK modulation and the desired channel frequency. This voltage controls the transmit VCO such that the
VCO output signal, centered on the correct RF channel, is frequency modulated with the original GMSK data.
The centre frequency of the transmit VCO is offset from the UHF LO frequency by 270 MHz. The OPLL acts as
a tracking narrowband band pass filter tuned to the desired channel frequency. This reduces the wideband
noise floor of the modulation and up-conversion process and provides significant filtering of spurious
products. The OPLL architecture results in a low-noise GMSK modulated signal at 902 MHz with very low
spurious content.
The RF GMSK output from the transmit VCO is fed via TX SAW filter to the RF power amplifier. The peak
output power and the profile of the transmitted burst are controlled by means of a closed feedback loop. The
RF output from the PA is sampled with a directional coupler. The sampled signal passes to an RF detector
diode whose output voltage is dependent on the incident RF level. This ÔfeedbackÕ voltage passes to the
inverting input of the loop integrator. A ÔreferenceÕ signal is generated within the baseband section under
control of the layer 1 software. The loop maintains zero difference between the ÔfeedbackÕ signal and the
ÔreferenceÕ signal. In this way, the amplitude and shape of the transmitted RF burst may be controlled by the
baseband processor. In particular, the rise and fall profiles can be controlled to meet the stringent power/time
templates and switching transient requirements of GSM 05.05.
The RF output passes to the antenna connector via an integrated TX/RX switch and lowpass filter to attenuate
the harmonics generated by the power amplifier.
Samsung Electronics 2-1
2-2 Samsung Electronics
2-2 Baseband Part
2-2-1 General Block Diagram
Circuit Description
cmd
cmd
cmd
cmd
power
clk
I,Q Rx
Vmid
I,Q Tx
RS232
3V/ 5V
add
data
add
data
audio
Earphone (Spk/Mic)
Spk/Mic
Vther.
Vcel.
dai
synth.cmd
radio.cmd
keyboard
Vib
voice data
eepdata
KERNEL
B.B. FILTER
SERIAL
EEPROM
VIBRATOR
SIM
TRANSLATOR
MEMORY
(Flash1 + SRAM)
Flash2
(Voice recognisation)
VOCODER
SIM I/F
SIM
2-1-3 Receiver
The incoming RF signal passes through the integrated lowpass filter and TX/RX switch. This is followed by a
947 MHz SAW Band Pass Filter and a bipolar low-noise amplifier (LNA). The HD155101BF includes an active
bias circuit which stabilizes the DC operating point of the LNA. The RF signal passes via a second RF SAW
filter to the first receive mixer. This mixer is implemented as a Gilbert cell within the HD155101BF. The
incoming signal at 947 MHz mixes with the UHF LO at 1172 MHz to generate a 225 MHz IF signal. The IF
signal passes from the mixer output via a 225 MHz IF SAW filter to the first IF amplifier. A further internal
Gilbert cell mixes the 225 MHz IF signal down to the 45 MHz second IF. The 45 MHz output from the second
mixer is filtered and passes to the AGC amplifier. The gain of the AGC amplifier is set by a DC control voltage
supplied by the baseband. The usable control range is in excess of 80dB. Finally, the AGC output signal at 45
MHz passes to the demodulator and is mixed down to DC to generate I and Q baseband signals. The baseband
signals pass via baseband filter to the baseband A/D converters. The remainder of the channel filtering is
performed by the baseband chipset.
(Voice recognition)
< Fig. 3 Baseband Block Diagram >
Samsung Electronics 2-3
2-2-2 ROM1 & SRAM
8M (X16) Flash ROM and 2M (X8) bit SRAM are used. Two devices are merged in one package. This device is a
combination memory organized as 524, 288 x 16 bit flash memory and 262, 144 x 8 bit static RAM in one
package.
2-2-3 ROM2
A 8M (X16) bit Flash Memory is used for the voice recognition and voice memory. This device is an 8, 388, 608
bit flash memory with batch chip erasing, sector erasing, and byte and word writing using a single 3V power
supply.
2-2-4 EEPROM
The kernel requires some external non-volatile memory to store various system parameters, such as RF control
calibrations, extra dial stores etc. A 64 K (65, 536) bit device is used. This device is internally organized 8192 x 8.
This device features a serial interface and software protocol allowing, operation on a simple, two wire bus.
2-3 SIM
2-3-1 SIM Interface
An interface is provided to a serial port controlling the SIM interface. It can support 5V and 3V SIM interface.
The hardware interface consists of SIMVCC, SIMdata I/O, SIMclk output, SIMRST output, and SIMPRES input.
The interface is controlled through TX Data, RX Data, control, and status registers. Transmit and receive data
may use a 256 byte buffer or be exchanged through single byte registers. SIMVCC may be used to control the
power supply to the SIM card.
Circuit Description