Page 1
Advanced Power MOSFET
SFF9140
FEATURES
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
175oC Operating Temperature
Extended Safe Operating Area
Lower Leakage Current : 10 µ A (Max.) @ VDS = -100V
Lower R
: 0.161 Ω (Typ.)
DS(ON)
Absolute Maximum Ratings
Characteristic Value Units Symbol
Drain-to-Source Voltage
Continuous Drain Current (TC=25oC)
Continuous Drain Current (TC=100oC)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (TC=25oC)
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, from case for 5-seconds
1/8”
T
V
DSS
I
I
DM
V
E
I
AR
E
dv/dt
P
, T
J
T
D
GS
AS
AR
D
STG
L
BV
R
DSS
DS(on)
= -100 V
= 0.2
Ω
ID = -13.2 A
TO-3PF
1
2
3
1.Gate 2. Drain 3. Source
-100
-13.2
-9.2
1
O
2
O
1
O
1
O
3
O
53
+
_
20
348
-13.2
8.0
-6.5
80
0.53
- 55 to +175
300
V
A
A
V
mJ
A
mJ
V/ns
W
W/oC
o
C
Thermal Resistance
Symbol Typ.
R
θJC
R
θJA
Characteristic Max.
Junction-to-Case
Junction-to-Ambient
Units
--
--
1.88
40
o
C/W
Page 2
SFF9140
P-CHANNEL
POWER MOSFET
Electrical Characteristics (T
Characteristic Symbol Max. Units Typ. Min. Test Condition
BV
∆ BV/∆ TJ
V
R
DSS
GS(th)
I
GSS
I
DSS
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
Q
gs
Q
gd
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
g
Gate-Source Charge
Gate-Drain( “ Miller “ ) Charge
=25oC unless otherwise specified)
C
VGS=0V,ID=-250µ A
-100
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.11
--
--
--
--
--
--
8.9
1180
240
83
14
22
45
26
43
7.4
17.8
-100
-100
1535
--
--
-4.0
100
-10
0.2
--
360
125
40
55
100
60
54
--
--
V
ID=-250µ A See Fig 7
V/oC
VDS=-5V,ID=-250µ A
V
VGS=-20V
nA
VGS=20V
VDS=-100V
µ A
VDS=-80V,TC=150oC
VGS=-10V,ID=-6.6A
Ω
Ω
VDS=-40V,ID=-6.6A
VGS=0V,VDS=-25V,f =1MHz
pF
See Fig 5
VDD=-50V,ID=-17A,
RG=12
ns
See Fig 13
VDS=-80V,VGS=-10V,
nC
ID=-17A
See Fig 6 & Fig 12
4
O
4
O
Ω
4
5
O
O
4
5
O
O
Source-Drain Diode Ratings and Characteristics
Characteristic Symbol Max. Units Typ. Min. Test Condition
I
I
SM
V
t
Q
Notes ;
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
1
O
2
L=3.0mH, IAS=-13.2A, VDD=-25V, RG=27 Ω * , Starting TJ =25oC
O
3
ISD -17A, di/dt 450A/µ s, VDD BV
O
4
Pulse Test : Pulse Width = 250µs, Duty Cycle 2%
O
5
Essentially Independent of Operating Temperature
O
Continuous Source Current
S
Pulsed-Source Current
Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
_
<
_
<
_
<
, Starting TJ =25oC
DSS
O
O
--
--
-13.2
1
--
--
4
--
--
--
135
--
0.7
_
<
-53
-4.0
--
--
A
V
ns
µ C
Integral reverse pn-diode
in the MOSFET
TJ=25oC,IS=-13.2A,VGS=0V
TJ=25oC,IF=-17A
diF/dt=100A/µ s
O
4
Page 3
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
V
GS
Top : - 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
1
- 5.5 V
10
- 5.0 V
Bottom : - 4.5 V
0
10
, Drain Current [A]
D
-I
-1
10
-VDS , Drain-Source Voltage [V]
@ Notes :
1. 250 µs Pulse Test
2. TC = 25 oC
0
10
SFF9140
1
10
175 oC
25 oC
0
10
, Drain Current [A]
D
-I
-1
1
10
10
2 4 6 8 10
- 55 oC
-VGS , Gate-Source Voltage [V]
@ Notes :
1. VGS = 0 V
2. VDS = -40 V
3. 250 µs Pulse Test
0.6
0.5
]
Ω
, [
DS(on)
R
0.4
0.3
0.2
VGS = -10 V
Drain-Source On-Resistance
0.1
0.0
0 8 16 24 32 40 48 56 64
VGS = -20 V
-ID , Drain Current [A]
2000
C
1500
1000
Capacitance [pF]
500
iss
C
oss
C
rss
0
0
10
C
= Cgs+ Cgd ( Cds= shorted )
iss
C
= Cds+ C
oss
gd
C
= C
rss
gd
1
10
-VDS , Drain-Source Voltage [V]
@ Note : TJ = 25 oC
@ Notes :
1. VGS = 0 V
2. f = 1 MHz
Fig 4. Source-Drain Diode Forward Voltage Fig 3. On-Resistance vs. Drain Current
1
10
0
10
175 oC
, Reverse Drain Current [A]
-I
DR
-1
10
25 oC
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
@ Notes :
1. VGS = 0 V
2. 250 µs Pulse Test
-VSD , Source-Drain Voltage [V]
Fig 6. Gate Charge vs. Gate-Source Voltage Fig 5. Capacitance vs. Drain-Source Voltage
10
5
, Gate-Source Voltage [V]
GS
-V
0
0 10 20 30 40 50
VDS = -20 V
VDS = -50 V
VDS = -80 V
@ Notes : ID =-17 A
QG , Total Gate Charge [nC]
Page 4
SFF9140
P-CHANNEL
POWER MOSFET
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
1.2
1.1
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Junction Temperature [oC]
Operation in This Area
is Limited by R
2
10
1
10
, Drain Current [A]
-I
D
0
10
@ Notes :
1. TC = 25 oC
2. TJ = 175 oC
3. Single Pulse
DS(on)
DC
@ Notes :
1. VGS = 0 V
2. ID = -250 µA
1 ms
10 ms
0.1 ms
2.5
2.0
1.5
, (Normalized)
1.0
DS(on)
R
0.5
Drain-Source On-Resistance
0.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
@ Notes :
1. VGS = -10 V
2. ID = -8.5 A
TJ , Junction Temperature [oC]
Fig 10. Max. Drain Current vs. Case Temperature Fig 9. Max. Safe Operating Area
15
12
9
6
, Drain Current [A]
D
-I
3
-1
10
0
10
1
10
2
10
-VDS , Drain-Source Voltage [V]
0
25 50 75 100 125 150 175
Tc , Case Temperature [oC]
Fig 11. Thermal Response
0
10
D=0.5
@ Notes :
0.2
0.1
0.05
-1
10
0.02
0.01
(t) , Thermal Response
JC
θ
Z
-2
10
-5
10
single pulse
-4
10
t1 , Square Wave Pulse Duration [sec]
1. Z
2. Duty Factor, D=t1/t
3. TJM-TC=PDM*Z
-3
10
-2
10
(t)=1.88 oC/W Max.
JC
θ
P
DM.
t
-1
10
2
(t)
JC
θ
1.
t
2.
0
10
1
10
Page 5
P-CHANNEL
POWER MOSFET
SFF9140
Fig 12. Gate Charge Test Circuit & Waveform
-10V
“ Current Regulator ”
200nF 12V
-3mA
V
R
G
50KΩ
300nF
V
GS
R
1
Current Sampling (IG)
Resistor
Fig 13. Resistive Switching Test Circuit & Waveforms
V
out
in
DUT
Same Type
as DUT
DUT
R
2
Current Sampling (ID)
Resistor
R
L
V
DD
( 0.5 rated V
V
GS
Q
-10V
V
DS
Q
gs
g
Q
gd
Charge
t
on
t
d(on)tr
)
DS
V
in
10%
90%
V
out
t
off
t
f
t
d(off)
Vary tp to obtain
required peak I
-10V
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
V
DS
D
R
G
L
I
D
V
DD
C
V
DD
E
= LL I
AS
----
1
2
ID (t)
2
AS
t
p
DSS
-------------------BV
-- V
DSS
DD
Time
V
(t)
DS
DUT
I
AS
t
p
BV
DSS
Page 6
SFF9140
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
V
DS
DUT
--
I
S
L
P-CHANNEL
POWER MOSFET
V
GS
( Driver )
I
S
( DUT )
V
DS
( DUT )
V
GS
V
GS
Driver
R
G
D =
IFM , Body Diode Forward Current
Compliment of DUT
Gate Pulse Width
-------------------------Gate Pulse Period
Body Diode
Forward Voltage Drop
(N-Channel)
• dv/dt controlled by “RG”
• IS controlled by Duty Factor “D”
Body Diode Reverse Current
I
RM
di/dt
V
f
V
DD
10V
V
DD
Body Diode Recovery dv/dt