Samsung SF700 Circuit Descriptions

SF700AT 5-1

5. Circuit Description

5-1 General

The main circuit board consists of memory, MODEM, TX- and RX-related circuitry, Speakerphone, TAD,
and the Integrated Facsimile Controller (IFC), which includes the CPU and I/O device drivers and controls
the system.

5-2 IFC

This circuit consists of the data and address bus, real time clock (RTC), image sensor, motor driver
controller, Thermal Print head controller, IFC including I/O port, and system reset circuit.

Figure 5-1: XFC-B Memory Map

CPU (Logical) Address Space

FFFFFF

F00000

0FFFFF

000000

MCSn

ROMCSn

CS0n

Not

Available

Internal

Registers

CS2n ­CS4n

CS1n

Internal

Memory

00FFFF
00FF00

00FE00
00FD00
00FC00

00E000

Reserved

Setup

Registers

Operational

Registers

CS4n
CS3n

CS2n

Reserved

Shading Inversion

DBCMC Buffer

Dither Table

Reserved

00FEFF
00FEE0

00FE80

00FE00

00FDFF
00FDC0

00FD80

00FD00

00FBFF
00FBE0

00FBD0
00FBC0

00FB80

00E000

5-2-1 Memory Map

The external memory of the CPU is divided into
32kB RAM (0000H through 8000H) and 64kB ROM
(FF0000H through FFFFFFH).

Circuit Description

5-2 SF700AT

Figure 5-2: XFC-B Hardware Interface Signals

5-2-2 Data & Address Bus Control

/RD and /WR signals are active in the low state,
with the PH2 clock in a high state, and an internal
wait state occurs in the TSTCLK (6 MHz). These
signals are sent to the /RD and /WR ports of
RAM , ROM, and the MODEM in order to read or
write data when a chip select line is active.

/CS0: RAM chip select active (low)
/ROMCS: ROM chip select active (low)
/MCS: MODEM chip select active (low)
D0 - D7: 8 bit data bus
A0 - A16: address bus

5-2-3 System Clock

The 6 MHz internal clock frequency is generated
by dividing the 12 MHz system clock from
MODEM by two inside the MODEM.

OPERATOR

PANEL

SERIAL

COMMUNICATION

PRINTER

DATA

CONTROL

AND

SENSORS

MOTOR
DRIVER

(MOTOR)

SCANNER
CONTROL

AND

PROCESSING

RTC

CRYSTAL

EXTERNAL

BUS

MODEM

GENERAL
PURPOSE

I/ 0

TXD

RXD

STB 0~3

PDAT
PCLK

PLAT

THADI

SM 0~3

MOTOR POS

START

SCLK

VIDCTL1

H/B
Vin

+Vref

-Vref

XIN

XOUT

/ROMCS
/RAMCS

/RD/WR
D0~D7

A0~A16

/RD/WR
D0~D7

A0~A4

/MCS
/MIRQ
SYSCLK

/PWRDWN
/RESET

/BATRST

IFC(XFC-B)

Circuit Description

SF700AT 5-3

Figure 5-4: Printer Timing

5-2-4 Real Time Clock (RTC)

This circuit receives clock pulses from an external

32.768 kHz crystal, which it divides into hours,

minutes, seconds, year, month, and day.
A battery maintains operation when power is off.
XFC-B can up-track 32 years, beginning with 1992.

5-2-5 Print Control

The PCLK and PDAT signals synchronise serial
print data to the TPH. PLAT latches TPH serial
print data to the TPH from a shift register through
PDAT. STB0 - STB3 enable TPH printing in four
sequential intervals.

This system has 10ms/Line printing format and
determines STB High/Low enable status
according to the STBPOL signal.

Figure 5-3: RTC Block Diagram

32768 KHz

15 BIT

PRESCALER

1Hz CO=60 CO=60 CO=24

6 BIT

SECONDS

6 BIT

MINUTES

5 BIT

HOURS

BUSY

DETECT

5 BIT

DAYS

4 BIT

MONTHS

5 BIT

YEARS

MONTH

DECODER

LEAP YEAR

DECODER

3 STATE

DRIVER

BUSY FLAG CLEAR BUSY FLAG

CO=28,29,

30,or 31

CO=12

PrintLine

(MSINT Cary-out)

Shift Data

Sh D Sh C Sh D Sh C

Print
Cmd

Shift Clk

STB0

STB1

STB2

2 DotClk Delays

5 DotClk Delays

2 DotClk Delays

STB3

Print
Cmd

Circuit Description

5-4 SF700AT

5-2-6 TPH A/D Converter

The TADC is composed of a 6 bit DAC,
comparator, filter, and 9 bit up/down counter. The
6 MSBs of the 9 bit counter generate a reference
signal to the comparator. TPH temperature is
sensed by comparing DAC output voltage to the

comparator with the thermistor
input voltage (THDI), which originates as an
output signal from the TPH. It then supplies the
proper strobe pulse to the TPH. The thermistor
input voltage (THDI) operates within a range of 1
to 4V.

Figure 5-5: Thermal ADC Block Diagram

Figure 5-6: THDI/Thermal Printer Head Connection Circuit

+5V

Ground

R28

R29

THD1

Rt (T)
Thermal

printhead
thermistor

Approximate values of R28 and R29 can be calculated
from the following formulas:

R28=0.25*[R29*rT(T1)]/[R29+Rt(T1)]
R29=[15Rt(T1)*Rt(T2)]/[Rt(T1)-16Rt(T2)]

where T1=minimum temperature, T2=maximum temperature.

THDI

DAC out

Comparator

+

6-bit DAC
1/2 bit

+

6 MSBs

9-bit up/down

Counter

Counter Clock

Data Bus

Circuit Description

SF700AT 5-5

SclkCtrlLo
SclkCtrlHi

Band Gen (8x)

Tx/Rx Control

IRQ control

SARTCmd RxShift Reg

SartlRQ

CPU Bus

SCLK

RXD

TXD

Internal Register

(SARTData)

RxBuffer

(SARTData)

TxShift Reg

5-2-7 Operation Panel Control

Communication

A Synchronous/Asynchronous
Receiver/Transmitter (SART) controls serial data
transmission between the main circuit and the
operator panel.

Figure 5-7: SART Block Diagram