Samsung SF6500 Circuit Descriptions
Samsung Electronics
5-1
5. Circuit Descriptions
5-1 Main PBA
The main board consists of CPU, System controller, Fax modem, Modem interface, Image processor,
Printing ASIC, I/O port gate array. Detail description is provided below.
5-1-1 Memory & I/O Map
BMC (Bus and Memory Controller) in the system
controller interfaces directly with CPU, ROM,
SRAM, and I/O.
Figure 5-1 Memory & I/O Map
FFFFF
F00000
EFFFF
E00000
DFFFF
C00000
BFFFF
800000
7FFFF
400000
3FFFF
000000
ON-CHIP INTERNAL REGISTER
(1 Mbyte)
I/O (1 Mbyte)
SRAM(2 Mbyte)
EPROM (4 Mbyte)
DRAM (4 Mbyte)
DRAM (4 Mbyte)
CPU
A16-A23
ADO-AD15
INT, HOLD
CAS, WEO, WE1
WEO, WE1
DRQ, DAK, TRIG
CS, RESET
PIC_ CS
PIC_ INT
PIC_ DRQ
DDIN
PIC DARK
HBE,ADS, DDIN
MCS, RD,
WEO
MIRQ
CLOCK
ADO-AD7
MA1-MA5
MODEM
ECP
ADO-AD15
MA1-MA7
SYSTEM
CONTROLLER
ADO-AD15
MA1-MA11
ADO-AD15
MA1-MA5
ADO-AD7
MA1-MA5, A22
CS
, CHSYNC
SCLK, SDATA
PRINT
ASIC
T
X
D
R
X
D
L I U
IMAGE
PROCESSOR
(SDIP III)
MEMORY
(DRAM)
5-1-2 CPU and System Controller
Figure 5-2 Hardware Interface Signals
5-1-3 System Clock
A high-speed clock and low-speed clock are used
for the system controller. The high-speed clock
39.3216 MHz is generated at external oscillator and
applied to the system controller. The CPU divides
the high-speed clock in two. They will be used for
bus clock and system clock source. The low-speed
clock is used for elapse time counter and refresh
rate counter.
5-1-4 Reset
When +5V power is higher than +4.5V (typically),
the voltage detector PST520C output goes 'High.'
The gate array generates CPU reset signal (Low) to
initialize the CPU. It causes the system controller
and peripheral device to be reset. When +5V
power drops below +4.5V, the voltage detector
PST520C output goes 'Low' and alerts main power
fail through CPU NMI (Non Maskable Interrupt)
pin and system controller PFAIL pin.
5-1-5 Bus & Memory Control
System controller BMC (Bus and Memory
Controller) interfaces directly with CPU, ROM,
SRAM, DRAM, and I/O device and generates
WAIT signal. BMC is divided into five zones by
decoding high-order address. The select signals
are SEL0 (ROM select), SEL1 (SRAM select), and
SEL2 (Gate Array select). It reads and writes data
when /RD, /WE0, /WE1, and /OE signal go
'Low'. Reading is activated always in Word-wide,
and writing is in Even byte when /WE0 goes
'Low', Odd byte when /WE1 goes 'Low' and
Word-wide when both signals go 'Low.' DRAM
access is controlled by /RAS0, /RAS1, and /CAS.
In order to access 8 Mbyte, /RAS0 is bank selected
by ASIC.
5-1-6 Scanner Control
IMAGE SENSOR
The CIS equipped with 300 dpi scanning density
and 2.5 ms for 1 line storage time.
IMAGE PROCESSOR
It supplies clock signal into CIS and performs
shading correction, AGC, edge emphasis,
correction, 64 gray levels, DMA, horizontal
reduction from 300 dpi A4 to 203 dpi A4.
SCAN MOTOR CONTROL
It supplies four phase strobes from system
controller to scan motor driver. Motor drives as
follows:
Motor Function Strobe Pulse Phase
Copy 400 pps 2-phase
Quick scan 600 pps 2-phase
Fine mode 600 pps 2-phase
Super fine mode 600 pps 1/2-phase
5-1-7 ASIC
ASIC is composed of LSU (Laser Scanning Unit)
interface, dpi conversion mode, smoothing mode,
external chip select decoder, DRAM bank select,
I/O port, print data line memory control, and
UART. In print mode, there are pass mode and
conversion mode. In pass mode, copy is made by
scanning at 300 dpi and printing at 300 dpi. In
conversion mode, it prints the received data after
406 dpi conversion through smoothing. UART is
also equipped to communicate with I-LIU chip in
9.6 k bps serial. LSU interface timing diagram is
provided below.
5-2
Samsung Electronics
Figure 5-3 LSU Interface Timing Diagram
Circuit Description
/HSYNC
/CHSYNC
SCLK
SDATA
/VDATA
/APCSH
Samsung Electronics
5-3
5-2 OPE PBA
OPE board consists of Micom, LED, key matrix, document detect sensor, and scan position sensor. When a
user presses a key, the key input data is applies to Micom through the key matrix. Micom applies the
corresponding code to the main board through UART (Universal Asynchronous Receiver Transmitter). The
main board sends out the data from Micom to LCD or LED to display the information.
5-3 Mother PBA
This board supplies power from SMPS to other boards and connects signals from the main board to HVPS,
Scan, LSU, and mech boards.
5-4 HVPS PBA
This HVPS (High Voltage Power Supply) supplies -400 VDC bias voltage into the magnet roller, -1100 VDC
charging voltage into charging roller, 4000 VDC transfering voltage and -900 VDC retransfering voltage into
the transfer roller.
5-5 Scan PBA
This board consists of Scan motor drive IC (SLA7024M), CIS, and OPE PBA interface connector. It is
connected to the main board through the mother board.
5-6 Mech PBA
This board contains the main motor driver IC (SLA7020M), speaker, solenoid, and 2nd cassette connection
switch.
5-7 MFP PBA (Option)
This board controls PC interface function, such as PC printing, scanning, and PC faxing. It controls the data
signal between PC and this machine. This board contains 40-pin connector to connect to the main board, 36pin centronics connector to connect to PC, and CL-CD1283 chip, 74LS245, 74HC00 to perform IEEE-1284
operation.
Circuit Description
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