Samsung SF5800 Circuit Descriptions

5. Circuit Description

5-1 Main PBA

5-1-1 Summary

The main circuit that consists of CPU, MFP controller (built-in 32bit RISC pr ocessor cor e : ARM7TDMI) including various I/O device drivers, system memory, scanner, printer, motor driver, PC I/F, and FA X transceiver controls the whole system. The entire structure of the main circuit is as follows:

Samsung Electronics 5-1

Fig.5-1. Entire Structure of Main Circuit for Each Key Signal

5-2 Samsung Electronics

Circuit Description

5-1-2 MFP Controller (KS32C6100 : U1)

Fig.5-2. Uart Block Diagram

SYSTEM CLOCK The internal clock frequency is 33MHz 66MHz system

clock (MCLK) supplied from the outside is used being divided inside.

DATA & ADDRESS BUS CONTROL

• /RD & /FMEM_WR, /WR /RD & /FMEM_WR signals are synchronized with MCLK(33MHz) and become LOW ACTIVE. These signals are strobe signals used to read and write data when each CHIP SELECT is connected with /RD and /WR pin of RAM, ROM, MODEM and the outside devices and becomes active. /WR is strobe signal used only write signal for SCAM image processor.

• CHIP SELECT (/SDIP_CS, /RCS0, /RCS2, /MCS, /SCS

- /SDIP_CS : SCAN MEMORY CHIP SELECT (LOW ACTIVE)

- /RCS0 : FLASH MEMORY CHIP SELECT (LOW ACTIVE)

- /RCS2 : MASK ROM CHIP SELECT (LOW ACTIVE)

- /MCS : MODEM CHIP SELECT (LOW ACTIVE)

- /SCS : SRAM CHIP SELECT (LOW ACTIVE)

• D0 - D31

- 32bit data bus

• A0 - A 2 3

- ADDRESS BUS (A22 - A23 are reserved.)

SERIAL COMMUNICATION PART U A R T (Universal Asynchronous

Receiver/Transmitter) at KS32C6100 enables the main and LIU, main and OPE to transmit serial data. The block diagram of UART i s a s follows: KS32C6100 has two UART channels. The baud rate is 9600bps.

Circuit Description

Samsung Electronics 5-3

Fig.5-3. Uart Data Format

Fig.5-4. External DMA Timing Diagram

EXTERNAL DMA

It brings data fr om an external device (SCAN_IP:U31) through EXTDMAchannel 1. When the DMA REQUEST is sent from a n external device to KS32C6100, DMA ACKNOWLEDGE signal is activated and DMA channel 1 is driven to produce CHIP SELECT and READ STROBE (/RD) and data is br ought fr om the external device. It generates the address, CHIP SELECT and WRITE STROBE (/WR) i n o r der to move this data to destination memory, a nd then stores the data. In other words, when the external DMA is requested by an external device, KS32C6100 drives internal D M A controller, D M A channel 1 is assigned to external channel, the data is sent from memory to memory or from external device to memory.

Following timing shows that when DMA REQUEST (/XDREQ) is generated, DMA ACKNOWLEDGE (/XDACK) is sent after 2 cycles and the 2 Word Data is r ead fr om external device, and is written into memory. After that if the DMA REQUEST is maintained continuously, DMA ACKNOWLEDGE signal is generated after 4 cycles and the same operation is repeated. Following diagram shows one DMA cycle. The external device (SCAN_IP) using the DMA maintains continuously DMA r equest to be activated until second DMA is performed, so one r equest brings 2 Word.

Circuit Description

5-4 Samsung Electronics

DRAM CONTROLLER

As KS32C6100 has DRAM contro ller, DRAM can be connected with external memory. The control mode of DRAM controller can access EARLY WRITE, NORMAL READ, PAGE MODE, and BYTE/HALF, and supports EDO DRAM as well as normal DRAM. DRAM READ/WRITE signals use /DWE signal to control system buses. It supports CAS BEFORE RAS for DRAM REFRESH. Connected with common /CAS(0-3), /RAS(1:0), it consists of 2 banks and each may be connected with up to 2M - 8M halfword, t h e default setting of this system is 8MB. The field of DRAM is in figure 5-1 (Entire Str uctur e of Main Circuit for Each Key Signal), r elated timing diagram is in figure 5-4.

TC (REAL TIME CLOCK)

R TC circuit maintains curr ent time information, and it operates in both primary power mode and battery back-up mode. As RTC does not in MFP contr oller, R TC IC is needed separately. This cir cuit (R TC-4513) receives clock source from an internal 32.768 kHz crystal, and divides it into hours, minutes, seconds, year, month, and day. RTC_EN, DATA and CLK control the R TC IC. RTC_EN is CHIP SELECT signal, DATAis bidirectional signal and used to select mode, write addre ss, read/write data. CLK reads or output data in rising edge.

PARALLEL PORT INTERFACE

KS32C6100 has parallel port interface enabling parallel interface with PC. This part connected with the computer through the centr onics connector makes possible parallel interface with the computer. It generates control signal and consists of /ERROR, PE, BUSY, /ACK, SLCT, /INIT, /SLCTIN, /AUTOFD, and /STB. Data is transmitted according to the standard of IEEE P1284 (http://www.fapo.com/ieee 1284.html). The controller supports compatibility mode which is the traditional way to transmit print data, nibble mode (4bit data) to upload data to the computer, and ECP (Extended Capabilities Port: 8bit data transmission) duplex high-speed transmission with the computer. Compatibility mode, called as Centronics mode, is protocol which used to transmit data from PC to printer. ECP mode is protocol which supports rapid bidir ectional communication with input/output device such as printer, scanner. ECP mode supports 2 cycles for bidir ectional communication: Data cycle and Command cycle. Command cycle is formed runlength count and channel addressing. RLE (Run Length Encoding) mode can compress data, and be used to transmit raster image to printer or scanner.

This system uses RLE method for high-speed transmission. It enables data to be printed, uploaded, and downloaded. It also monitors system.

Circuit Description

Fig.5-5 Compatibility Hardware handshaking Timing

1. Write the data to the data register.

2. Program reads the status register to check that the printer is not BUSY.

3. If not BUSY, then Write to the Control Register to assert the STROBE line.

4. Write to the Control register to de-assert the STROBE line.

Fig.5-6 ECP Hardware Handshaking Timing (forward)

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD.

2. Host asserts nSTROBE low to indicate valid data.

3. Peripheral acknowledges host by setting BUSY high.

4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral.

5. Peripheral sets BUSY low to indicate that it is ready for the next byte.

6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low.

Samsung Electronics 5-5

Circuit Description

Fig.5-7 ECP Hardware Handshaking Timing (reverse)

1. The host request a reverse channel transfer by setting nINIT low.

2. The peripheral signals that it is OK to proceed by setting PE low.

3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high.

4. Peripheral asserts nACK low to indicate valid data.

5. Host acknowledges by setting nAUTOFD high.

6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host.

7. Host sets nAUTOFD low to indicate that it is ready for the next byte.

8. The cycle repeats, but this time it is a command cycle because BUSY is low.

5-6 Samsung Electronics

Circuit Description

Samsung Electronics 5-7

ENGINE CONTROLLER

• Message Communication The print interface uses CnPMSG and CnEMSG to transmit and receive 8-bit message, CnPBSY and CnEBSY to indicate the dir ection of data transfer and COMCLK to pace data transmissions. PIFC does not employ handshaking, but asserts CnPBSY and CnEBSY befor e the actual data transmission to provide sufficient time for the logic to pr epare for the subsequent data. COMCLK remains inactive until either CnPBSY o r CnEBSY is asserted and then goes thr ough eight periods for 8-bit data transmission or reception.

Thre e r egisters, TBR (Transmit Buffer Register), RBR (Receive Buffer Register), ar e used for message communication. The TBR and RBR contain the 8-bit command to be transmitted to the printer engine through the CnEMSG pin and the 8-bit engine message received for the printer engine thr ough the Cnemsg pin, respectively. The CMOD contain a transmit enable bit (TX) to make CnPSBY signal active, a r ead-only status bit (RX) to indicate the Cnebsy signal status and 5-bit prescaler value used to generate COMCLK clock. In message reception, the RX bit is clear ed when a low-to-high transition occurs on CnEBSY , and at the meantime an interr upt signal INT_BUSY is posted to indicate that one-byte engine message has been received by PIFC.

Circuit Description

5-8 Samsung Electronics

+ 17 hidden pages