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4.4 PBA CIRCUIT DESCRIPTIONS
4.4.1 MAIN PBA
The Main PBA consists of six functional blocks. The functional blocks are:
•CPU
•Fax engine
•Memory
•Image processing
•AFE
•Telephone circuit
CPU
NS32FV164 is used as the control processor. This CPU executes the program instructions stored two 27c020
(256 kbyte x 2) EEPROMs and controls all system tasks that are to be preformed. The CPU stores the System
in 32 kbyte of SRAM. CPU clock is generated by the fax engine.
MEMORY
CPU uses two 256 kbyte EPROM (27C020), one 32 kbyte SRAM (62256) for system data and two 512 kbyte
DRAM (48C512X4) for working memory and pixel data.
FAX ENGINE
The uses NS32FX200-25 as a fax engine. It includes the bus controller, DMA controller, interrupt controller,
UART, general purpose 1/0 port, RTC, sigma delta codes, and DRAM controller. It also generates various
system control signal and 2 divided system clocks from an oscillator.
AS modem facility, It has modulator/demodulator for G3 mode, DTMF tone generator and tone detector.
The Msys5600/5700 can operate at speeds of 14000, 12000, 9600, 7200, 4800, 2400, and 300 bps. The
NS32FX200 satisfies the telecommunications requirements specified in CCITT recommendations V.17, V.29,
V.27ter, T.30, and T.4.
Its power is provided by a battery back-up circuit to retain RTC data.
IMAGE PROCESSING
Image processing consists of the image processor (STL7057) and SRAM (6264, 8kbyte). It has the following
functional blocks:
•A/D converter
•Edge emphasis
•Gray scale (error diffusion method
•AGC/ABC
•Generation of the CIS drive clock
A 8 MHz system clock is supplied.
64 kbyte
64 kbyte
256 kbyte
1 Mbyte
Working memory
ECM memory
OGM memory
Bit map memory
Pixel memory
Pixel memory
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