Samsung SF-530 Schematics Diagram

Repair Manual

1. Block Diagram

2. Connection Diagram

3. Circuit Description

4. Schematic Diagrams

CONTENTS

SAMSUNG FACSIMILE

SF-530/531P

Electronics

Samsung Electronics Digital Printing CS Group

This manual is made and

described centering around

circuit diagram

and circuit description needed

in the repair center

in the form of appendix.

SAMSUNG

1-1

Samsung Electronics

BLOCK DIAGRAM

Repair Manual

1. Block Diagram

MA I N

POWER

CORD

KS32C65100

ARM7T

GEU

P1284

ITU

I/OI/F

CACHE( 6 K)

DMAC

PVC

UART* 2

MEM OR Y I / F

MODEM

DRAM

(8MB)

CI S I NTERFACE

PART

HOST

)

CI S

CENTRONI CS

USB

TX MOTOR

DRI VER

MOTOR

RTC

Bac k- up Par t

LI U

MO DE M &

EXT_PHONE

SEPERAT ING

PART

600/ /600

Tx: Rx

TRANSFORMER

EXTERNAL

PHONE

DETECT I ON

PART

EXTERNAL

PHONE

LI NE

HANDSET

600/ /600

Tx: Rx

TRANSFORMER

FLASH

MEMORY

(2MB)

+5V

UART

-5V

SCAN Boar d

MI COM

- LCD Dr iv e

- Key Scan

OPE

LCD

DOC

SEN SOR

SMPS

HVPS

+24V

MOTOR

OLENOIDE

ENGINE

B'D

FAN

OPC_FUSE

Audio Part

EXIT

SEN SOR

MHV

OPC GND

SUPPLY

DEV

THV

UNICON

(USB IC)

Note. -. SF-530 : Fax Function Only

-. SF-531P : Printer Function with Fax

*Note

33600 bps

2-1

Samsung Electronics

CONNECTION DIAGRAM

Repair Manual

2. Connection Diagr am

5GND5 4+5V 3OPE_TXD 2OPE_RST 1OPERXD

LCD

CN1

OP E

CN3

SCAN B’ D

8 +

7 +

6 S

T A

5 +

4 S

T *

3 S

T *

2 S

T B

1 G

0 O

E R

9 G

D 5

8 O

E T

7 O

E R S

6 G

D 5

5 +

4 C

S S

3 C

S L

2 C

S S

1 C

S C

CN1

214365871091211141316151817

CN1 6

1 2 34 5 678 91011 12131415161718

HOST

(PC)

IEEE1284 I/F (36PIN)

USB PORT (4PIN)

CN2

CN19

1+5V 2/PEMPTY 3/FEED 4GND5

SENSOR

B’ D

COVER SWITCH

1+24V 2+24VS

HVPS

CN1

1+24VS1 2GND24 3THVPWM 4/THV_EA 5THVREAD 6MHVPWM 7BIASPWM 8+5V 9GND

CN8 - 1

THER-MISTOR

1THERM_A 2THERM_B

CN7

CN1 8

CN15- 1

CN1 3- 1

CN7

CN9

ENG INE

B’d

LSU

LD DIODE

POLY GO N MOT OR

1+24VS 2GND24 3PMOTOR 4/LREADY 5EXTCLK

6/USYNC 7+5V 8CND5

9/LD_ON 10 VD0 11 / APC_SH

12 SLUTCH 13 FAN 14 PTL 15 DEV_FUSE 16 / NEW_DEVE 17 / EGMOT_A0 18 / EGMOT_ A1 19 EGMOT_PHA 20 / EGMOT_B0 21 / EGMOT_B1 22 GND5 23 +5V 24 EGMOT_PHA 25 +24VS 26 +24VS 27 GND24 28 GND24

CN1 2

SPK

1SPKOUT 2AGND

4 M

M T

3 M

M T

2 A

G N D

1 N

0 M

M R

9 /

T P

8 C

M L

7 R E

M O T

6 C

5 /

4 /

3 +

2 G N D 5

1 /

R I

CN1 4

1+24VS 2FUSER_ON 3+5V 4/EXIT 5+5V 6GND5 7+5V 8GND5 9-5V 10 GND5 11 24V 12 GND24 13 24V 14 GND24 15 24V 16 GND24

CN5 03

SMPS

Heat Lamp

(Fuser)

HOT Neutral

CLINE

MAIN B’d

1GND5 2+5V 3V0 4LCD_RS 5LCD_RW 6LCD_F 7LED_0 8LED_1 9LED_2 10 LED_3 11 LED_4 12 LED_5 13 LED_6 14 LED_7

HOOK B’d CN2 CN1

CN3

MJ1

1LINE_2 2LINE_3 3LINR_4 4LINR_5 5LINR_6

6EXT_3 7EXT_4 8EXT_5

1MIC1 2 RCV3 3MIC2 4 RCV1 5 HOOK2 6 HOOK2 _NC 7 HOOK2 _NO

10 HOOK1 11 HOOK1_NO 12 HOOK1_NC

LIU B’d

MJ1

1 CIS_SIG 2 GND 3 +5V 4 GND 5 GND 6 START PULSE 7 GND 8 CIS MAIN CLOCK 9 LED B 10 LED G 11 LED R 12 V LED

1 CIS_SIG 2 GND 3 +5V 4 CIS_SI 5 CIS_CLK 6 CIS_LED 7 +24V

200 DPI 300 DPI

1 +24 2 +24 3 SCNMOT_A 4 SCNMOT_*A 5 SCNMOT_B 6 SCNMOT_*B

SCAN

MOTOR

CN2 CN4

CIS

3-1

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3. Circuit Description

3-1 Main PBA

3-1-1 Summary

The main circuit that consists of CPU, MFP controller including various I/O device drivers, system memory, scanner, printer, motor driver, PC I/F, and FAX transceiver controls the whole system. The entire structure of the main circuit is as follows:

I/O Ports

Controller

Scan Image &

Scan Motor

Controller

Ink Head

Controller

DMA

Controller

Parallel

Port

Interface

Video Data

Controller

UART/

Serial I/O

LSU

Control

PWM &

Gen. Timer

System Bus Controller Bus Arbitration

Bus Interface

ROM/SRAM/DRAM Controller

System Manager

Bus Router

PLL & Clock

Save

Interrupt

Controller

A/D

Converter

Derasterizer

Carrier Motor

Control

Position &

Fire Control

Paper Motor

Control

Real Time

Clock

Watch Dog

Timer

CPU

(ARM7TDMI)

I/D Cache

(2-KB)

LBUS

ADDR

DATA

CNTR

3-2

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-1-2 Circuit Operation

• CLOCK

1) System Clock Device Oscillator Frequency 9.500132 MHz KS32C65100 RISC PROCESSOR: drives PLL internally and uses 37.17 MHz.

2) Video Clock Device Oscillator Frequency 28.7448 MHz

3) USB Clock Device Oscillator Frequency 48 MHz±%

3-3

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

• KS32C65100 MICROPROCESSOR

1) KS32C65100 MICROPROCESSOR PIN & INTERFACE

Signal Pin No. I/O Type Description

OSCI 184 I7 KS32C65100 master clock in put.

OSCO 185 O7 KS32C65100 master clock outpu t.

PLL_FILTER 183 I5 PLL filter

nRESET 182 I4

Not reset. nRESET is the global reset input for the KS32C65100. For a system reset, nRESET must be held to low level for at least 65 machine cycles.

nSLCTIN/GIP[16] 152 I1

Not select information. This input signal is used by parallel port interface to request 'on-line' status information.

nSTROBE 151 I1

Not strobe. The nSTROBE input indicates when valid data is on parallel port data bus, PPD[7:0]

nAUTOFD/GIP[17] 154 I1

Not auto feed. The nAUTOFD input indicates whether data on the parallel port data bus, PPD[7:0], is an auto feed command. Otherwise, the bus signals are interpreted as data only.

nINIT/GIP[15] 153 I1

Not initialization. The nINIT input signal initializes the parallel port's input con trol.

nACK 159 I1

Not parallel port acknowledg e. The nACK output signal is issued whenever a transfer on the parallel port data bus is completed.

BUSY 158 O1

Parallel port busy. The BUSY output signal indicates that the KS32C65100 parallel port is currently busy.

SELECT 156 O1

Parallel port select. The SELECT output signal indicates whether the device connected to the KS32C65100 parallel port is 'on-line' or 'off-line'.

PERROR 157 O1

Parallel port paper error. PERROR output indicates that a problem exists with the paper in the ink-jet printer. It could indicate that the printer has a paper jam or that the printer isoutofpaper.

nFAULT 155 O1

Not fa ult. The nFAULT output indicates that an error condition exists with the printer. This signal can be used to indicate that the printer is out of ink or to inform the user that the printer is not turned on.

PPD[7:0] 142~149 I/O2

arallel port data bus. This 8-bit, tri-state bus is used to exchange data between the KS32C6510 0 and an external host(peripheral).

SAVRT 2 I6 Top reference voltage for IP ADC

SAIN 3 I6 Analog input for IP ADC

SAVRB 4 I6 Bottom reference voltage for IP ADC

3-4

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Signal Pin No. I/O Type Description

CIS_CLK 6 O1 CIS shift clock CIS_SI 7 O1 CIS latch signal PHA_IA0 164 O1 Line feed motor phase signal A PHA_IA1 165 O1 Line feed motor phase signal AZ PHB_IB0 167 O1 Line feed motor phase signal B PHB_IB1 168 O1 Line feed motor phase signal BZ LF_PH0/GOPA[21] 163 O1 Line feed motor control signal 0 LF_PH1/GOPA[22] 166 O1 Line feed motor control signal 1 CR_PHA/GOPA[23] 110 O1 Direction control line for phase A CR_PHB/GOPA[24] 113 O1 Direction control line for phase B CRIA0/GOPA[25] 109 O1 Current control line 0 for phase A CRIA1/GOPA[26] 111 O1 Current control line 1 for phase A CRIB0/GOPA[27] 112 O1 Current control line 0 for phase B CRIB1/GOPA[28] 114 O1 Current control line 1 for phase B CHX/GIP[8] 116 I3 Encode sensor CHY/GIP[9] 117 I3 Encode sensor

ADDR[21:0]

77~80, 82~88, 90~100

Address bus. The 22bit address bus, ADDR[21:0], covers the full 4M half-words address range of each ROM/SRAM, DRAM, and external I/O bank

DATA[15:0]

59~66, 68~75

I/O3 Exte rnal bi-directional 16-bit data bus.

nRAS[1:0] 52,53 O1

Not row address strobe for DRAM. The KS32C65100 supports up to two DRAM b anks. One nRAS output is provided for each bank.

nCAS[1:0] 54,55 O1

Not column address strobe for DRAM. The two nCAS outputs indicate the byte selections whenever a DRAM bank is accessed.

nOE 56 O1

Not output e nable. Whenever a memory access occurs, the nOE output controls the output enable port of the specific memory device.

nWE 57 O6

Not write enable. Whene ver a memory access occurs, the nWE outpu t con trols the write enable port of the specific memory device.

nPHGA[13:1]/ GOPB[12:0]

16~24,

26~29

O1 Gate control line for print head.

PHOE[16:1]/ GIOP[26:11]

31~38,

40~47

I/O1 Drain control line for print head.

3-5

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Signal Pin No. I/O Type Description

RXD0/GIP[0] 194 I1

Receive data input for the UART0. RXD0 is the UART0 channel's input signal for receiving serial data.

RXD1/GIP[1] 192 I1

Receive data input for the UART1. RXD1 is the UART1 channel's input signal for receiving serial data.

RXD2/GIP[2] 190 I1

Receive data input for the UART2. RXD2 is the UART2

channel's input signal for receiving serial data. nEINT0/GIP[3] 8 I3 External interrupt request input nEINT0. nEINT1/GIP[4] 9 I3 External interrupt request input nEINT1. nEINT2/GIP[5] 10 I3 External interrupt request input nEINT2. nXDREQ/GIP[6] 199 I3 External DMA request.

TXD0/GOPA[0] 193 O1

Transmit data output for the UART0. TXD0 is the UART0

channel's o utput for transmitting serial data.

TXD1/GOPA[1] 191 O1

Transmit data output for the UART1. TXD1 is the UART1

channel's o utput for transmitting serial data.

TXD2/GOPA[2] 189 O1

Transmit data output for the UART2. TXD2 is the UART2

channel's o utput for transmitting serial data.

nXDACK/GOPA[5] 200 O1

Exte rnal DMA acknowledge. This active low output signal is

generated whenever a DMA transfer is completed. TONEOUT/GOPA[3] 188 O1 Tone generator output. nWDTO/GOPA[4] 187 P3 Reset out by watch dog timer. nIOWR/GOPA[10] 161 O1 External output write strobe nIORD/GOPA[9] 162 O1 External output read strobe CLKOUT/GOPA[6] 180 O1 Clock for external chip nECS2/GOPA[8] 14 O1 External memory chip select 2. TCK 132 I2 JTAG TCK interface in MDS mode. TMS 135 I2 JTAGTMSinterfaceinMDSmode. TDI 133 I2 JTAG TDI interface in MDS mode. nTRST 136 I2 JTAG nTRST interface in MDS mode. TDO 134 O1 JTAG TDO interface in MDS mode.

GIOP[10:0]

137~140,

173~179

I/O4 General I/O port.

TEST0 169 I2

Test 0 pin. At normal operation this pin must be connected

to GND.

TEST1 170 I2

Test 1 pin. At normal operation this pin must be connected

to GND.

TEST2 171 I2

Test 2 pin. At normal operation this pin must be connected

to GND.

3-6

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Signal Pin N o. I/O Type Description

nECS[1:0] 12,13 O1

Not external chip select. Three I/O banks are provided for external memory-mapped I/O operations. Each I/O bank contains up to 4M half-word. The nECS signals indicate that an external I/O bank is selected.

nRCS[2] 51 O2

Not ROM/SRAM chip select. The KS32C65100 can access

up to three external ROM/SRAM banks. nRCS[0]

corresponds to ROM/SRAM bank 0, nRCS[1] to bank 1, and

nRCS[2] to bank 2. By controlling the nRCS signals, CPU

addresses can be mapped into the physical memory banks.

nRCS[1]/GOPA[7] 50 O1

nRCS[0] 49 O1

SC_CONPHA/ GOPA[19]

102 O1 Scan motor control/Bi-phase

SC_CONPHB/ GOPA[20]

105 O1 Scan motor control/Bi-phase

SC_CUR[3:0]

103, 104,

106, 107

O1 Scan motor bi-current/un i-phase

PWMO[2:0]/ GOPA[13:11]

118~120 O1 PWM out signal

VDO2/GOPA[29] 121 O4 Video out from PIFC VDO1/GOPA[14] 122 O5 Video out from LSU control LSU_CLK/

GOPA[15]

123 O1 Clock for LSU motor

nHSYNC1/GIP[10] 125 I1 HSYNC1 nLREADY/GIP[11] 126 I1 LSU ready nHSYNC2/GIP[12] 127 I1 HSYNC2 VDI/GIP[13] 128 I2 Video data input from RET VCLK/GIP[14] 129 I2 External video clock nEXTWAIT/G IP[7] 130 I3 External wait RTCXIN 202 I7 RTC oscillator clock input. RTCXOUT 203 O7 RTC oscillator clock output.

SLED[2:0]/ GOPA[18:16]

196~198 O1 CIS LED signals

GAVRT 20 5 I5 Top reference voltage for general ADC GAIN[2:0] 206~208 I5 Analog inputs for general ADC RTC_VDD 201 RTC VDD.

Signal Pin No. I/O Type Description

VDD_PLL 18 6 PLL power (3.3V). SAVDD 1 Analog power for scan ADC and general ADC (3.3V). SAVSS 5 Scan ADC gr ound. GAVSS 204 General ADC gr ound

3VDD

15, 30, 81 ,

115, 131,

160

3.3V internal power. Externally connected to the 3.3V regulator.

5VDD

48, 67, 89 ,

141, 195

5V I/O power. Externally connected to the VCC board plane.

VSS

11, 25, 39 ,

58, 76, 1 01,

108, 124, 150, 172,

181

System ground. Externally connected to the ground board plane.

3-7

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-1-3 PROGRAM ROM (FLASH MEMORY)

1) DEVICE TYPE No. AM29F800B CAPACITY 2 Mbit (512K * 16bit * 2)

2) PROGRAMMING BEFORE ASS’Y EPROM PROGRAMMER or PROGRAMMING at the factory AFTER ASS’Y DOWNLOAD from PC

3-1-4 DRAM CONTROL

1) DEVICE TYPE NO. K4E641611D-TC50(EDO Type) CAPACITY 64 Mbit (4M * 16bit)

2) OPERATING PRINCIPLE DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores data white the

CPU processes data. The address to read and write the data is specified by RAS SIGNAL and CAS SIGNAL. DRAMWE*SIGNAL is activated when writing data and DRAMOE*SIGNAL, when reading.

3-1-5 USB (Universal Serial Bus)

SAMSUNG’S UNICON is used as the interface IC and 48MHz clock is used. When the data is received through the USB port, USBIRQ SIGNAL is activated to send interrupt to CPU, then it directly sends the data to DRAM by USB_CS SIGNAL through D(0;7).

3-1-6 Modem and TX-and RX Related Circuits

MODEM

The Conexant™ FM336 modem is a V.34 half-duplex modem that supports Group 3 facsimile send and receive speeds up to 33600 bps using the V.34 half-duplex mode. Using a V.34 technique to optimize modem configuration for line conditions, the modem connects at the optimal selected data rate that the channel can support from 33600 bps to 2400 bps.

The modem can operate over the public switched telephone network (PSTN) through a line terminator provided by a Data Access rrangement (DAA). The modem satisfies the requirements specified inITU-T recommendations V.34, V.17, V.29, V.27 ter, V.23, V.21, and meets the binary signal ingrequirements of V.8 and T.30. Internal HDLC support eliminates the need for an external serial input/output (SIO) device in the DTE for products incorporating error detection and T.30 protocol. The modem can perform HDLC framing per T.30 at all data speeds. CRC generation/checking along with zero insertion/deletion enhances DLC/HDLC frame operations. An FSK flag pattern detector facilitates FSK detection during high speed reception.The modem features a programmable DTMF transmitter/receiver and three programmable tone detectors which operate in the tone mode.

The modem offers lower power consumption and small size to allow the design of compact system enclosures for use in industrial, office, and home environments.The modem is available in a 100-pin PQFPpackage.

3-8

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

FM336 FEATURES

• 2-wire half

- duplex fax modem modes with send and receive data rates up to 33600 bps.

- V.34, V.17, V.29, V.27 ter, and V.21 channel 2

- Short train option in V.17 and V.27 ter

• 2-wire full

- duplex data modem modes

- V.21, V.23 (75 bps TX/1200 bps RX or 1200 bps TX/ 75 bps RX)

• PSTN session starting

- V.8 signaling

• HDLC support at all speeds

- Flag generation, 0 bit stuffing, ITU CRC

- 16 or CRC

- 32 calculation and generation

- Flag detection, 0 bit deletion, ITU CRC

- 16 or CRC

- 32 check sum error detection

FSK flag pattern detection during high speed receiving

• Tone modes and features

- Programmable single or dual tone generation

- DTMF receive

- Tone detection with three programmable tone detectors

• Serial synchronous data

• Parallel synchronous data

• Automatic Rate Adaptation (ARA) in V.34 Half-Duplex

• TTL and CMOS compatible DTE interface

- ITU-T V.24 (EIA/TIA-232-E) (data/control)

- Microprocessor bus (data/configuration/control)

• Receive dynamic range: 0 dBm to –43 dBm for V.17, V.33, V.29, V.27terand V.21, –9 dBm to –43 dBm for V.34 half-duplex

• Programmable RLSD turn-on and turn-off thresholds

• Programmable transmit level: 0 to -15 dBm

• Adjustable speaker output to monitor received signal

• DMA support interrupt lines

• Two 16-byte FIFO data buffers for burst data transfer with extension up to 255 bytes

• NRZI encoding/decoding

• Diagnostic capability

• +3.3V operation with +5V tolerant inputs

• +5V analog signal interface

• Typical power consumption:- Sleep mode: 20 mW

- Normal mode: 250 mWa

• 100-pin PQFP package

3-9

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Signaling Rates, and Data Rates

Configuration

Modulation

Carrier Frequency

(Hz) –0.01%

Data Rate (bps)

–0.01%

Symbol Rate

(Symbols/Sec.)

Bits/Symbol -

Data

Bits/Symbol -

TCM

Constellation

Points

V.34 33600 TCM TCM Note 2 33600 3429 only Note 2 Note 2 Note 2 V.34 31200 TCM TCM Note 2 31200 320 0 mi n Note 2 Note 2 Note 2 V.34 28800 TCM TCM Note 2 28800 300 0 mi n Note 2 Note 2 Note 2 V.34 26400 TCM TCM Note 2 26400 280 0 mi n Note 2 Note 2 Note 2 V.34 24000 TCM TCM Note 2 24000 280 0 mi n Note 2 Note 2 Note 2 V.34 21600 TCM TCM Note 2 21600 240 0 mi n Note 2 Note 2 Note 2 V.34 19200 TCM TCM Note 2 19200 2400 to 3429 Note 2 Note 2 Note 2 V.34 16800 TCM TCM Note 2 16800 2400 to 3429 Note 2 Note 2 Note 2 V.34 14400 TCM TCM Note 2 14400 2400 to 3429 Note 2 Note 2 Note 2 V.34 12000 TCM TCM Note 2 12000 2400 to 3429 Note 2 Note 2 Note 2 V.34 9600 TCM TCM Note 2 9600 2400 to 3429 Note 2 Note 2 Note 2 V.34 7200 TCM TCM Note 2 7200 2400 to 3429 Note 2 Note 2 Note 2 V.34 4800 TCM TCM Note 2 4800 2400 to 3429 Note 2 Note 2 Note 2 V.34 2400 TCM TCM Note 2 2400 2400 only Note 2 Note 2 Note 2 V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 — V.21 FSK 1080/1750 Up to300 300 1 0 — V.17 14400 TCM TCM 1800 14400 2400 6 1 128 V.17 12000 TCM TCM 1800 12000 2400 5 1 64 V.17 9600 TCM TCM 1800 9600 2400 4 1 32 V.17 7200 TCM TCM 1800 7200 2400 3 1 16 V.29 9600 QAM 1700 9600 2400 4 0 16 V.29 7200 QAM 1700 7200 2400 3 0 8 V.29 4800 QAM 1700 4800 2400 2 0 4 V.27 ter 4800 DPSK 1800 4800 1600 3 0 8 V.27 ter 2400 DPSK 1800 2400 1200 2 0 4 V.21 Channel 2 FSK 1750 300 300 1 0 —

Notes:

1. Modulation legend: TCM:Trellis-Coded Mod ulati on QAM: Quadrature Amplitude Modulation FSK:Frequency Shift Keying DPSK: Differential Phase Shift Keying

2. Adaptive; established during handshake: Carrier Frequency (H z)

Symbol Rate (Baud) V.34 Low Carrier V.34 High Carrier 2400 1600 1800

2800 1680 1867 3000 1800 2000 3200 1829 1920 3429 1959 1959

3-10

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

V.24

Interface

Host

Processor

FM336

Modem

Crystal

Power Supply

Speaker

Amplifier

Optional

Eye Pattern

Generator

Line

Interface

/RTS

TXD

/CTS

TDCLK

XTCLK

/RLSD

RXD

/RDCLK

/DTR

/RI*

/DSR**

/RD

/CS

/WR

D[7:0]

RS[4:0]

IRQ

/RESET

TXRQ*

RXRQ**

XTL0

XTLI

TXA1

RIN

TXA2

/TALK

RINGD

EYEXY

EYESYNC

EYECLK

+5V

AGND DGND

SPKR

* Selectable; TXRQ output replaces /RI output. ** Selectable; RXRQ output replaces /DSR output.

1176DG F2-1

TIP

RING

telephone line

+3.3V

Oscillator

CLKIN

Modem Functions Interface Signals

3-11

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Pin Signal Label

I/O Type

Interface

Pin Signal Label

I/O Type

Interface

1 RESERVED - - 51 RESERVED - 2 RS2 IA HOST Interface 52 VSUB GND 3 RS3 IA HOST Interface 53 VSS GND 4 RS4 IA HOST Interface 54 NC - NC 5 /CS IA HOST Interface 55 NC - NC 6 /WR IA HOST Interface 56 Sleep MI Modem Interconnect 7 /RD IA HOST Interface 57 VDD1 PWR 8 /RDCLK OA DTE Serial Interface 58 RESERVED - -

9 /RLSD OA DTE Serial Interface 59 RESERVED - 10 TDCLK OA DTE Serial Interface 60 NC - NC 11 TXD IA DTE Serial Interface 61 SR1 IO MI Mod em Inter co nne ct 12 /CTS OA DTE Serial Interface 62 VCORE PWR 13 VDD1 PWR - 63 VDD1 PWR 14 RESERVED - - 64 XTCLK IA DTE Serial Interface 15 RESERVED - - 65 VSS GND 16 VSS GND - 66 RESERVED - 17 NC - NC 67 RXD OA DTE Serial Interface 18 /RESET OA Modem Interconnect 68 /DTR IA DTE Serial Interface 19 SR4OUT OA Modem Interconnect 69 VDD1 PWR 20 NC - NC 70 IA_SLEEP MI Modem Interconnect 21 SR4IN IA Modem Inter co nne ct 71 VGG PWR 22 CLK_OUT OA Modem Inter co nne ct 72 YCLK OA Overhead Signal 23 EYESYNC OA Diagnostic Signal 73 XCLK OA Overhead Signal 24 EYECLK OA Diagnostic Signal 74 EYEXY OA Diagnostic Signal 25 MAVSS GND - 75 /DSR OA DTE Serial Interface 26 MAVDD PWR - 76 /RI OA Telephone Line Interface 27 SPKR O(DF) Telephone Line Interface 77 RINGD IA Telephone Line Interface 28 TXA2 O(DD) Telephone Line Interface 78 /RTS IA DTE Serial Interface 29 TXA1 O(DD) Telephone Line Interface 79 IRQ OA HOST Interface 30 VREF MI Modem Interconne ct 80 VSS GND 31 VC MI Modem Inter connect 81 GPO0 MI Modem Interconnect 32 RIN I(DA) Telephone L

ine Interface 82 RESERVED - 33 MAVSS AGND - 83 RESERVED - 34 /POR IA Modem

Interconnect 84 VDD1 PWR 35 RESERVED - - 85 XTALI/CLKIN I Overhead Signal 36 RESERVED - - 86 XTALO O Overhead Signal 37 /TALK O(DD) Telephone Line Interface 87 D0 IA/OB HOST Interface 38 VDD PWR - 88 D1 IA/OB HOST Interface 39 RESERVED - - 89 D2 IA/OB HOST Interface 40 RESERVED - - 90 D3 IA/OB HOST Interface 41 NC - NC 91 D4 IA/OB HOST Interface 42 M_CNTRL_SIN IA Modem Interconnect 92 VDD1 PWR 43 M_CLKIN IA Modem Inter co nne ct 93 D5 IA/OB HOST Interf ace 44 M_TXSIN IA Modem Inter co nne ct 94 D6 IA/OB HOST Interf ace 45 M_SCK IA Modem Inter co nne ct 95 D7 IA/OB HOST Interf ace 46 M_RXOUT IA Modem Interco nne ct 96 RS0 IA/OB HOST Interface 47 M_STROBE IA Modem Inter co nne ct 97 RS1 IA/OB HOST Interface 48 RESERVED - - 98 PLL_VDD PWR 49 OH O(DD) Telephone Line Interface 99 VSS GND 50 VDD PWR - 100 PLL_GND GND -

Notes:

1. I/O types: MI = Modem interconnect. IA, IB = Digital input. OA, OB = Digital output. I(DA) = Analog input. O(DD), O(DF) = Analog output.

NC = No external connection required.

RESERVED = No external connection allowed.

3. Interface Legend: HOST = Modem Control Unit (Host) DTE = Data Terminal Equipment

FM336 Pin Signals

3-12

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Label I/O Type Signal Name/Description

TELEPHONE LINE INTERFACE/AUXILIARY

TXA1, TXA2 O(DD)

Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Each output can drive a 300 load.

RIN O(DA)

Receive Analog. RIN is a single-ended receive data input from the telephone line interface or an optional external hybrid circuit.

RINGD IA

Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency detection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35 optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring signals are reflected on the /RI output signal as well as the RI bit.

/TALK O(DD)

Relay B Control. The /TALK open collector output can directly drive a +5V reed relay coil with a minimum resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (electro-mechanical relays). /TALK is c ontrol l ed by host s etting/resetting of the RB bit.

In a typical application, /TALK is connected to the normall y closed Talk/ Data relay (/TALK). In this case, /TALK active opens the relay to disconnect the handset from the telephone line.

OH O(DD)

Relay A Control. The OH open collector output can directly drive a +5V reed relay coil with a minimum resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (electro-mechanical relays). OH is control l ed by host sett i ng/resetting of the RA bit.

In a typical application, OH is connected to the normally open Off-Hook relay (OHRC). In this case, OH active closes the relay to connect the modem to the telephone line.

Alternatively, in a typical applicati on, OH is connected to the normally open Caller ID relay (CALLID). When the modem detects a Calling Number Delivery (CND) message, the OH output is asserted to close the CALLID relay in order to AC couple the CND information to the modem RIN input (without closing the offhook relay and allowing loop current flow which would indicate an off-hook condition).

/RI OA

Ring Indicator. /RI output follows the ringing signal present on the line with a low level (0 V) during the ON time, and a high level (+3.3 V) during the OFF time coincident with the ringing signal. The RI status bit reflects the state of the /RI output.

DIAGNOSTIC SIGNALS

Three signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye pattern is a display of received baseband constellation. By observi ng this constellation, common line disturbances can usually be identified.

EYEXY OA

Serial Eye Pattern X/Y Output. EYEXY is a serial output containing two 11-bit diagnostic words (EYEX and EYEY) for display on the oscilloscope X axis (EYEX) and Y axis (EYEY). EYEX is the first word clocked out; EYEY follows. Each word has 8-bits of significance. EYEXY is clocked by the rising edge of EYECLK. This serial digital data must be converted to parallel digital form by a serial-to-parallel convert er, and then to analog form by two digital-to-analog (D/A) converters .

EYECLK OA

Serial Eye Pattern Clock. EYECLK is a 336 kHz output clock for use by the serial-to-parallel converters. The low-to-high transitions of RDCLK coinci de with the low-to-high transitions of EYECLK. EYECLK, therefore, can be used as a receiver multiplexer clock.

EYESYNC O

Serial Eye Pattern Strobe. EYESYNC is a strobe for loading the D/A converters.

SPEAKER INTERFACE

SPKR O(DF)

Speaker Analog Output. The SPKR output reflects the received analog input signal. The SPKR on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speak er is t urned off , the SPKR output is clamped to the voltage at the VC pin. The SPKR output can drive an impedance as low as 300 ohms. In a typical application, the SPKR output is an input to an external LM386 audio power amplifier.

FM336 Signals Definitions

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