Samsung SF-530 Schematics Diagram

Repair Manual

Repair Manual

1. Block Diagram

2. Connection Diagram

3. Circuit Description

4. Schematic Diagrams

CONTENTS

SAMSUNG FACSIMILE

SF-530/531P

Electronics

Samsung Electronics Digital Printing
CS Group

Copyright (c) 2001. 10

This manual is made and

described centering around

circuit diagram

and circuit description needed

in the repair center

in the form of appendix.

SAMSUNG

1

1-1

Samsung Electronics

BLOCK DIAGRAM

Repair Manual

1. Block Diagram

MA I N

POWER

CORD

KS32C65100

ARM7T

GEU

P1284

ITU

I/OI/F

CACHE( 6 K)

DMAC

PVC

UART* 2

MEM OR Y I / F

MODEM

DRAM

(8MB)

CI S I NTERFACE

PART

HOST

(P

C

)

CI S

CENTRONI CS

USB

TX MOTOR

DRI VER

TX

MOTOR

RTC

Bac k- up Par t

LI U

MO DE M &

EXT_PHONE

SEPERAT ING

PART

600/ /600

Tx: Rx

TRANSFORMER

EXTERNAL

PHONE

DETECT I ON

PART

EXTERNAL

PHONE

LI NE

HANDSET

600/ /600

Tx: Rx

TRANSFORMER

FLASH

MEMORY

(2MB)

+5V

UART

-5V

SCAN Boar d

MI COM

- LCD Dr iv e

- Key Scan

OPE

LCD

DOC

SEN SOR

SMPS

HVPS

+24V

MOTOR

OLENOIDE

ENGINE

B'D

FAN

OPC_FUSE

Audio Part

EXIT

SEN SOR

MHV

OPC GND

SUPPLY

DEV

THV

UNICON

(USB IC)

Note. -. SF-530 : Fax Function Only

-. SF-531P : Printer Function with Fax

*Note

33600 bps

2

2-1

Samsung Electronics

CONNECTION DIAGRAM

Repair Manual

2. Connection Diagr am

5GND5
4+5V
3OPE_TXD
2OPE_RST
1OPERXD

LCD

CN1

OP E

CN3

SCAN B’ D

1

8
+

2

4

V

1

7
+

2

4

V

1

6
S

C

N

M

O

T
A

1

5
+

5

V

1

4
S

C

N

M

O

T
*

B

1

3
S

C

N

M

O

T
*

A

1

2
S

C

N

M

O

T
B

1

1
G

N

D

1

0
O

P

E
R

X

D

9
G

N

D
5

8
O

P

E
T

X

D

7
O

P

E
R
S

T

6
G

N

D
5

5
+

5

V

4
C

I

S
S

I

G

3
C

I

S
L

C

D

2
C

I

S
S

I

1
C

I

S
C

L

K

CN1

214365871091211141316151817

CN1 6

1 2 34 5 678 91011 12131415161718

HOST

(PC)

IEEE1284 I/F
(36PIN)

USB PORT
(4PIN)

CN2

CN19

1+5V
2/PEMPTY
3/FEED
4GND5

SENSOR

B’ D

COVER
SWITCH

1+24V
2+24VS

HVPS

CN1

1+24VS1
2GND24
3THVPWM
4/THV_EA
5THVREAD
6MHVPWM
7BIASPWM
8+5V
9GND

5

CN8 - 1

THER-MISTOR

1THERM_A
2THERM_B

CN7

CN1 8

CN15- 1

CN1 3- 1

CN7

CN9

ENG INE

B’d

LSU

LD DIODE

POLY GO N
MOT OR

1+24VS
2GND24
3PMOTOR
4/LREADY
5EXTCLK

6/USYNC
7+5V
8CND5

9/LD_ON
10 VD0
11 / APC_SH

12 SLUTCH
13 FAN
14 PTL
15 DEV_FUSE
16 / NEW_DEVE
17 / EGMOT_A0
18 / EGMOT_ A1
19 EGMOT_PHA
20 / EGMOT_B0
21 / EGMOT_B1
22 GND5
23 +5V
24 EGMOT_PHA
25 +24VS
26 +24VS
27 GND24
28 GND24

CN1 2

SPK

1SPKOUT
2AGND

1

4
M

O

D

E

M
T

X

A

1

1

3
M

O

D

E

M
T

X

A

2

1

2
A

G
N
D

1

1
N

C

1

0
M

O

D

E

M
R

X

9
/

E

X

T
P

H

O

N

E

8
C

M
L

1

7
R
E

M
O
T

E

6
C

M

L

2

5
/

D

P

4
/

H

O

O

K

1

3
+

5

V

2
G
N
D
5

1
/

R
I

N

G

CN1 4

1+24VS
2FUSER_ON
3+5V
4/EXIT
5+5V
6GND5
7+5V
8GND5
9-5V
10 GND5
11 24V
12 GND24
13 24V
14 GND24
15 24V
16 GND24

CN5 03

SMPS

A

Heat Lamp

(Fuser)

HOT
Neutral

CLINE

MAIN B’d

1GND5
2+5V
3V0
4LCD_RS
5LCD_RW
6LCD_F
7LED_0
8LED_1
9LED_2
10 LED_3
11 LED_4
12 LED_5
13 LED_6
14 LED_7

HOOK B’d CN2 CN1

CN3

MJ1

1LINE_2
2LINE_3
3LINR_4
4LINR_5
5LINR_6

6EXT_3
7EXT_4
8EXT_5

1MIC1
2 RCV3
3MIC2
4 RCV1
5 HOOK2
6 HOOK2 _NC
7 HOOK2 _NO

10 HOOK1
11 HOOK1_NO
12 HOOK1_NC

LIU B’d

MJ1

1 CIS_SIG
2 GND
3 +5V
4 GND
5 GND
6 START PULSE
7 GND
8 CIS MAIN CLOCK
9 LED B
10 LED G
11 LED R
12 V LED

1 CIS_SIG
2 GND
3 +5V
4 CIS_SI
5 CIS_CLK
6 CIS_LED
7 +24V

200 DPI 300 DPI

1 +24
2 +24
3 SCNMOT_A
4 SCNMOT_*A
5 SCNMOT_B
6 SCNMOT_*B

SCAN

MOTOR

CN2 CN4

CIS

3

3-1

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3. Circuit Description

3-1 Main PBA

3-1-1 Summary

The main circuit that consists of CPU, MFP controller including various I/O device drivers, system memory, scanner, print­er, motor driver, PC I/F, and FAX transceiver controls the whole system. The entire structure of the main circuit is as follows:

I/O Ports

Controller

Scan Image &

Scan Motor

Controller

Ink Head

Controller

DMA

Controller

Parallel

Port

Interface

Video Data

Controller

UART/

Serial I/O

LSU

Control

PWM &

Gen. Timer

System Bus Controller Bus Arbitration

Bus Interface

ROM/SRAM/DRAM Controller

System Manager

Bus Router

PLL & Clock

Save

Interrupt

Controller

A/D

Converter

Derasterizer

Carrier Motor

Control

Position &

Fire Control

Paper Motor

Control

Real Time

Clock

Watch Dog

Timer

CPU

(ARM7TDMI)

I/D Cache

(2-KB)

LBUS

ADDR

DATA

CNTR

3-2

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-1-2 Circuit Operation

• CLOCK

1) System Clock
Device Oscillator
Frequency 9.500132 MHz
KS32C65100 RISC PROCESSOR: drives PLL internally and uses 37.17 MHz.

2) Video Clock
Device Oscillator
Frequency 28.7448 MHz

3) USB Clock
Device Oscillator
Frequency 48 MHz±%

3-3

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

• KS32C65100 MICROPROCESSOR

1) KS32C65100 MICROPROCESSOR PIN & INTERFACE

Signal Pin No. I/O Type Description

OSCI 184 I7 KS32C65100 master clock in put.

OSCO 185 O7 KS32C65100 master clock outpu t.

PLL_FILTER 183 I5 PLL filter

nRESET 182 I4

Not reset. nRESET is the global reset input for the
KS32C65100. For a system reset, nRESET must be held to
low level for at least 65 machine cycles.

nSLCTIN/GIP[16] 152 I1

Not select information. This input signal is used by parallel
port interface to request 'on-line' status information.

nSTROBE 151 I1

Not strobe. The nSTROBE input indicates when valid data is
on parallel port data bus, PPD[7:0]

nAUTOFD/GIP[17] 154 I1

Not auto feed. The nAUTOFD input indicates whether data
on the parallel port data bus, PPD[7:0], is an auto feed
command. Otherwise, the bus signals are interpreted as data
only.

nINIT/GIP[15] 153 I1

Not initialization. The nINIT input signal initializes the parallel
port's input con trol.

nACK 159 I1

Not parallel port acknowledg e. The nACK output signal is
issued whenever a transfer on the parallel port data bus is
completed.

BUSY 158 O1

Parallel port busy. The BUSY output signal indicates that the
KS32C65100 parallel port is currently busy.

SELECT 156 O1

Parallel port select. The SELECT output signal indicates
whether the device connected to the KS32C65100 parallel
port is 'on-line' or 'off-line'.

PERROR 157 O1

Parallel port paper error. PERROR output indicates that a
problem exists with the paper in the ink-jet printer. It could
indicate that the printer has a paper jam or that the printer
isoutofpaper.

nFAULT 155 O1

Not fa ult. The nFAULT output indicates that an error
condition exists with the printer. This signal can be used to
indicate that the printer is out of ink or to inform the user
that the printer is not turned on.

PPD[7:0] 142~149 I/O2

arallel port data bus. This 8-bit, tri-state bus is used to
exchange data between the KS32C6510 0 and an external
host(peripheral).

SAVRT 2 I6 Top reference voltage for IP ADC

SAIN 3 I6 Analog input for IP ADC

SAVRB 4 I6 Bottom reference voltage for IP ADC

3-4

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Signal Pin No. I/O Type Description

CIS_CLK 6 O1 CIS shift clock
CIS_SI 7 O1 CIS latch signal
PHA_IA0 164 O1 Line feed motor phase signal A
PHA_IA1 165 O1 Line feed motor phase signal AZ
PHB_IB0 167 O1 Line feed motor phase signal B
PHB_IB1 168 O1 Line feed motor phase signal BZ
LF_PH0/GOPA[21] 163 O1 Line feed motor control signal 0
LF_PH1/GOPA[22] 166 O1 Line feed motor control signal 1
CR_PHA/GOPA[23] 110 O1 Direction control line for phase A
CR_PHB/GOPA[24] 113 O1 Direction control line for phase B
CRIA0/GOPA[25] 109 O1 Current control line 0 for phase A
CRIA1/GOPA[26] 111 O1 Current control line 1 for phase A
CRIB0/GOPA[27] 112 O1 Current control line 0 for phase B
CRIB1/GOPA[28] 114 O1 Current control line 1 for phase B
CHX/GIP[8] 116 I3 Encode sensor
CHY/GIP[9] 117 I3 Encode sensor

ADDR[21:0]

77~80,
82~88,
90~100

O5

Address bus. The 22bit address bus, ADDR[21:0], covers
the full 4M half-words address range of each ROM/SRAM,
DRAM, and external I/O bank

DATA[15:0]

59~66,
68~75

I/O3 Exte rnal bi-directional 16-bit data bus.

nRAS[1:0] 52,53 O1

Not row address strobe for DRAM. The KS32C65100
supports up to two DRAM b anks. One nRAS output is
provided for each bank.

nCAS[1:0] 54,55 O1

Not column address strobe for DRAM. The two nCAS
outputs indicate the byte selections whenever a DRAM bank
is accessed.

nOE 56 O1

Not output e nable. Whenever a memory access occurs, the
nOE output controls the output enable port of the specific
memory device.

nWE 57 O6

Not write enable. Whene ver a memory access occurs, the
nWE outpu t con trols the write enable port of the specific
memory device.

nPHGA[13:1]/
GOPB[12:0]

16~24,

26~29

O1 Gate control line for print head.

PHOE[16:1]/
GIOP[26:11]

31~38,

40~47

I/O1 Drain control line for print head.

3-5

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Signal Pin No. I/O Type Description

RXD0/GIP[0] 194 I1

Receive data input for the UART0. RXD0 is the UART0
channel's input signal for receiving serial data.

RXD1/GIP[1] 192 I1

Receive data input for the UART1. RXD1 is the UART1
channel's input signal for receiving serial data.

RXD2/GIP[2] 190 I1

Receive data input for the UART2. RXD2 is the UART2

channel's input signal for receiving serial data.
nEINT0/GIP[3] 8 I3 External interrupt request input nEINT0.
nEINT1/GIP[4] 9 I3 External interrupt request input nEINT1.
nEINT2/GIP[5] 10 I3 External interrupt request input nEINT2.
nXDREQ/GIP[6] 199 I3 External DMA request.

TXD0/GOPA[0] 193 O1

Transmit data output for the UART0. TXD0 is the UART0

channel's o utput for transmitting serial data.

TXD1/GOPA[1] 191 O1

Transmit data output for the UART1. TXD1 is the UART1

channel's o utput for transmitting serial data.

TXD2/GOPA[2] 189 O1

Transmit data output for the UART2. TXD2 is the UART2

channel's o utput for transmitting serial data.

nXDACK/GOPA[5] 200 O1

Exte rnal DMA acknowledge. This active low output signal is

generated whenever a DMA transfer is completed.
TONEOUT/GOPA[3] 188 O1 Tone generator output.
nWDTO/GOPA[4] 187 P3 Reset out by watch dog timer.
nIOWR/GOPA[10] 161 O1 External output write strobe
nIORD/GOPA[9] 162 O1 External output read strobe
CLKOUT/GOPA[6] 180 O1 Clock for external chip
nECS2/GOPA[8] 14 O1 External memory chip select 2.
TCK 132 I2 JTAG TCK interface in MDS mode.
TMS 135 I2 JTAGTMSinterfaceinMDSmode.
TDI 133 I2 JTAG TDI interface in MDS mode.
nTRST 136 I2 JTAG nTRST interface in MDS mode.
TDO 134 O1 JTAG TDO interface in MDS mode.

GIOP[10:0]

137~140,

173~179

I/O4 General I/O port.

TEST0 169 I2

Test 0 pin. At normal operation this pin must be connected

to GND.

TEST1 170 I2

Test 1 pin. At normal operation this pin must be connected

to GND.

TEST2 171 I2

Test 2 pin. At normal operation this pin must be connected

to GND.

3-6

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Signal Pin N o. I/O Type Description

nECS[1:0] 12,13 O1

Not external chip select. Three I/O banks are provided for
external memory-mapped I/O operations. Each I/O bank
contains up to 4M half-word. The nECS signals indicate that
an external I/O bank is selected.

nRCS[2] 51 O2

Not ROM/SRAM chip select. The KS32C65100 can access

up to three external ROM/SRAM banks. nRCS[0]

corresponds to ROM/SRAM bank 0, nRCS[1] to bank 1, and

nRCS[2] to bank 2. By controlling the nRCS signals, CPU

addresses can be mapped into the physical memory banks.

nRCS[1]/GOPA[7] 50 O1

nRCS[0] 49 O1

SC_CONPHA/
GOPA[19]

102 O1 Scan motor control/Bi-phase

SC_CONPHB/
GOPA[20]

105 O1 Scan motor control/Bi-phase

SC_CUR[3:0]

103, 104,

106, 107

O1 Scan motor bi-current/un i-phase

PWMO[2:0]/
GOPA[13:11]

118~120 O1 PWM out signal

VDO2/GOPA[29] 121 O4 Video out from PIFC
VDO1/GOPA[14] 122 O5 Video out from LSU control
LSU_CLK/

GOPA[15]

123 O1 Clock for LSU motor

nHSYNC1/GIP[10] 125 I1 HSYNC1
nLREADY/GIP[11] 126 I1 LSU ready
nHSYNC2/GIP[12] 127 I1 HSYNC2
VDI/GIP[13] 128 I2 Video data input from RET
VCLK/GIP[14] 129 I2 External video clock
nEXTWAIT/G IP[7] 130 I3 External wait
RTCXIN 202 I7 RTC oscillator clock input.
RTCXOUT 203 O7 RTC oscillator clock output.

SLED[2:0]/
GOPA[18:16]

196~198 O1 CIS LED signals

GAVRT 20 5 I5 Top reference voltage for general ADC
GAIN[2:0] 206~208 I5 Analog inputs for general ADC
RTC_VDD 201 RTC VDD.

Signal Pin No. I/O Type Description

VDD_PLL 18 6 PLL power (3.3V).
SAVDD 1 Analog power for scan ADC and general ADC (3.3V).
SAVSS 5 Scan ADC gr ound.
GAVSS 204 General ADC gr ound

3VDD

15, 30, 81 ,

115, 131,

160

3.3V internal power.
Externally connected to the 3.3V regulator.

5VDD

48, 67, 89 ,

141, 195

5V I/O power.
Externally connected to the VCC board plane.

VSS

11, 25, 39 ,

58, 76, 1 01,

108, 124,
150, 172,

181

System ground.
Externally connected to the ground board plane.

3-7

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-1-3 PROGRAM ROM (FLASH MEMORY)

1) DEVICE
TYPE No. AM29F800B
CAPACITY 2 Mbit (512K * 16bit * 2)

2) PROGRAMMING
BEFORE ASS’Y EPROM PROGRAMMER or PROGRAMMING at the factory
AFTER ASS’Y DOWNLOAD from PC

3-1-4 DRAM CONTROL

1) DEVICE
TYPE NO. K4E641611D-TC50(EDO Type)
CAPACITY 64 Mbit (4M * 16bit)

2) OPERATING PRINCIPLE
DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores data white the

CPU processes data. The address to read and write the data is specified by RAS SIGNAL and CAS SIGNAL.
DRAMWE*SIGNAL is activated when writing data and DRAMOE*SIGNAL, when reading.

3-1-5 USB (Universal Serial Bus)

SAMSUNG’S UNICON is used as the interface IC and 48MHz clock is used.
When the data is received through the USB port, USBIRQ SIGNAL is activated to send interrupt to CPU, then it directly
sends the data to DRAM by USB_CS SIGNAL through D(0;7).

3-1-6 Modem and TX-and RX Related Circuits

MODEM

The Conexant™ FM336 modem is a V.34 half-duplex modem that supports Group 3 facsimile send and receive speeds
up to 33600 bps using the V.34 half-duplex mode. Using a V.34 technique to optimize modem configuration for line condi­tions, the modem connects at the optimal selected data rate that the channel can support from 33600 bps to 2400 bps.

The modem can operate over the public switched telephone network (PSTN) through a line terminator provided by a Data
Access rrangement (DAA). The modem satisfies the requirements specified inITU-T recommendations V.34, V.17, V.29,
V.27 ter, V.23, V.21, and meets the binary signal ingrequirements of V.8 and T.30. Internal HDLC support eliminates the
need for an external serial input/output (SIO) device in the DTE for products incorporating error detection and T.30 proto­col. The modem can perform HDLC framing per T.30 at all data speeds. CRC generation/checking along with zero inser­tion/deletion enhances DLC/HDLC frame operations. An FSK flag pattern detector facilitates FSK detection during high
speed reception.The modem features a programmable DTMF transmitter/receiver and three programmable tone detectors
which operate in the tone mode.

The modem offers lower power consumption and small size to allow the design of compact system enclosures for use in
industrial, office, and home environments.The modem is available in a 100-pin PQFPpackage.

3-8

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

FM336 FEATURES

• 2-wire half

- duplex fax modem modes with send and receive data rates up to 33600 bps.

- V.34, V.17, V.29, V.27 ter, and V.21 channel 2

- Short train option in V.17 and V.27 ter

• 2-wire full

- duplex data modem modes

- V.21, V.23 (75 bps TX/1200 bps RX or 1200 bps TX/ 75 bps RX)

• PSTN session starting

- V.8 signaling

• HDLC support at all speeds

- Flag generation, 0 bit stuffing, ITU CRC

- 16 or CRC

- 32 calculation and generation

- Flag detection, 0 bit deletion, ITU CRC

- 16 or CRC

- 32 check sum error detection

-

FSK flag pattern detection during high speed receiving

• Tone modes and features

- Programmable single or dual tone generation

- DTMF receive

- Tone detection with three programmable tone detectors

• Serial synchronous data

• Parallel synchronous data

• Automatic Rate Adaptation (ARA) in V.34 Half-Duplex

• TTL and CMOS compatible DTE interface

- ITU-T V.24 (EIA/TIA-232-E) (data/control)

- Microprocessor bus (data/configuration/control)

• Receive dynamic range: 0 dBm to –43 dBm for V.17, V.33, V.29, V.27terand V.21, –9 dBm to –43 dBm for V.34 half-duplex

• Programmable RLSD turn-on and turn-off thresholds

• Programmable transmit level: 0 to -15 dBm

• Adjustable speaker output to monitor received signal

• DMA support interrupt lines

• Two 16-byte FIFO data buffers for burst data transfer with extension up to 255 bytes

• NRZI encoding/decoding

• Diagnostic capability

• +3.3V operation with +5V tolerant inputs

• +5V analog signal interface

• Typical power consumption:- Sleep mode: 20 mW

- Normal mode: 250 mWa

• 100-pin PQFP package

3-9

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Signaling Rates, and Data Rates

Configuration

Modulation

1

Carrier Frequency

(Hz) –0.01%

Data Rate (bps)

–0.01%

Symbol Rate

(Symbols/Sec.)

Bits/Symbol -

Data

Bits/Symbol -

TCM

Constellation

Points

V.34 33600 TCM TCM Note 2 33600 3429 only Note 2 Note 2 Note 2
V.34 31200 TCM TCM Note 2 31200 320 0 mi n Note 2 Note 2 Note 2
V.34 28800 TCM TCM Note 2 28800 300 0 mi n Note 2 Note 2 Note 2
V.34 26400 TCM TCM Note 2 26400 280 0 mi n Note 2 Note 2 Note 2
V.34 24000 TCM TCM Note 2 24000 280 0 mi n Note 2 Note 2 Note 2
V.34 21600 TCM TCM Note 2 21600 240 0 mi n Note 2 Note 2 Note 2
V.34 19200 TCM TCM Note 2 19200 2400 to 3429 Note 2 Note 2 Note 2
V.34 16800 TCM TCM Note 2 16800 2400 to 3429 Note 2 Note 2 Note 2
V.34 14400 TCM TCM Note 2 14400 2400 to 3429 Note 2 Note 2 Note 2
V.34 12000 TCM TCM Note 2 12000 2400 to 3429 Note 2 Note 2 Note 2
V.34 9600 TCM TCM Note 2 9600 2400 to 3429 Note 2 Note 2 Note 2
V.34 7200 TCM TCM Note 2 7200 2400 to 3429 Note 2 Note 2 Note 2
V.34 4800 TCM TCM Note 2 4800 2400 to 3429 Note 2 Note 2 Note 2
V.34 2400 TCM TCM Note 2 2400 2400 only Note 2 Note 2 Note 2
V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 —
V.21 FSK 1080/1750 Up to300 300 1 0 —
V.17 14400 TCM TCM 1800 14400 2400 6 1 128
V.17 12000 TCM TCM 1800 12000 2400 5 1 64
V.17 9600 TCM TCM 1800 9600 2400 4 1 32
V.17 7200 TCM TCM 1800 7200 2400 3 1 16
V.29 9600 QAM 1700 9600 2400 4 0 16
V.29 7200 QAM 1700 7200 2400 3 0 8
V.29 4800 QAM 1700 4800 2400 2 0 4
V.27 ter 4800 DPSK 1800 4800 1600 3 0 8
V.27 ter 2400 DPSK 1800 2400 1200 2 0 4
V.21 Channel 2 FSK 1750 300 300 1 0 —

Notes:

1. Modulation legend: TCM:Trellis-Coded Mod ulati on QAM: Quadrature Amplitude Modulation
FSK:Frequency Shift Keying DPSK: Differential Phase Shift Keying

2. Adaptive; established during handshake:
Carrier Frequency (H z)

Symbol Rate (Baud) V.34 Low Carrier V.34 High Carrier
2400 1600 1800

2800 1680 1867
3000 1800 2000
3200 1829 1920
3429 1959 1959

3-10

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

V.24

Interface

Host

Processor

FM336

Modem

Crystal

Power Supply

Speaker

Amplifier

Optional

Eye Pattern

Generator

Line

Interface

/RTS

TXD

/CTS

TDCLK

XTCLK

/RLSD

RXD

/RDCLK

/DTR

/RI*

/DSR**

/RD

/CS

/WR

D[7:0]

RS[4:0]

IRQ

/RESET

TXRQ*

RXRQ**

XTL0

XTLI

TXA1

RIN

OH

TXA2

/TALK

RINGD

EYEXY

EYESYNC

EYECLK

+5V

AGND
DGND

SPKR

* Selectable; TXRQ output replaces /RI output.
** Selectable; RXRQ output replaces /DSR output.

1176DG F2-1

TIP

RING

telephone
line

+3.3V

Oscillator

CLKIN

OR

Modem Functions Interface Signals

3-11

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Pin Signal Label

I/O Type

1

Interface

3

Pin Signal Label

I/O Type

1

Interface

3

1 RESERVED - - 51 RESERVED - ­2 RS2 IA HOST Interface 52 VSUB GND ­3 RS3 IA HOST Interface 53 VSS GND ­4 RS4 IA HOST Interface 54 NC - NC
5 /CS IA HOST Interface 55 NC - NC
6 /WR IA HOST Interface 56 Sleep MI Modem Interconnect
7 /RD IA HOST Interface 57 VDD1 PWR ­8 /RDCLK OA DTE Serial Interface 58 RESERVED - -

9 /RLSD OA DTE Serial Interface 59 RESERVED - ­10 TDCLK OA DTE Serial Interface 60 NC - NC
11 TXD IA DTE Serial Interface 61 SR1 IO MI Mod em Inter co nne ct
12 /CTS OA DTE Serial Interface 62 VCORE PWR ­13 VDD1 PWR - 63 VDD1 PWR ­14 RESERVED - - 64 XTCLK IA DTE Serial Interface
15 RESERVED - - 65 VSS GND ­16 VSS GND - 66 RESERVED - ­17 NC - NC 67 RXD OA DTE Serial Interface
18 /RESET OA Modem Interconnect 68 /DTR IA DTE Serial Interface
19 SR4OUT OA Modem Interconnect 69 VDD1 PWR ­20 NC - NC 70 IA_SLEEP MI Modem Interconnect
21 SR4IN IA Modem Inter co nne ct 71 VGG PWR ­22 CLK_OUT OA Modem Inter co nne ct 72 YCLK OA Overhead Signal
23 EYESYNC OA Diagnostic Signal 73 XCLK OA Overhead Signal
24 EYECLK OA Diagnostic Signal 74 EYEXY OA Diagnostic Signal
25 MAVSS GND - 75 /DSR OA DTE Serial Interface
26 MAVDD PWR - 76 /RI OA Telephone Line Interface
27 SPKR O(DF) Telephone Line Interface 77 RINGD IA Telephone Line Interface
28 TXA2 O(DD) Telephone Line Interface 78 /RTS IA DTE Serial Interface
29 TXA1 O(DD) Telephone Line Interface 79 IRQ OA HOST Interface
30 VREF MI Modem Interconne ct 80 VSS GND ­31 VC MI Modem Inter connect 81 GPO0 MI Modem Interconnect
32 RIN I(DA) Telephone L

ine Interface 82 RESERVED - ­33 MAVSS AGND - 83 RESERVED - ­34 /POR IA Modem

Interconnect 84 VDD1 PWR ­35 RESERVED - - 85 XTALI/CLKIN I Overhead Signal
36 RESERVED - - 86 XTALO O Overhead Signal
37 /TALK O(DD) Telephone Line Interface 87 D0 IA/OB HOST Interface
38 VDD PWR - 88 D1 IA/OB HOST Interface
39 RESERVED - - 89 D2 IA/OB HOST Interface
40 RESERVED - - 90 D3 IA/OB HOST Interface
41 NC - NC 91 D4 IA/OB HOST Interface
42 M_CNTRL_SIN IA Modem Interconnect 92 VDD1 PWR ­43 M_CLKIN IA Modem Inter co nne ct 93 D5 IA/OB HOST Interf ace
44 M_TXSIN IA Modem Inter co nne ct 94 D6 IA/OB HOST Interf ace
45 M_SCK IA Modem Inter co nne ct 95 D7 IA/OB HOST Interf ace
46 M_RXOUT IA Modem Interco nne ct 96 RS0 IA/OB HOST Interface
47 M_STROBE IA Modem Inter co nne ct 97 RS1 IA/OB HOST Interface
48 RESERVED - - 98 PLL_VDD PWR ­49 OH O(DD) Telephone Line Interface 99 VSS GND ­50 VDD PWR - 100 PLL_GND GND -

Notes:

1. I/O types:
MI = Modem interconnect.
IA, IB = Digital input.
OA, OB = Digital output.
I(DA) = Analog input.
O(DD), O(DF) = Analog output.

2.

NC = No external connection required.

RESERVED = No external connection allowed.

3. Interface Legend:
HOST = Modem Control Unit (Host)
DTE = Data Terminal Equipment

FM336 Pin Signals

3-12

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Label I/O Type Signal Name/Description

TELEPHONE LINE INTERFACE/AUXILIARY

TXA1, TXA2 O(DD)

Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase
with each other. Each output can drive a 300 load.

RIN O(DA)

Receive Analog. RIN is a single-ended receive data input from the telephone line interface or an optional
external hybrid circuit.

RINGD IA

Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency
detection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35
optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing
less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring
signals are reflected on the /RI output signal as well as the RI bit.

/TALK O(DD)

Relay B Control. The /TALK open collector output can directly drive a +5V reed relay coil with a minimum
resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A
clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be
used to drive heavier loads (electro-mechanical relays). /TALK is c ontrol l ed by host s etting/resetting of the
RB bit.

In a typical application, /TALK is connected to the normall y closed Talk/ Data relay (/TALK). In this case,
/TALK active opens the relay to disconnect the handset from the telephone line.

OH O(DD)

Relay A Control. The OH open collector output can directly drive a +5V reed relay coil with a minimum
resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A
clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be
used to drive heavier loads (electro-mechanical relays). OH is control l ed by host sett i ng/resetting of the RA
bit.

In a typical application, OH is connected to the normally open Off-Hook relay (OHRC). In this case, OH
active closes the relay to connect the modem to the telephone line.

Alternatively, in a typical applicati on, OH is connected to the normally open Caller ID relay (CALLID). When
the modem detects a Calling Number Delivery (CND) message, the OH output is asserted to close the
CALLID relay in order to AC couple the CND information to the modem RIN input (without closing the off­hook relay and allowing loop current flow which would indicate an off-hook condition).

/RI OA

Ring Indicator. /RI output follows the ringing signal present on the line with a low level (0 V) during the ON
time, and a high level (+3.3 V) during the OFF time coincident with the ringing signal. The RI status bit
reflects the state of the /RI output.

DIAGNOSTIC SIGNALS

Three signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The
eye pattern is a display of received baseband constellation. By observi ng this constellation, common line
disturbances can usually be identified.

EYEXY OA

Serial Eye Pattern X/Y Output. EYEXY is a serial output containing two 11-bit diagnostic words (EYEX
and EYEY) for display on the oscilloscope X axis (EYEX) and Y axis (EYEY). EYEX is the first word clocked
out; EYEY follows. Each word has 8-bits of significance. EYEXY is clocked by the rising edge of EYECLK.
This serial digital data must be converted to parallel digital form by a serial-to-parallel convert er, and then to
analog form by two digital-to-analog (D/A) converters .

EYECLK OA

Serial Eye Pattern Clock. EYECLK is a 336 kHz output clock for use by the serial-to-parallel converters.
The low-to-high transitions of RDCLK coinci de with the low-to-high transitions of EYECLK. EYECLK,
therefore, can be used as a receiver multiplexer clock.

EYESYNC O

A

Serial Eye Pattern Strobe. EYESYNC is a strobe for loading the D/A converters.

SPEAKER INTERFACE

SPKR O(DF)

Speaker Analog Output. The SPKR output reflects the received analog input signal. The SPKR on/off and
three levels of attenuation are controlled by bits in DSP RAM. When the speak er is t urned off , the SPKR
output is clamped to the voltage at the VC pin. The SPKR output can drive an impedance as low as 300
ohms. In a typical application, the SPKR output is an input to an external LM386 audio power amplifier.

FM336 Signals Definitions

3-13

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Label I/O Type Signal Name/Description

REFERENCE SIGNALS AND MODEM INTERCONNECT

VC MI

Low Voltage Reference. Connect to analog ground through 10 F (polarized, + terminal to VC)
and 0.1 F (ceramic) in parallel.

VREF MI

High Voltage Reference. Connect to VC through 10 F (polarized, + termi nal t o VREF) and 0.1 F
(ceramic) in parallel.

/POR IA

Power-On-Reset. Connects to /RESET.

/RESET OA

Reset. Connects to /POR.

CLK_OUT MI

IA Clock. Connect to M_CLKIN.

SR4OUT OA

SR4OUT. Connect to M_TXSIN.

SR4IN IA

SR4IN. Connect to M_RXOUT.

SR1IO OA

SR1IO. Connect to M_CNTRL_SIN.

M_CNTRL_SIN IA

M_CNTRL_SIN. Connect to SR1IO.

M_CLKIN IA

M_CLKIN. Connect to CLK_OUT.

M_TXSIN IA

M_TXSIN. Connect to SR4OUT.

M_SCK IA

M_SCK. Connect to EYECLK.

M_RXOUT IA

M_RXOUT. Connect to SR4IN.

M_STROBE IA

M_STROBE. Connect to EYESYNC.

SLEEP MI

SLEEP. Connect to IA_SLEEP.

IA_SLEEP MI

IA_SLEEP. Connect to SLEEP

GPO0 MI

GPO0. Connect to /RDCLK.

DTE SERIAL INTERFACE

/RDCLK OA

Receive Data Clock. The modem outputs a synchronous Receive Data Cl ock (/RDCLK) for USRT
timing. The /RDCLK frequency is the data rate (–0.01%) with a duty cycle of 50 –1%. The /RDCLK
low-to-high transitions coincide with th e center of t he received data bits.

/RLSD OA

Received Line Signal Detector. For V.17, V.33, V.29, and V.27 ter; RLSD goes active at the end
of the training sequence. If energy is above the turn-on threshold and training is not detected, the
/RLSD off-to-on response time is 816 baud times for V.17/V.33, V.29, and V.27 ter long train; 492
baud times for V.17/V.33; and 486 baud times for V.27 ter short train. The /RLSD on-to-off time is
40 – 5 ms for V.17/V.33, 35 – 5 ms for V.29 or 11.6 – 5 ms for V.27 ter. The /RLSD on-to-off time
ensures

that all valid data bits have appeared on RXD.

The /RLSD programmable threshold levels default to —43 dBm for off-to-on and to —48 dBm for on-
to-off. A minimum hysteresis of 2 dBm exists between the act ual off-to-on and on-to-off transition
levels. The threshold level and hysteresis are measured with an unmodulated 2100 Hz tone applied
to the Receiver Analog (RXA) input.

Note: Performance may be degraded when the received signal level is less than —43 dBm.

TDCLK OA

Data Clock. The modem outputs a synchronous Data Clock (DCLK) for USRT timing. The DCLK
frequency is the data rate (–0.01%) with a duty cycle of 50 –1%. The DCLK low-to-high transitions
coincide with the center of the data

bits. Transmit Data (TXD) must be stable during the one
microsecond period immediately preceding the rising edge of DCLK and following the rising edge of
DCLK.

TXD IA

Transmit Data. The modem obtains serial data to be transmitted from the local DTE on the
Transmit Data (TXD) input in serial data mode (TPDM bit = 0), or from the interface memory
Transmit Data Register (TBUFFER) in parallel data mode (TPDM bit = 1).

FM336 Signals Definitions (Cont’d)

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CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Label I/O Type Signal Name/Description

/CTS OA

Clear To Send. /CTS active indicates to the local DTE that the modem will transmit any data
present on TXD. /CTS response times from an active condition of /RTS are shown in Table 1-3.

XTCLK IA

External Transmit Clock. In synchronous communication, an external transmit data cl ock can be
connected to the modem XTCLK input. The clock supplied at XTCLK must exhibit the same
characteristics as TDCLK. The XTCLK input is then reflected at the TDCLK output.

RXD OA

Received Data. The modem presents received serial data to the local DTE on the Received Data
(RXD) output and to the interface memory Receive Data Register (DBUFFER) in parallel data
mode.

/DTR IA

Data Terminal Ready. In V.8 and V.34 configuration, activating /DTR init i ates t he handshake
sequence. The DATA bit must be set to complete the handshake.

In V.21 or V.23 configuration, activating /DTR causes t he modem t o enter the data state provided
that the DATA bit is a 1. If in answer mode, the modem immediately sends answer tone. During the
data mode, deactivating /DTR causes the transmitter and receiver t o turn off and return to the idle
state.

The /DTR input and the /DTR control bit are logically ORed.

/DSR OA

Data Set Ready. DSR ON indicates that the modem is in the data transfer state. DSR OFF
indicates that the DTE is to disregard all signals appearing on the interchange ci rcuits except Ring
Indicator (/RI). /DSR is OFF when the modem is in a test mode (local analog or remote digital
loopback). The /DSR status bit reflects the state of the /DSR output.

/RTS IA

Request to Send. The active low /RTS input allows the modem to transmit data present at TXD in
the serial data mode (TPDM bit = 0), or in DBUFFER in the parallel data mode (TPDM bit = 1),
when /CTS becomes active.

The /RTS hardware control input is logically ORed with the /RTSP bit by the modem to form the
resultant control signal.

HOST INTERFACE

/CS IA

Chip Select. The active low /CS input selects and enables the modem DSP for parallel data
transfer between the DSP and the host over the microprocessor bus.

/WR IA

Write. Writing is controlled by the host pulsing /WR input low during the microprocessor bus access
cycle. The write timing is:

Parameter Symbol Min. Max. Units

CS Setup Time TCS 0 — ns
RSi Setup Time TRS 10 — ns
Control Hold Time THC 10 — ns
Write Data Setup Time TWDS 20 — ns
Write Data Hold Time TDHW 10 — ns

Note: A read or write operati on foll owing a write operati on m ust be del ayed by at least 4 XCLK

cycles.

/RD IA

Read Enable. Reading is controlled by the host pulsing /RD input low during the microprocessor
bus access cycle. The read timing is:

Parameter Symbol Min. Max. Units

CS Setup Time TCS 0 — ns
RSi Setup Time TRS 10 — ns
Data Access Time TDA — 45 ns
Data Hold Time T DHR 10 — ns
Control Hold Time THC 10 — ns

Notes:

1. /CS and /RD must not both be continuously active.
A read or write operation following a read operation must be delayed by at least 2 XCLK cycle.

FM336 Signals Definitions (Cont’d)

3-15

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

Label I/O Type Signal Name/Description

IRQ OA

Interrupt Request. Interrupt request outputs may be connected to the host processor interrupt
request input in order to interrupt host program execution for immediate modem service. The IRQ
output can be enabled in DSP interface memory to indicate immediate change of conditions in the
modem. The use of IRQ is optional depending upon modem application.

The IRQ output structure is an open-drain field-effect-transistor (FET). The IRQ output can be wire­ORed with other IRQ lines in the application system. Any of these sources can drive t he host
interrupt input low, and the host interrupt servici ng process norm a l l y continues until all interrupt
requests have been serviced (all IRQ lines have returned high).

Because of the open-drain structure of IRQ#, an external pull-up resi stor to +3.3V is required at
some point on the IRQ line. The resistor value should be small enough to pull the IRQ line high
when all IRQ drivers are off (it must overcome the leakage currents). The resist or value s houl d be
large enough to limit the driver sink current to a level acceptable to each driver. If only the modem
IRQ# output is used, a resistor value of 5.6K ohms, 20%, 0.25 W, is sufficient.

D0-D7 IA/OB

Data Lines. Eight bi-directional data lines (D0—D7) provide parallel transfer of data between the
host and the modem. The most significant bit is D7. Data direction is cont rol l e d by the Read Enable
(READ#-¿2) and Write Enable (WRITE#-R/W#) signals.

During a read cycle, data from the DSP interface memory register is gated onto the data bus via
three-state drivers in the DSP. These drivers force the data li nes hi gh for a one bit, or low for a zero
bit. When not read, the three-state drivers assume their high-im pedance (off) state.

During a write cycle, data from the data bus is copied into the selected DSP i nterf ace memory
register, with high and low bus levels representing one and zero bit states, respectively.

RS0-RS4 IA/OB

Register Select Lines. Five active high Register Select inputs (RS0—RS4) address interface
memory registers within the DSP when /CS is low. These lines are typically connected to address
lines A0-A4.

When selected by /CS low, the DSP decodes RS0 through RS4 to address one of 32 8-bit internal
interface memory registers (00-1F). The most significa nt address bit is RS4 while the least
significant address bit is RS0. The selected register ca n be read from, or writt en i nto, vi a the 8-bit
parallel data bus (D0—D7).

OVERHEAD SIGNALS

VDD1 PWR 3.3V Supply Voltage for DSP Digital Circ uit s.
VSS DGND Digital ground.
VGG PW R 5V Supply Voltage for DSP Digital Circuits.
MAVSS AGND Analog ground.
MAVDD PWR 5V Suppl y Voltage for IA Analog Circuits.
VDD PWR 5V Supply Voltage for IA Digital Circuits.
VSUB GND Connect to analog ground.
XCLK OA

XCLK Output. Output clock at 63.5045 MHz, which runs during normal operational mode and
turned off during Sleep Mode.

YCLK OA

YCLK. Output clock at 28.224 MHz, which runs during normal operat ional mode and turned off
during Sleep Mode..

Label I/O Type Signal Name/Description

XTALI/CLKIN I/O

Crystal In/Clock In. Connect to an external 28.224 MHz crystal circuit or an external 28.224 MHz
oscillator circ

uit.

Label Crystal Oscillator

XTALI/CLKIN XTALI CLKIN

XTALO/NC I/O

Crystal Out/NC. Connect to the external crystal circuit return or leave open.
Label Crystal Oscillator

XTALO/NC XTALO NC
PLL_VDD PWR PLL Supply Voltage.
PLL_GND DGND PLL Supply Voltage return.
VCORE PWR 3.3V Supply Voltage. Connect to VDD1.
RESERVED - Reserved pins are used for future development and should not be connected to any circuitry.

FM336 Signals Definitions (Cont’d)

3-16

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-1-7 Scanner Part

CIS DRIVER, INPUT PROCESSOR

CIS contacl signal is consist of BLED, RLED, GLED, CIS_CLK CIS_SI. CIS driver power supply is +5v, LED driver power
supply is +5v also. As CIS input signal, minc-Vref values O, MAXC+Vref Values is about 1.2V.

SPECIFICATION

PIN FUNCTION DESCRIPTION

No. Signature Name Description

1 SIG signal output Video output signal
2 GND Ground 0V DC ; reference point
3 VDD Supply voltage +5V DC supply (ref. to GND)
4 GND Ground 0V DC ; reference point
5 GND Ground 0V DC ; reference point
6 SI Start pulse Start pulse
7 GND Ground 0V DC ; reference point
8 CLK Clock CIS main clock

9 LEDB LED Ground (blue) LED POWER SUPPLYBLUE
10 LEDG LED Ground (green) LED POWER SUPPLY GREEN
11 LEDR LED Ground (red) LED POWER SUPPLY RED
12 VLED Supply voltage LED POWER SUPPLY

Readable width 216mm
Number of sensor elements 2552 dots(21~2572 dots available)
Resolution 75 ms/line
Scanning speed 7.5 ms/line
Light source Color LEDs

Red (640 mm)
Green(525mm)

Blue(470mm)
Data output 1 analogue
Outward dimension(WXHXL) 18.0 X 12.2 X 231.0 mm (attachment)

3-17

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

ELECTRICAL CHARACTERISTICS (TA=25˚C)

CIS Driver Clock Timing

Item SYMBOL MIN. TYP . MAX. UNIT NOTE

Power Supply VDD 4.75 5.0 5.25 V

VLED 4.75 5.0 5.25 V

Input Voltage VIH 3.2 V SI & CLK

VIL 0.8 V

Input Current IIH 20 µA. SI & CLK

IIH 0.2 mA.

LED Current ILEDr 30 mA. REF.

ILEDg 60 mA. REF.

ILEDb 60 mA. REF.
Clock Frequency. CLK 2 MHz
Clock Pulse “L” Duty 15 % tw/to
Setup Time tsu 0 tw/2 ns
Hold Time th tw/2 ns
SIG Delay Time tpd 1 250 ns

tpd 2 30 ns
Sampling Reriod ts 90 ns

CLK

SIG

S1

tpd2

tpd1

tw

th

tsu

to

2nd1st

ts

3-18

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

ROD LENS ARRAY

SHIFT REGISER & ANALOG SWITCH

VLED

LEDR

LEDG

LEDB

VDD

GND

S1

OP AMP

SENSOR

CLK

SIG

12021

ST

2.5ms

1.2ms

1.2ms

1.2ms

1.2ms

7.5ms/line

OFF

OFF

OFF

B O/P R O/P G O/P B O/P R O/P G O/P

OFF

OFF

OFF

ON

ON

ON

LED_R

LED_G

LED_B

SIG O/P

CIS Block Diagram

3-19

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CIRCUIT DESCRIPTION

Repair Manual

3-1-8 HOST INTERFACE:

Parallel Port Interface

P ARALLELPORTINTERFACE PART KS32C61 100 has the Parallel Port Interface Part that enables Parallel Interface with
PC. This part is connected to PC through Centronics connector. It generates major control signals that are used to actu­ate parallel communication. It is comprised of/ERROR, PE, BUSY, /ACK, SLCT , /INIT, /SLCTIN, /AUTOFD and /STB. This
part and the PC data transmission method support the method specified in IEEE P1283 Parallel Port Standard
(http://www.fapo.com/ieee1284.html). In other words, it supports both compatibility mode (basic print data transmitting
method), the nibble mode (4bit data; supports data uploading to PC) and ECP(enhanced capabilities port: 8bits data - high
speed two-way data transmission with PC). Compatibility mode is generally referred to as the Centronics mode and this is
the protocol used by most PC to transmit data to the printer. ECP mode is an improved protocol for the communication
between PC and peripherals such as printer and scanner, and it provides high speed two-way data communication. ECP
mode provides two cycles in the two-way data transmission; data cycle and command cycle. The command cycle has two
formats; Run-Length Count and Channel Addressing. RLE (Run-Length Count) has high compression rate (64x) and it
allows real-time data compression that it is useful for the printer and scanner that need to transmit large raster image that
has a series of same data. Channel Addressing was designed to address multiple devices with single structure. For exam ­ple, like this system, when the fax/printer/scanner have one structure, the parallel port can be used for other purposes while
the printer image is being processed.This system uses RLE for high speed data transmission. PC control signals and data
send/receive tasks such as PC data printing, high speed uploading of scanned data to PC, upload/download of the fax
data to send or receive and monitoring the system control signal and overall system from PC are all processed through
this part.

3-20

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD

2. Host asserts nSTROBE low to indicate valid data

3. Peripheral acknowledges host by setting BUSY high

4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral

5. Peripheral sets BUSY low to indicate that it is ready for the next byte

6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low

PPD(7: 0)

nSTROBE

BUSY

nAC

K

DATA

COMPATIBILITY HARDWARE HANDSHAKING TIMING

PPD(7: 0)

nAUTOFD

nSTROBE

BUSY

BY TE0

BY TE1

COMM

AND

BY TE

DAT A BYTE

12345 6

ECP HARDWARE HANDSHAKING TIMING (FORWARD)

3-21

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

PPD

(7: 0)

BUSY

nACK

nAUTOFD

BY TE0

BY TE1

COMM AND BYTE

DAT A BYTE

12 3 4 56

nINIT

PE

78

ECP HARDWARE HANDSHAKING TIMING (REVERSE)

1. The host request a reverse channel transfer by setting nINIT low

2. The peripheral signals that it is OK to proceed by setting PE low

3. The peripheral places data on the data lines and indicates a data cycle by setting BUSYhigh

4. Peripheral asserts nACK low to indicate valid data

5. Host acknowledges by setting nAUTOFD high

6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host

7. Host sets nAUTOFD low to indicate that it is ready for the next byte

8. The cycle repeats, but this time it is a command cycle because BUSY is low

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CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

CS

RD VVR

A0/ALE

D[7:0]/AD[7:0]

INTR

MODE[1:0]

Microcontroller Interface

Endpoint/Contol FIFOs

Control

Status

RX

TX

RESET
Vcc

GND

XIN
XOUT

CLKOUT

48 MHz

Oscillator

Clock

Generator

SIE

Media Access Controller[MAC]

Physical Layer interface[PHY]

Trans ceiver

VReg

Clock

Recovery

USB Event

Detect

V3.3

AGND

D+

D-

Upstream Port

USB INTERFACE

• Full-Speed USB Node Device

• USB transceiver

• 3.3V signal voltage regulator

• 48 MHz oscillator circuit

• Programmable clock generator

• Serial Interface Engine consisting of Physical Layer In-terrace (PHY) and Media Access Controller (MAC), USB

Specification 1.0 compliant

• Control/Status Register File

• USB Function Controller with seven FIFO-based End-points :

- One bidirectional Control Endpoint 0 (8bytes)

- Three Transmit Endpoints (2*32 and 1*64 bytes)

- Three Receive Endpoints (2*32 and 1*64 bytes)

• 8-bit parallel interface with two selectable modes :

- non-multiplexed

- multiplexed (Inter compatible)

• DMAsupport for parallel interface

• MICROWIRE/PLUS Interface

• 28-pin SO package

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CIRCUIT DESCRIPTION

Repair Manual

CS
A0

VVR

RD

D[7:0]

DATA_IN

DATA_OUT

ADDR

DATA_IN

DATA_OUT

ADDRESS

0x00

0x3F
REGISTERFILE

NON-MULTIPLEXED MODE INTERFACE BLOCK DIAGRAM

NON-MULTIPLEXED MODE BASIC TIMING DIAGRAM

cs

A0

RD

VVR

D[7:0]

input

out

vvrte Address

Read Data

out

Burst Read Data

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Repair Manual

3-2 OPE PBA

3-2-1 SUMMARY

Scan

Position

Sensor

Document

Detect

Sensor

Connector

MICOM

HT48C5A

UART

Reset

11

7

X

Y8

RESONATOR

7.37 MHz

LCD

16x 1Line

Key Matrix

LEDs

OPE Board is separated functionally from the main board
and operated by the micom(HT48C5A) in the board. OPE
and the main use UART (universal asynchronous receiv­er/transmitter) channel to exchange information. OPE
reset can be controlled by the main.

OPE micom controls key-scanning and LCD and LED dis­play, detects documents and senses SCAN position. If
there occurs an event in OPE (such as key touch and sen­sor level change), it sends specific codes to the main to
respond to the situation and the main analyzes these
codes and operates the system.

For example, it the main is to display messages in OPE,
the main transmits data through UART line to OPE
according to the designated format and OPE displays this
on LCD, LED. OPE’s sensing is also transmitted to the
main through UART line and then the main drives neces-

sary operation.
OPE PBA consists of U1(MICOM, HT48C5A),LCD, key

matrix, LED indicators, SCAN position sensor and the
document detect sensor. Refer to OPE Schematic
Diagram and Wiring Diagram sections of this manual.

• Display from the controller is received at U2 pin 47
(RX DATA).

• LCD drive signals are sent from P1-x pin group, P1­4~P1-14 pins.

• Machine status LED drive signals are sent from U2
LED0~LED4.

• Document detect sensor output is received at U2 pin 1.

• Scan position sensor output is received at U2 pin7

<OPE BLOCK DIAGRAM>

3-25

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-3 LIU PBA

The LIU (Line Interface Unit) using the discrete method is comprised of the following.

(1) Tel_line Interface Circuit that connects the PSTN(exchange) and the system (Facsimile)
(2) Telephone circuit composed of dial/speech circuit.

3-3-1 Tel_Line interface Circuit

T el_Line Interface is the path that connects the signals between PSTN(exchange) and the system (Facsimile) and it is com ­prised of Tel-Line Interface Circuit and Impedance Matching Trans Circuit.

(1) TEL_LINE Interface Circuit
(2) TRANS Circuit for IMPEDANCE MATCHING

3-3-2 Telephone Circuit (Ringer/Dial/Speech Circuit, etc)

The telephone circuit is comprised of ring detect circuit, dialer circuit, speech circuit, external hook detect circuit and recall
circuit.

(1) Ring Detect Circuit
(2) Dialling Circuit (including MF Dialling Signal Transmitting Circuit)
(3) Speech Circuit
(4) External Hook Detect Circuit
(5) Recall Circuit

3-26

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-3-3 Detailed Spec.

TEL_LINE INTERFACE CIRCUIT

1) TEL_LINE INTERFACE CIRCUIT

• It is an interface that physically connects facsimile to the PSTN (public switching telephone network) through TIPand
RING as in fig. 1.

• ARS 1-3 protects the system from voltage overload such as the surge coming through PSTN. ARS 2 and ARS 3 are
used as overload protection in common mode (between TIP/RING and FRAME GROUND). ARS 1 is used as over­load protection in normal mode (between TIN and RING) and it uses ARREST OR for 600V. However, arrestor’s rated
voltage differs from European and USA(400v).

• CML(CONNECT MODEM to LINE) RELAYK1 is a switch designed to selectively connect the PSTN to system voice
communication path and fax communication path. In STAND_BY MODE and voice communication mode, it is con­nected to TEL PARTand FAX PART while communicating and dialing.

• CML Relay (K1): CML relay interfaces with T2(600:600) TRANS in communication mode.

• DC Impedance: DC impedance is determined in the DC Feeding Unit. It represents DC characteristic of the comput-

er connected through -48V DC power of the switch and lines. The DC characteristic of required by the communica­tion standards of a number of countries is the DC resistance of 50Ω~300Ω to the current range of 20mA~120mA.
(value varies depend on countries).

• AC Impedance or Return Loss: AC impedance is determined by the peripheral circuits of T2 T ransformer . It is the stan­dard required for optimum signal transmission between computer and switch. When the AC impedance of the com­puter for AC signal transmission and the AC impedance of the switch matches, the signal can be transmitted without
loss. Therefore, communication standards specifies the AC impedance of the computer and it implies the return loss.
The communication standards of each country , considering the characteristic of their lines, requires 600Ωor the return
loss of 14dB and higher against the AC impedance of Complex and the AC signals of 300Hz~400Hz. The AC imped­ance of transformer changes depending on the load resistance, the core material, coil inductance and resistance, but
generally its characteristic against load resistance is considered.

TIP

RING

ARS1

ARS2

ARS3

K1

to F AX
to TEL

FG

<TEL_LINE INTERFACE CIRCUIT>

3-27

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

RINGER DIAL CIRCUIT

1) Ringer Circuit

• The ring detect circuit detects the ring signal by sending the bell signal sent from PSTN to the primary photo coupler
(PC814). At this point, C(1uF/250V) is used to match the ring impedance and R is coupled directly in order to prevent
any damage to the photo coupler due to ring voltage.

2) Dialing Circuit

• Dialing circuit is initiated only when the power is on and it is transmitted to line through the modem of main part (T2
trans)

3) External Hook Detect Circuit

• In the discrete LIU method, the external hook detect circuit is designed to use both the photo coupler and current
detector in order to be used in all countries including the countries with low series resistance (Germany, Switzerland,
Belgium, Austria, etc.). T o use photo coupler (PC814), you must carefully select the resister connected parallel (75Ω)
to the photo coupler in order to satisfy the voltage drop standards of England and a few other countries. The diode
connected to the current detector pin (5/6) was used to detect the external hook all through when the line parity turns
over.

4) Recall Circuit

• In the discrete LIU method, we used the recalling method using low cost photo coupler instead of using photo MOS
relay in order to initiate the recalling for handset hook off dialling after the power is turned on. In this case, the time
break recall was enabled by switching the power transistor of the telephone circuit using the secondary CPU control.

3-28

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-4 Engine PPA

3-4-1 Engine Configuration

3-4-1-1. Video Controller Board

Video Controller Board receives image data from the host computer and converts it into bitmap (binary) image or receives
bitmap image directly from the host computer and sends it to the engine controller board.

3-4-1-2. SMPS Board

It basically receives AC input and generates ripple-free DC level +5V and -5V +24V. Next, it supplies these voltages to each
unit appropriately.

It also supplies AC power to heat lamp of fixing unit.

3-4-1-3. HVPS Board

HVPS board generates high voltages of THV/MHV/Supply/Dev and supplies them to the developing unit to create images.
It is designed to realize optimum conditions for the images.

This board includes LSU interface unit and cover open sensing unit that it intercepts +24V voltage to the main motor , LSU,
fan, clutch and fixing unit when you open the front cover.

3-4-1-4. Developer

Using the digital picture process, developing unit generates visible images. It is comprised of charge roller, OPC drum,
developer roller, supply roller and toner.

3-4-1-5. LSU (Laser Scanning Unit)

This is controlled by engine controller . Using laser beam control, exposure of OPC drum and the rotational principle of poly­gon mirror, it forms electro-static latent image in the OPC drum with the video data received from engine. It is the core part
of LBP. OPC drum synchronizes with the feeding speed of the paper and rotates. When the laser beam inside LSU reach ­es at the end of polygon mirror, it generates /HSYNC signal and send it to engine. Then the engine detects /HSYNC sig­nal and adjusts the lengthwise row of the image on the paper. After detecting /HSYNC and after set time period, it sends
the video data to LSU to adjust the left margin on the paper.

The one side of the polygon mirror is the one line scanned.

3-4-1-6. Transfer

Transcribing unit is comprised of PTL(pre-transfer lamp) and transcribing roller. PTL detects the beam of the OPC drum,
lowers the electric potential of the developing unit and lower the adhesiveness of toner to enhance transcription coefficient.

And the transcribing roller transfers the toner (constituting element of video image) on OPC drum to the paper.

3-4-1-7. Fixer

It is comprised of heat lamp, heat roller, pressure roller, thermistor and thermostat. It fixes the toner powder transferred to
the paper on the paper using pressure and high heat in order to finish the final printing job.

3-29

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-4-2. Developing Process

3-4-2-1 Feeder

Engine operates this unit. Solenoid rotates the feed roller and feeds one paper. Then the paper is fed into the set and hits
the actuator of the feed sensor. At this point, the engine detects the signal and prepares to spray according to the image
data. If any problem happens to this feed sensor operation, the system displays “paper jam error” on the OPpanel.

Also, feed sensor unit is closely related to the paper margin.

3-4-2-2. Electrifier

This unit electrifies consistent negative voltage to OPC. When the high negative voltage (-1550V) is allowed to charge roller ,
the OPC drum surface will be consistently electrified with approximately +1300V. This is the first process in generating the
digital picture.

3-4-2-3. Exposer

After receiving bitmap image data from engine board, LSU turns the laser diode either on or off depending on whether the
digital data is present or absent in order to expose the OPC drum with the switched laser beam data. The difference
between the voltages generated at this point is presented above. In other words, the part exposed to the laser will have ­50V and its relative electric potential will increase and form electrostatic latent image.

The part unexposed to the laser as it did not have the video data will consistently retain -800V. Eventually, the image will
form in the part electrified and rose to -50V(forms black dot) and the part retaining -800V will be white in order to make the
basic condition to form the video data.

LSU

2.Charging

7.Fixing

8.Exit

EXIT
SENSOR

6.Transfer

5.Pre-Transfer

FEED
SENSOR

3.Exposure

4.Development

1.Feeding

H/R

P/R

C/R

OPC

T/R

PTL

D/R

S/R

< Engine Operating Description >

3-30

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-4-2-4. Developer Unit

On the surface where OPC drum and developer roller (rotate in opposite direction) meet, the toner that has negative elec­tric characteristic moves to the exposed part (-50V) due to the electric potential difference, but it will not move to the unex ­posed part (-800V).

3-4-2-5. Transfer Unit

T oner on the OPC drum is transferred to paper by transfer unit. In other words, the toner on the OPC drum surface is induct ­ed by the transfer roller electrified to approximately +1.3KV(600~2800V variable) to the paper.
At this point, the voltage (600~2800V variable) is determined by temperature and humidity.
The above process is called “transfer”.

OPC

T/R

GND

1.3 KV

3-31

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-4-2-6. Anchorage unit

The toner transferred on to the paper is at the electronically low state and it can be easily scattered. Considering this fact,
we used heat (180°C) and pressure (4kg) to fix the toner on the paper permanently. Then the image formed will remain on
the paper permanently. Heat roller transfers the heat from the heat lamp inside to the paper. The surface of the heat roller
specially coated with Teflon repels toner melted by the heat from the surface.
The pressure roller on the bottom of the heat roller is made of silicon resin and its surface is also coated with Teflon. The
thermistor of the fixer unit detects the surface temperature of the heat roller and feeds this information back in order to retain
180°C while printing and 135°C, while on standby. The thermostat is used as the secondary safety device and it prevents
overheat by shutting the main power when the heat lamp
is overheated.

3-4-2-7. Exit

After the digital picture process is finished, the printed paper will come out of the set through the exit sensor. The signal
detected will be transferred to the engine and provide the position information. If the actuator and the sensor do not work
normally, the system will display “Paper Jam 2 Error”.

Heat Lamp

Heat Roller

Paper

Toner

Pressure

Roller

Spring

Thermistor

3-32

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

SWITCHING
CONTROL UNIT

TRANS

SWITCHING
CONTROL UNIT

SWITCHING
CONTROL UNIT

MHV-PWM

DEV-EA

SUPPLY-EA

REGULATION
CIRCUIT

OUTPUT
CIRCUIT

FEEDBACK

THVPWM

THVEA

THVREAD

PWM
CONTROL UNIT

SWITCHING
CONTROL UNIT

TRANS

SWITCHING
CONTROL UNIT

TRANS

FEED BACK

THV

REGULATION
CIRCUIT

REGULATION
CIRCUIT

THV
ENVIRONMENT
RECOGNITION
CIRCUIT

BIAS OUTPUT UNIT BLOCK DIAGRAM

TRANSFER OUTPUT UNIT BLOCK DIAGRAM

3-33

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-4-2-8. MHV (Electrification Output Enable)

Electrification Output Enable is the electrification output control signal 'PWM-LOW ACTIVE'.
When MHV-PWM LOW signal is received, Q401 turns on and the steady voltage will be accepted to the non-inverting ter­minal of OP-AMP 324. As the voltage higher than the inverting reference voltage of OP-AMP, which is set to R405 and
R406, OP-AMP output turns high.

This output sends IB to the TRANS auxiliary wire through current-restricting resistance Q402 via R408 and C403 and Q402
turns on. When the current is accepted to Q402, Ic increases to the current proportional to time through the T401 primary
coil, and when it reaches the Hfe limit of Q402, it will not retain the "on" state, but will turn to "of f". As Q402 turns 'of f', TRANS
N1 will have counter-electromotive force, discharge energy to the secondary unit, sends current to the load and outputs
MHV voltage through the high voltage output enable, which is comprised of Regulation– circuit.

MHV-PWM

U2 7407

R411 2.2K

18V

Q401 A708

R403 130K

R402
82K

R412 2K

R404
27K

C408
104

R406

2.2K

R405 220K

24VS

+

_

R408
47K

R409
390

KA324

C403
333

Q402
D526

24VS

T401

C404
3K/471

D402
4KV

C406
3K/471

R416
15M

R417
15M

MHV OUTPUT

3-34

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-4-2-9. BIAS (supply/dev output unit)

BIAS voltage output is generated only when electrification voltage is set to output. In the circuit presented above, it orga­nizes enough zener-diodes required to output dev/supply voltage from electrification output.

Supply voltage is output when the supply-ea signal is 'L'. When supply-ea is 'L', Q104 turns off and as Q105 does not turn
on, the electric potential of the output unit retains the electric potential of zener and thus -500V is output as the supply volt­age.

In case supply-ea signal is 'H', both Q104 and Q105 will turn on and the electric potential of the output unit will not retain
the electric potential of zener and become GND level and thus the output voltage will become .

The output condition of developer voltage is the same as that of the supply voltage.

MHV-PWM

U2 7407

R411 2.2K

18V

Q401 A708

R403 130K

R402
82K

R412 2K

R404
27K

C408
104

R406

2.2K

R405 220K

24VS

+

_

R408
47K

R409
390

KA324

C403
333

Q402
D526

24VS

T401

C404
3K/471

D402
4KV

C406
3K/471

R416
15M

R417
15M

MHV
OUTPUT

DEV-EA

24VS

R114
33K

R113
10K

R115 3.3K

R117 10K

R116

2.2K

Q106
C3198

Q107 A1413

R118
33K

C107
1K/101

ZD401 150V

ZD402 150V

ZD403 51V

DEV
OUTPUT

SUPPLY
OUTPUT

SUPPLY-EA

24VS

R107
33K

R106
10K

R108 33K

R112
2K

Q104
C3198

Q105 A1413

R109 10K

R110

2.2K

R111
33K

C106
1K/101

ZD404 150V

ZD405 150V

ZD406 100V

ZD407 100V

3-35

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-4-2-10. THV(THV(+)/THV(-) Output Unit)

Transfer(+) output unit is the transfer output control signal 'PWM-LOW ACTIVE'.
When THV-PWM LOW signal is received, Q203 turns on and the steady voltage will be accepted to the non-inverting ter-

minal of OP-AMP324. As the voltage is higher than the inverting reference voltage of OP-AMP, OP-AMP output turns high.
The 24V power adjusts the electric potential to ZD201 and ZD202, sends IB to TRANS auxiliary wire through current-

restricting resistance R215 via R212 and C204, and eventually Q204 will turn on. When the current is accepted to Q402,
Ic increases to the current proportional to time through the T201 primary coil, and when it reaches the Hfe limit of Q204, it
will not retain the "on" state, but will turn to "off". As Q402 turns 'off', TRANS N1 will have counter-electromotive force, dis­charge energy to the secondary coil, sends current to the load and outputs THV voltage through the high voltage output
enable, which is comprised of Regulation– circuit. The output voltage is determined by the DUTY width. Q203 switches
with PWM DUTY cycle to fluctuate the output by fluctuating the OP-AMP non-inverting end VREF electric potential, and
the maximum is output at 0% and the minimum, at 100%.Transfer(-) output unit is THV-EA'L' enable.

When THV-EA is 'L', Q302 turns on and the VCE electric potential of Q302 will be formed and sends IB to TRANS auxil­iary wire through R311, C305 and VR302 via current-restricting resistance R314, and eventually Q303 will turn on. When
the current is accepted to Q303, Q303's Ic increases to the current proportional to time through the T301 primary coil, and
when it reaches the Hfe limit of Q303, it will not retain the "on" state, but will turn to "off". As Q303 turns 'off', TRANS N1
will have counter-electromotive force, discharge energy to the secondary coil, send current to load and output THV(-) volt­age through the high voltage output enable, which is comprised of Regulation– circuit.

#7 TEV-PWM

5V

U2

12

3

R201
10K

U2

R205

1.8K

R206
100

Q203
A708Y

R208
30K

18V

R209
100KF

VR201
50K

R207
2K

C201
103

C202
121

R210
845KF

D202
1N4148

R211
1MF

5

6

7

+

_

U1

11

KA324

24VS

+

C101
35V47

UF

D201
1N4148

24VS

R213

2.2K

R212
680K

C203
472

D203
1N4148

ZD201

5.65V

ZD202
705V

R214

2.2K

C204
333Z

Q204
D526

T201
KAB-007

C206
3KV470pF

C205
2KV68pF

D204
4KV

D205
4KV

R215
390

C207
3KV470pF

R216
SBR306

R218
MGR1/2W100KF

R217
SBR207

#17
#19

#5

#24

5V

TEV-EA

TEV-READ

18V

R3
1/2W560

ZD1

5.6V

C7
104

D301
1N4148

5

6

7

U2
7407

D-GND

24VS

C4
103

8

9

10

U1

+

_

KA324

R301
470K

C301
222

R302
33K

R303
100KF

C302
102

D302
1N4148

C303
103

R304
389KF

R305
10KF

VR301
5K

R306

26.1KF

C304
500V103Z

18V

R309
202K

R307
33K

Q301
A708Y

18V

R310

2.2K

R308
33K

Q302
A708Y

R312
1W56

R313
1W56

Q303
D526

R311
100KF

C305
333Z

VR302
2K

R314

1.7K

KAB-006
T301

1

5

2

4

6

7

1

5

2

4

7

6

C307
3KW470pF

D304
4KV

C306
2KV68pF

D303
4KV

C308
3KV470pF

R315
SBR306

3-36

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-4-2-11. Environment Recognition

THV voltage recognizes changes in transfer roller environment and allows the voltage suitable for the environment in order
to realize optimum image output. The analog input is converted to digital output by the comparator that recognizes the envi ­ronmental changes of the transfer roller. It is to allow the right transfer voltage to perform appropriate environmental
response considering the environment and the type of paper depending on this digital output by the programs that can be
input to the engine controller ROM.

For ML-5000 or ML-5200 series, this environment recognition setting is organized as follows: First, set the THV(+) stan­dard voltage. Allow 200MΩload to transfer output, enable output and set the standard voltage 800V using VR201. Then
set 78 (CPU's recognition index value) as the standard using VR302. This standard value with CPU makes sure that the
current feedback is 4µA when output voltage is 800V and load is

200MΩ.If the load shows different resistance value when 800V is output, the current feedback will also be different and
thus the index value will also be different. according to the index value read by CPU, the transfer voltage output will differ
according to the preset transfer table.

The changes in transfer output required by each load is controlled by PWM-DUTY.

4

4-1

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4.Schematic Diagrams

4-1 Main Circuit Diagram (1/6)

APOLLO2(MAIN)

4-2

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-2 Main Circuit Diagram (2/6)

APOLLO2(MAIN)

4-3

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-3 Main Circuit Diagram (3/6)

APOLLO2(MAIN)

4-4

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-4 Main Circuit Diagram (4/6)

APOLLO2(MAIN)

4-5

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-5 Main Circuit Diagram (5/6)

APOLLO2(MAIN)

4-6

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-6 Main Circuit Diagram (6/6)

APOLLO2(MAIN)

4-7

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-7 LIU Circuit Diagram (1/2)

APOLLO2(LIU)

4-8

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-8 LIU Circuit Diagram (2/2)

APOLLO2(LIU)

4-9

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-9 OPE Circuit Diagram

APOLLO2 (OPE)

APOLLO2 (OPE)

CN1
GILS-5P-S2T2-EF

KA2-14P8-2.54DSA

P1

P1

P1

P1

P1

P1

P1

P1

P1

P1

P1

P1

P1

P1

D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)

U3
CD74HC14MX

10

U3
CD74HC14MX

+5V

14

7

GND5

D_DET

D_SCAN

C5
100nF

GND5

100nF

V16

12

V17

C21

GND5

U3
CD74HC14MX

2

3

5

U3
CD74HC14MX

10uF

R39

+5V

+5V

R2
22K

4

6

V1

C17

V2

16V

V3

V4

GND5

22K

GND5

+5V

R21
300

123

GND5

35

48

47

37

38

11

12

13

14

10

30

31

32

33

18

17

16

15

19

8

9

2

1

7

U2

_RESET

TXD

RXD

XTAL1

XTAL2

NC1

NC2

NC3

NC4

LCD_RS

LCD_RW

LCD_E

LCD_D0

LCD_D1

LCD_D2

LCD_D3

LCD_D4

LCD_D5

LCD_D6

LCD_D7

SENSOR

D_DET

D_SCAN

VSS

HT48R50

R22
300

4

U4
KPI-L05

+5V

36

VDD

20

_INT

21

TMR0

34

TMR1

6

LED0

5

LED1

4

LED2

3

LED3

46

LED4

45

LED5

44

LED6

43

LED7

39

NC5

40

NC6

41

NC7

42

NC8

22

KEY0

23

KEY1

24

KEY2

25

KEY3

26

KEY4

27

KEY5

28

KEY6

29

KEY7

D_SCAND_DET

C6
100nF

GND5

1

Q1
KSA1182-Y

3K

3K

R15

GND5

V9

V10

V11

V12

V13

V14

V15

R49

+5V

R10

R11
200 200

2

LED1

SLS-NNGR202TS

3

1

Q4

GND5

KSA1182-Y

TOLL PAPER POWER TONER E-MAIL

3K

3K

3K

R50

R51

R48

D1
MMSD914T1

05

04

03

02

01 06

D2
MMSD914T1

3

SW1

2

SW2

1

SW3

SW22

SW23

SW24

SW25 SW40

SW26

6

SW4

5

SW5

4 *

SW6

10

SW27

SW28

09

SW29

08

SW30

07

SW31

R44
200

2

SLS-NNGR202TS

3

15

14

13

12

11

Son-Hyun

+5V

R45
200

LED2

GND5

D3
MMSD914T1

9

SW7

8

SW8

7

SW9

SW32

SW33

SW34

SW35

SW36

Date Changed:Changed by:

+5V

R41

R40

200

200

2

1

20

19

18

17

16

Q2
KSA1182-Y

LED3

SLS-NNGR202TS

3

D4
MMSD914T1

V-REQUEST

#

SW10 SW16

0

SW11

SW12

TOLL

SW37

PAPER

SW38

POWER

SW39

TONER

SW41

GND5

D5
MMSD914T1

STOP

START/

Time Changed:

SW13

SW14

SW15

SW42

SW43

SW44

SW45

1

Q3
KSA1182-Y

SW17

REPORT/

HELP

Engineer:

Ho-Jin Park

Drawn by:

Ho-Jin Park

R&D CHK:

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK:

2

3

D6
MMSD914T1

COPY/ SEARCHOHD/

REPRINT

E-MAIL

<

REDIAL

RECALL

+5V

R43

R42

200

200

LED5

SLS-NNGR202TS

SW18

SW47

SW48

SW49

1

GND5

D7
MMSD914T1

/DELETE

SW19

>

SW20

ADVANCED FAX

SW21

SETUP

SW52

RCV-MODE/

SW53

CONTRAST

RESOLUTION

SW54

SAMSUNG ELECTRONICS

TITLE:

REV:

2.0

Q5
KSA1182-Y

Drawing Number:

R47

R46

200

200

2

LED4

SLS-NNGR202TS

3

D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)

R7
22K

R6
22K

R5
22K

R4
22K

R36
22K

R8
22K

R9
22K

R3
22K

+5V

GND5

+5V

Size:

E

Page:

1

GND5

U3
CD74HC14MX

200R38

C15
47pF

C16
47pF

CSA7.37MTZ-TF01

GND5

R18

300

3

C

U5
ITR-9702/F2

E42K

11

13

1

X1

+5V

1

2

3

4

5

1

+5V

2

R35
10K

3

R34

C12

680

100nF

GND5

4

5

6

7

8

9

10

11

12

13

14

R1 200

C1
100pF

C14
100nF

+5V

R37
22K

8

GND5

GND5

U3

CD74HC14MX

C18
220pF

GND5

C19
220pF

C13
10uF

16V

9

GND5

C20
220pF

GND5

+5V

R19
300

1

A

GND5

4-10

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-10 Scan Circuit Diagram (200DPI)

APOLLO2(200DPI)

4-11

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-11 Scan Circuit Diagram (300DPI)

APOLLO2(300DPI)

4-12

SCHEMATIC DIAGRAMS

Samsung Electronics

Repair Manual

4-12 HVPS Circuit Diagram (1/2)

R512

430

1

2

5V

24VS

R405

220KF

MHV-PWM

SIZE A4

U3

R503

100

ZD401

1W 130V

R416

MGR1/2W 15MF

R515

MGR1/2W 6MF

+

-

U1-C

KA324

10

9

8

D501

1N4148

R508

86.6KF

R504

2K

C405

2KV 680

OUT

R516

MGR1/2W 50K

+

C3

35V 47uF

D402

4KV

MHV

R505
100KF

VR501

50K

R514

MGR1/2W 15MF

DRW. NO

C501

104

R520

MGR1/2W 9MF

D-GND

18V

Q501

A708-Y

R502

2.2K

APPROVED

GND

R519

MGR1/2W 50K

R506

86.6KF

Q1

B1151-Y

REV.

IN

R513
1W 3

Q502

D526-Y

R510

47K

Q401

A708-Y

THV-EA

C403

333

5V

R422

5.6K

R2

1K

R401

100

THV-PWM

CHECKED

D502

4KV

R4

1W 1K

24VS

C404

3KV 471

Q402

D526-Y

R1

5.6K

DESIGNED

R410
1W 3

R509
12KF

D404

1N4148

R403

110KF

D401

4KV

+

-

U1-D

KA324

12

13

14

Q2

C1008-Y

R411

2.2K

DEV

THV-READ

R3

100

R414

MGR1/2W 6MF

T501

T1167

1

4

2

5

7

6

J.S.YOUN

C504

333

1 OF 2

R413
MGR1/2W 6MF

SUPPLY

18V

C503

104

2.0

D403

1N4148

C1

104

C402

103

R408

47K

T401

KAB-006

1

4

2

5

7

6

R507

27K

R409

430

U2-A

R407
240K

C408

104

MHV-PWM

OPC

C2

104

C506

3KV 471

18V

R501

5.6K

R402
56KF

CN1-#7

REF. NO

C401

331

5V

R517

MGR1/2W 6MF

C505

2KV 680

U2-B

BIAS-PWM

TITLE

R404

33K

A-GND

7407

C406

3KV 471

VR401

50K

BIAS-PWM

3

4

GIL-S-9P-S2T2-EF

CN1

1
2
3
4
5
6
7
8
9

CN1-#6

7407

24V

R518

MGR1/2W 9MF

R426

MGR1/2W 100KF

24VS

R511

47K

KA7818

C502

222

24VS

R406

2.2KF

ZD501

1W 200V

R417

MGR1/2W 15MF

R412

2K

DONGYANG INSTRUMENTS

APOLLO2 (HVPS)

4-13

Samsung Electronics

SCHEMATIC DIAGRAMS

Repair Manual

4-13 HVPS Circuit Diagram (2/2)

C301

222

C4

104

APPROVED

R218

MGR1/2W 100KF

R309

2.2K

TITLE

18V

7407

R316

1KF

R211

1MF

VR302

5K

11 10

CHECKED

ZD202

7.5V

R305

6.2KF

CN1-#8

7407

+

C101

35V 47uF

R304

200KF

DESIGNED

CN1-#4

R303

100KF

U2-E

Q302

A708-Y

+

-

U1-B

KA324

5
6

7

R314
3KF

R315

BR1/2W 30MJ

2 OF 2

CN1-#5

Q203

A708-Y

Q303

D526-Y

R215

430

D301

1N4148

R206

100

C207

6KV 471

THV-EA

R214

1.2K
R217

BR1/2W 200MG

5V

U2-F

R301

470K

R307

33K

C305

333

J.S.YOUN

D204

6KV

C209

6KV 471

R306

26.1KF

3.0

24VS

R216

BR1/2W 30MJ

VR301

10K

R311

100KF

7407

VR201

50K

D304

4KV

REV.

D201

1N4148

C308

3KV 471

D-GND

R209

110KF

ZD201

5.6V

THV

CN1-#3

Q301

A708-Y

C302

102

R205

1K

D202

1N4148

T201

HVT-2A

1

4

2

5

7

6

D303

4KV

C205
6KV 101

D302

1N4148

D203

1N4148

R210

510KF

C306

2KV 680

R201

10K

D207

6KV

C208

6KV 471

C304
500V 103

13

12

C307

3KV 471

D206

6KV

R308

33K

SIZE A4

C203

472

+

-

U1-A

KA324

3
2

1

4

11

C201

103

5V

C303

333

THV-PWM

R317

2KF

R208
30KF

THV-READ

R212
470K

R207

2K

R213

2.2K

24VS

C202

331

1/2W

D205

6KV

REF. NO

U2-C

9 8

14

7

C206

6KV 471

18V

T301

KAB-006

1

4

2

5 6

7

24VS

R302

33K

500V

DRW. NO

18V

DONGYANG INSTRUMENTS

C204

473

Q204

D526-Y

R310

2.2K

APOLLO2 (HVPS)