Samsung SF4300 Circuit Descriptions

Samsung Electronics 5-1

5. CIRCUIT

5-1 MAIN PBA

5-1-1 SUMMARY

The main circuit that consists of CPU, MFP controller (built-in RISC processor core:
ARM7TDMI) including various I/O device drivers, system memory, scanner, printer,
motor driver, PC I/F, and FAX transceiver controls the whole system. The entire
structure of the main circuit is as follows:

Fig.5-1-1. Entire Structure of Main Circuit for Each Key Signal

LIU-TXD

MCLK(30MHz)

/POR

/ROMCS

/RD, /WR

D0~D15

D0~D15

D0~D7

A0~A17

A0~A9

A0~A4

/RST-OUT

PD0~PD7

/P-ERROR

/P-PE

/P-BUSY

/P-ACK

/P-SLCT

/P-INIT

/P-STB
245DIR

/P-SLCTIN

/P-AUTOFD

/MCS

/MIRQ

/RD, /WR

/RASO, 1

/WR

/UCAS,

/LCAS

/F-POR

LIU-RXD

IP-CLK

/XDACK

/XDREQ

/IP-CS

/RD, /WR

D0~D15

A0~A4

LFPHA

MFP CONTROLLER

(KS32C6200)

LFPHB

LFIA0
LFIA1

LFIB0
LFIB1

CR-REF

CRPHA
CRPHB

CRIA0
CRIA1
CRIB0
CRIB1

/HEAD-EN

HEAD-DATA

/HGA1~/HGA13

HOE1~HOE16

OK2PRINT

/FAULT-TEST

BIASOFF

/RST-OUT

/RST-OUT

LIU (STI9510)

COKOR IMAGE

PROCESSOR

FLASH

MEMORY

DRAM

MODEM

PARALLEL

INTERFACE

(IEEE1284)

LF MOTOR

DRIVER

CR MOTOR

DRIVER

PRINT HEAD’

DRIVER &

PRINT

CONTROL

CIRCUIT

5-2 Samsung Electronics

MFP Controller consists of CPU(ARM7TDMI RISC processor), 2K-byte cache, data and address buses, serial
communication part with LIU(Line Interface Unit), print head controller, parallel port interface, external
DMA part to receive data from external color image processor (CIPIA:U17), LF/CR motor diver controller and
I/O controller.

5-1-2-1. SYSTEM CLOCK

The internal clock frequency is 30MHz. 30MHz system clock (MCLK) supplied from the outside is used with­out being divided inside.

5-1-2-2. DATA & ADDRESS BUS CONTROL

¥ /RD & /WR

/RD & /WR signals are synchronized with MCLK(30MHz) and become LOW ACTIVE.
These signals are strobe signals used to read and write data when each CHIP SELECT is connected with
/RD and /WR pin of RAM, ROM, MODEM and the outside devices and becomes active.

¥ CHIP SELECT (/CSO, /ROMCS, /MCS)

- /IP-CS : CIP1A(U17) CHIP SELECT (LOW ACTIVE)

- /ROMCS : ROM/FLASH MEMORY(U10) CHIP SELECT (LOW ACTIVE)

- /MCS : MODEM(U21) CHIP SELECT (LOW ACTIVE)

When each CHIP SELECT is low, data can be read or written.

¥ D0 - D15

- 16bit data bus

¥ A0 - A17

- ADDRESS BUS (A18 - A21 are reserved.)

5-1-2 MFP CONTRLLER (KS32C6200 : U15)

Samsung Electronics 5-3

UART (Universal Asynchronous Receiver/Transmitter) at KS32C6200 enables the main and LIU to transmit
serial data. The block diagram of UART is as follows: (Fig.5-1-2) KS32C6200 has 2 UART channels. Channel
0(RXD0, TXD0) is used here and the baud rate is 9600bps.

5-1-2-3, LIU(Line Interface Unit) SERIAL COMMUNICATION PART

TxD

TxD

RxD

IRS

RE

IR Tx

Encoder

IR Rx

Decoder

0

0

1

1

RxD

UART

Block

Fig.5-1-2. UART BLOCK DIAGRAM

TXD :

START D0 D1 D2 D3 D4 D5 D6 D7 STOP

RXD :

START D0 D1 D2 D3 D4 D5 D6 D7 STOP

Fig.5-1-3 UART DATAFORMAT

START, STOP : 1BIT EACH
BAUD RATE : 9600bps
CPU I/F : SUPPORTS BOTH INTERRUPT & POLLING DRIVEN
PARITY : NO

5-4 Samsung Electronics

It brings data from an external device (CIP1A:U17) using DMA channel 0. DMA REQUEST sent from an
external device to KS32C6200 activates DMAACKNOWLEDGE signal and drives DMAchannel 0 to produce
CHIP SELECT and READ STROBE (/RD) at the external device and bring data from it. It generates address
of destination memory, CHIP SELECT and WRITE STROBE (/WR) in order to move this data into
destination memory, and then stores the data.

5-1-2-4 External DMA

MCLK

/XDREQ

/XDACK

D[15:0]

/RD

/WR

Fig.5-1-4 EXTERNAL DMA TIMING DIAGRAM

Samsung Electronics 5-5

As KS32C6200 has DRAM controller in it, DRAM can be connected with external memory. The control mode
of DRAM controller enabling EARLY WRITE, NORMAL READ, PAGE MODE, and BYTE/HALF WORD
ACCESS supports EDO DRAM as well as normal DRAM. DRAM READ/WRITE signals are /RD and /WR
signals used to control system buses. It supports CAS BEFORE RAS for DRAM REFRESH and self-refresh
mode for DRAM backup. Connected with common /LCAS, /UCAS and RAS[1:0], it consists of 2 banks.
Though each may be connected with up to 1M - 4M halfword, 512 Kbytes or 2 Mbytes are connected accord­ing to the model for this product.

5-1-2-6. PARALLEL PORT INTERFACE

This part connected with the computer through the centronics connector makes possible parallel interface
with the computer. Data is transmitted according to the standard of IEEE P1284. This MFP controller supports
compatibility mode the traditional way to transmit print data, nibble mode (4bit data) to upload data to the
computer, and duplex high-speed transmission with the computer ECP(Extended Capabilities Port: 8bit data
transmission) all together.
It enables PC data to be printed and scanned data to be uploaded quickly to the computer. Besides, various
data transmission and reception with the computer such as uploading received fax data, downloading fax
data to be sent, and monitoring system control signals and system conditions are carried out here.

5-1-2-5. DRAM CONTROLLER

PPD(7 : 0)

DATA

BUSY

nSTROBE

nACK

Fig.5-1-5 Compatibility Hardware handshaking Timing

5-6 Samsung Electronics

nSTROBE

BUSY

PPD(7 : 0)

nAUTOFD

BYTE0

DATA BYTE COMMAND BYTE

BYTE1

Fig.5-1-6 ECP Hardware Handshaking Timing (forward)

nACK

nAUTOFD

PPD(7 : 0)

BUSY

nINIT

PE

BYTE0

DATA BYTE COMMAND BYTE

BYTE1

Fig.5-1-7 ECP Hardware Handshaking Timing (reverse)

Samsung Electronics 5-7

This part produces major control signals used to drive INKJET head. It consists of signals to drive head noz­zles, /PHGA[13:1], PHOE[16:1], /FAULT-TEST, /HEAD-EN, and BIASOFF, and consists of signals to check
the status of the head, OK 2PRINT and HEAD-DATA.
It has double height print head system, 208 nozzles for mono and 192 nozzles for color, and uses
/PHGA[13:1], /PHOE[16:1] signals and /HEAD-EN to drive these nozzles. Fig.5-1-8 is timing diagram of
each signal.

5-1-2-7. INKJET HEAD CONTROLLER

/PHGA

Signal

PHOE

Signal

Fire Enable Timer

Pre-Heat Pulse Width

Front End Delay Back End DelayPr-Heat Delay Width

Fire Pulse Width

t

p (PD)

Fig.5-1-8 Timing Diagram to Drive Head

5-8 Samsung Electronics

/HEAD-EN

/PHGA1
/PHGA2

/PHGA3
/PHGA4

/PHGA5
/PHGA6

/PHGA7
/PHGA8
/PHGA9

/PHGA10
/PHGA11

/PHGA12
/PHGA13

(Tp)

PHOE1-

PHOE16

Fig.5-1-9. Timing Diagram for Each Nozzle

The above control signals are sent to head driver and the head driver converts these signals to the level
(+11.75V) to drive head nozzles.

5-1-2-8. MOTOR CONTROLLER (CRPHA, CRPHB, CRIA0, 1, CRIB0, 1, LFPHA, LFPHB, LFIA0, 1, LFIB0, 1)

MFP Controller (KS32C6200:U15) supports 2 stepper motors. It controls CR(Carriage Return) motor used to
read and print documents and LF (Line Feed) motor used to feed and eject paper.
CR motor controller can support 75, 150, 200, 300, 600, or 1200dpi according to resolution, while LF motor
controller supports uni-polar and bi-polar according to the kind of motors. Though full step, half step and soft­ware control are possible for both, bi-polar CR motor is controlled half step and LF motor is controlled half
step and quarter step here.

Samsung Electronics 5-9

5-1-2-9. I/O PORT OF KS32C6200

PIN NAME

CIRCUIT NAME

I/O STATE DESCRIPTION

TXD 0 /GOP 0 LIU-TXD 0 - UART DATA TO I-LIU CHIP IN LIU

TXD 1 /GOP 1 - 0 - UNUSED

/EDACK /GOP 2 /XDACK 0

H DEFAULT STATE

L DMA ACKNOWLEDGE

TONE / GOP 3 KEYCLICK 0 - BEEP TONE

/RSTO / GOP 4 /RESET 0

H WATCHDOG RESET OUT IS INACTIVE

L WATCHDOG RESET OUT IS ACTIVE

/IOWR 1 / GOP 5 /FAULT-TEST 0

H DEFAULT STATE

L CHECK FAULT IN PRINTHEAD

/IOWR 2 / GOP 6 RX-CTL 0

H MODEM RX PATH CONNECTION

L

REMOTE START DETECTION PATH CONNECTION

/IORD 1 / GOP 7 /HEAD-EN 0

H PRINTHEAD IS DISABLE

L PRINTHEAD IS ENABLE

/IORD 2 / GOP 8 TONE-CTL 0

H MONITORING TX/RX SOUND

L BEEP SOUND

CLKOUT / GOP 9 IP-CLK 0 - CIP CLOCK

FIREPS / GOP 10 /RST-OUT 0

H EXT. CHIP IS ACTIVE

L EXT. CHIP IS RESET

/HSC / GOP 11 BIASOFF 0

H PRINTHEAD BIAS OFF

L PRINTHEAD BIAS ON

/HSM / GOP 12 CR-REF 0

H PRINT MODE IS LQ

L PRINT MODE IS DRAFT

5-10 Samsung Electronics

PIN NAME

CIRCUIT NAME

I/O STATE DESCRIPTION

RXD 0 / GIP 0 LIU-RXD I - UART DATA FROM I-LIU CHIP IN LIU

RXD 1 / GIP 1 /P-EXIT I

H PAPER IS NOT DETECTED

L PAPER IS DETECTED

/EINT 1 / GIP 2 /MIRQ I

H NO INTERRUPT FROM MODEM

L INTERRUPT FROM MODEM

/EINT 2 / GIP 3 OK2PRINT I

H NO FAULT IN PRINTHEAD

L FAULT IN PRINTHEAD

/EDREQ / GIP 4 /XDREQ I

H NO DMA REQUEST FROM CIP

L DMA REQUEST FROM CIP

UCLK / GIP 5 HEAD-DATA I - CODE DATA FROM PRINTHEAD

TCK / GIOP 0 TCK I/O - TEST PIN FOR EMULATOR (CLOCK)

TMS / GIOP 1 TMS I/O - TEST PIN FOR EMULATOR (DATA MODE)

TDI / GIOP 2 TDI I/O -

TEST PIN FOR EMULATOR (DATA FROM EMULATOR)

/TRST / GIOP 3 /TRST I/O -

TEST PIN FOR EMULATOR (RESET TO TAP CON.)

TDO / GIOP 4 TDO I/O -

TEST PIN FOR EMULATOR (DATA TO EMULATOR)

Samsung Electronics 5-11

As for SMARTJET there are 2 power resets of primary reset(/F-POR) and secondary reset(/POR) and also
reset by watchdog timer (/RSTO). Primary reset is used to initialize flash memory when the system is turned
on, while secondary reset is used to initialize the whole system by initializing MFP controller (KS32C6200)
after primary reset. Primary reset makes flash memory wait in READ mode to fetch program codes, and sec­ondary reset makes the main controller (KS53C6200) wake up and initialize external peripherals to operate
the system. Fig.5-1-10 is Power Reset Timing Diagram.

5-1-2-10. RESET CIRCUIT

supply

Voltage

/F-POR

/POR

PnRST

Internal Reset

256 MCLK

Reset filter

65 MCLK

ROM Access

(internal)

Reset

Fig.5-1-10 POWER RESET TIMING DIAGRAM