Samsung SF 3000, SF3000T Schematic
7. Circuit
CPU (Logical) Address Space
FFFFFF
FC0000
ROMCSn
CAS0
CAS1
CAS2
C00000
400000
800000
000000
MCSn
Internal
Registers
CS2n CS4n
CS1n
Internal
Memory
00FFFF
00FF00
00FE00
00FD00
00FC00
00E000
Reserved
Setup
Registers
Operational
Registers
CS4n
CS3n
CS2n
Reserved
Shading Inversion
DBCMC Buffer
Dither Table
Reserved
00FEFF
00FEE0
00FE80
00FE00
00FDFF
00FDC0
00FD80
00FD00
00FBFF
00FBE0
00FBD0
00FBC0
00FB80
00E000
7-1. Circuit Description
7-1-1. General
The main circuit board consists of a Jupiter-2 Chip (KS32C6500), memory, TX- and RX-related circuitry, and
some portions of the Line interface Unit, and controls the system.
7-1-2. System Control Part
This circuit consists of the EP-ROM and SRAM, External Real Time Clock crystal, RTC and memory back-up,
and the Jupiter-2 Chip (KS32C6500). The Jupiter-2 Chip is an integrated 14400bps modem, image processor, 16bit MPU, peripheral control, and analog front end circuit on a single-chip.
The modem is 14400 bps half duplex. It is a monolithic device incorporating an over sampling Σ∆ AFE, digital
filters, a digital signal processor (SDIP4) and CPU-Interface logic.
Memory Map
The external memory of the CPU is divided into 32kB RAM (0000H through 7FFFH), 512kB ROM (FC0000H
Figure 7-1 KS32C6500 External Memory Map
Samsung Electronics 7-1
Circuit Description
OPERATING
PANEL
SERIAL
COMMUNICATION
HEAD
DRIVER
RTC
CRYSTAL
(32, 768KHZ)
SDIP4 TAD PART
KS32C6500
MOTOR
DRIVER
(CR, LF
MOTOR)
DATA
MEMORY
(SRAM)
PROGRAM
MEMORY
(EPROM)
DRAM.
(USER MEMORY)
GENERAL
PURPOSE I/ 0
TXD
A0~A5
D0~D15 D0~D7
CONTROL
RXD
PHINA~D
CONTROL
+24
XIN
ONLY SF3000T
XOUT
/DMS
/RD/WR
D0~D7
A0~A14
/RD
/LCAS
/RASO~
/UCAS
D0~D15
A0~A17
/A16
/PMS
/RD/WR
D0~D7
A0~A4
/RESET
/RESTO
MODEM
Jupiter-2 Chip
KS32C6500 internal logic generates chip select
signals for both memory chips and peripherals. To
support external access, from one to three wait
cycles can be inserted under program control during
external accesses. A chip select signal line goes
active (low) whenever its corresponding device is
accessed over the external interface. The peripheral
addresses are located in data memory.
/SRAMCS : SRAM chip select active (low)
/ ROMCS : EP-ROM chip select active (low)
D0–D15 : 16 bit data bus
A0–A17 : address bus
System Clock
The 30 MHz internal system clock frequency is
supplied by an external clock generator.
Figure 7-2 Hardware Interface Signals
7`-2 Samsung Electronics
32.768 KHz
15 BIT
PRESCALER
1HZ CO=60 CO=60 CO=24
6 BIT
SECONDS
6 BIT
MINUTES
5 BIT
HOURS
BUSY
DETECT
5 BIT
DAYS
4 BIT
MONTHS
5 BIT
YEARS
MONTH
DECODER
LEAP YEAR
DECODER
3 STATE
DRIVER
BUSY FLAG CLEAR BUSY FLAG
CO=28,29,
30,or 31
CO=12
Circuit Description
CPU Bus
SclkCtrlLo
SclkCtrlHi
Baud Gen (8x)
Tx/Rx Control
IRQ control
SARTCmd
Internal Register
SartlRQ
SCLK
RXD
TXD
RxShift Reg
(SARTData)
RxBuffer
(SARTData)
TxShiftReg
JUPITER - 2
Real Time Clock (RTC)
The circuit receives clock pulses from an external 32.768 kHz crystal, which it divides into hours, minutes,
seconds, year, month, and day. A battery maintains operation when power is off. KS32C6500 can up-track 100
years, begining with 1998.
Figure 7-3 RTC Block Diagram
Operation Panel Control
A Synchronous/Asynchronous Receiver/Transmitter (SART) controls serial data transmission between the
main circuit and the operator panel.
. Serial Communication Signals
The KS32C6500 has two full-duplex serial communication ports. One port is used for I-LIU communication,
Figure 7-4 SART Block Diagram
and the other for OPE communication.
Samsung Electronics 7-3
Circuit Description
Reset
To initialize the chip’s internal logic, the reset input
(/RESET) must be held to 0 Volt for at least 22 CPU
clocks. During this time, Vdd must be greater than 3
volt. The watchdog timer can also invoke a system
reset.
[+5V Power Monitoring]
If 5 Volt power to KIA7045P drops to between 4.65V
and 4.35V (typically 4.5V), power failure will be
indicated and the output of KIA7045P will go ‘low’
(GND5). This causes the KS16118 to become active
(‘low’=reset).
The KS32C6500 reset causes the /RESET terminal to
be reset. The output terminal of KIA7045P is an
open-drain configuration, and is connected to
KS32C6500 through a 10 kohm pull-up resistor.
Carriage Return Motor Driver
The CR motor drives the head in two directions to
print data on the recording paper.
Motor type : Step Bipolar
Operation Voltage : +24V DC
Resistance : 5 ohm +/-10%
IC : PBL3717 x2EA
STEP MOTOR DRIVER OUTPUT SIGNAL
Standby Full Step
CRIAO
CRIA 1
PHA
PHB
CRIBO
CRIB 1
500mA
IMA
-500mA
500mA
IMB
-500mA
INPUT
OUTPUT
Line Feed Motor Driver
The LF motor feeds paper in and out.
Motor type : Step Unipolar
Operation Voltage : +24V DC
Holding Voltage : +5V DC
Resistance : 50 ohm ±10%
IC : STA471A
Head Nozzle Driver
The nozzle control circuit is composed as follows:
Number of nozzle : 56 nozzles for mono
Driving Voltage : +24V DC +/-2%
Driving Pulse Width : 3.6 us for mono
Operation Frequency : 5 kHz
Resistance : 30 ohm for mono
IC : SGS Thomson L6451 or Allegro A5817
The IC decodes four input signals (PHINA, PHINB,
PHINC, PHIND) and enables the selected using
OEA and OEB signal input.
IND INC INB INA N
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1 1 1 0 ALL OFF
1 1 1 1 ALL OFF
Table 7-1 Nozzle Driver Signal
Figure 7-5 Step Motor Drive
7-4 Samsung Electronics
1
5
10
15
20
25
30
35
40
120
115
110
105
100
95
90
85
80757065605550
45
125130135140145150155160
KS32C6500
160 QFP
(Top View)
PHADR11
PHADR10
PHADR9
PHADR8
PHADR7
PHADR6
PHADR5
GND1
HOE12
HOE11
HOE10
HOE9
HOE8
VDD1
HOE7
HOE6
HOE5
HOE4
HOE3
HOE2
HOE1
GND2
DC_CRIA0
DC_CRIA1
CRIB0
CRIB1
PORT0
PORT1
PORT2
??????????
??????????
GOP12/nHSM
HOE16/HOED?
HOE15/HOEC?
HOE14/HOEB?
HOE13/HOEA?
PHADR4/ PHIND
PHADR3/ PHINC
PHADR2/ PHINB
PHADR1/ PHINA
nECS3
nECS2
nECS1
nECS0
nWBE1
nWE
nOE
nCAS1
nCAS0
nRAS1
nRAS0
nRCS2
nRCS1
nRCS0
VDD4
VDDR21
VDDR20
VDDR19
VDDR18
VDDR17
VDDR16
VDDR15
VDDR14
VDDR13
VDDR12
VDDR11
VDDR10
VDDR9
VDDR8
VDDR7
VDDR6
VDDR5
VDDR4
VDDR3
VDDR2
VDDR1
VDDR0
GND5
nWBE0
GND6
V
D
D
3
D
A
T
A
1
5
D
A
T
A
1
4
D
A
T
A
1
3
D
A
T
A
1
2
D
A
T
A
1
1
D
A
T
A
1
0
D
A
T
A
9
D
A
T
A
8
D
A
T
A
7
D
A
T
A
6
D
A
T
A
5
D
A
T
A
4
D
A
T
A
3
D
A
T
A
2
D
A
T
A
1
D
A
T
A
0
V
D
D
2
P
P
D
0
P
P
D
1
P
P
D
2
P
P
D
3
P
P
D
4
P
P
D
5
P
P
D
6
P
P
D
7
G
N
D
3
n
S
T
R
O
B
E
n
A
U
T
O
F
D
n
S
L
C
T
I
N
n
I
N
I
T
S
E
L
E
C
T
n
A
C
K
n
F
A
U
L
T
P
O
R
T
4
P
O
R
T
3
B
U
S
Y
P
E
R
R
O
R
2
4
5
C
L
K
G
N
D
4
P
H
A
D
R
1
2
P
H
A
D
R
1
3
G
O
P
7
/
n
I
O
R
D
1
G
O
P
1
0
/
F
I
R
E
P
U
L
S
E
G
O
P
6
/
n
I
O
W
R
2
G
O
P
9
/
C
L
K
O
U
T
G
O
P
8
/
n
I
O
R
D
2
G
O
P
4
/
n
R
S
T
O
G
O
P
3
/
T
O
N
E
G
N
D
9
E
E
C
L
K
E
E
D
A
T
A
L
F
P
H
A
S
E
B
P
H
B
I
B
0
P
H
A
I
A
1
P
H
A
Z
I
A
1
P
H
B
Z
I
B
0
G
O
P
1
1
/
n
H
S
C
V
D
D
R
T
C
R
X
O
R
X
I
L
F
C
O
N
P
H
A
G
O
P
2
/
n
E
D
A
C
K
G
O
P
4
/
n
E
D
R
E
Q
G
O
P
3
/
n
E
I
N
T
2
G
O
P
2
/
n
E
I
N
T
1
G
O
P
5
/
n
I
O
W
R
1
V
D
D
5
G
N
D
8
M
C
L
K
G
N
D
7
n
R
E
S
E
T
C
L
K
S
E
L
G
I
P
5
/
U
C
L
K
T
E
S
T
2
T
E
S
T
1
G
I
P
1
/
R
X
D
2
G
I
P
1
/
R
X
D
2
G
I
P
0
/
R
X
D
1
G
I
P
0
/
R
X
D
1
Circuit Description
Jupiter-2 (KS32C6500) Pin Layout Diagram
Samsung Electronics 7-5
Figure 7-6 Pin Layout Diagram
Circuit Description
Jupiter-2 ASIC(KS32C6500) Pin Description
Pin No. KS32C6500 ATLAS used pin Pin Description
1 _PHGA11 NOT-USED
2 _PHGA10 NOT-USED
3 _PHGA9 NOT-USED
4 _PHGA8 NOT-USED
5 _PHGA7 NOT-USED
6 _PHGA6 NOT-USED
7 _PHGA5 NOT-USED
8 _PHGA4 PHIND INK NOZZLE ENABLE CONTROL SIGINAL
9 _PHGA3 PHINC INK NOZZLE ENABLE CONTROL SIGINAL
10 _PHGA2 PHINB INK NOZZLE ENABLE CONTROL SIGINAL
11 _PHGA1 PHINA INK NOZZLE ENABLE CONTROL SIGINAL
12 GND1 GND1
13 PHOE16 _HOED INK NOZZLE DECODING SIGNAL
14 PHOE15 _HOEC INK NOZZLE DECODING SIGNAL
15 PHOE14 _HOEB INK NOZZLE DECODING SIGNAL
16 PHOE13 _HOEA INK NOZZLE DECODING SIGNAL
17 PHOE12 NOT-USED
18 PHOE11 NOT-USED
19 PHOE10 NOT-USED
20 PHOE9 NOT-USED
21 VDD1 VDD1
22 PHOE8 NOT-USED
23 PHOE7 NOT-USED
24 PHOE6 NOT-USED
25 PHOE5 NOT-USED
26 PHOE4 NOT-USED
27 PHOE3 NOT-USED
28 PHOE2 NOT-USED
29 PHOE1 NOT-USED
30 GND2 GND2
31 GOP12 GOP12 TX CONTROL
32 DC_CRIA0 CRIA0 CRPHA, CRPAB: PHASE A, B DIRECTION
33 CRPHA/CHX CRPHA CONTROL SIGNAL
34 DC_CRI41 CRIA1 CRIA, CRIB: PHASE A, B CURRENT CONTROL
35 CRIB0 CRIB0 SIGNAL
36 CRPHB/CHY CRPHB L L : HIGH H L : MEDIUM
37 CRIB1 CRIB1 L H : LOW H H : NO
38 GPIO0 GPIO0
39 GPIO1 GPIO1
40 GPIO2 GPIO2
41 GPIO3 GPIO3
42 GPIO4 GPIO4
43 _FAULT NOT-USED
7-6 Samsung Electronics
Pin No. KS32C6500 ATLAS used pin Pin Description
44 PERROR NOT-USED
45 BUSY NOT-USED
46 _ACK NOT-USED
47 SELECT NOT-USED
48 _INT NOT-USED
49 _SLCTIN NOT-USED
50 _AUTOFD NOT-USED
51 _STROBE NOT-USED
52 GND3 GND3
53 PPD7 NOT-USED
54 PPD6 NOT-USED
55 PPD5 NOT-USED
56 PPD4 NOT-USED
57 PPD3 NOT-USED
58 PPD2 NOT-USED
59 PPD1 NOT-USED
60 PPD0 NOT-USED
61 245DIR NOT-USED
62 VDD2 VDD2
63 D0 D0
64 D1 D1
65 D2 D2
66 D3 D3
67 D4 D4
69 D5 D5
69 D6 D6
70 D7 D7
71 GND4 GND4
72 D8 D8
73 D9 D9
74 D10 D10
75 D11 D11
76 D12 D12
77 D13 D13
78 D14 D14
79 D15 D15
80 VDD3 VDD3
81 A0 A0
82 A1 A1
83 A2 A2
84 A3 A3
85 A4 A4
86 A5 A5
87 A6 A6
89 A7 A7
89 A8 A8
Circuit Description
Samsung Electronics 7-7
Circuit Description
Pin No. KS32C6500 ATLAS used pin Pin Description
90 A9 A9
91 A10 A10
92 GND5 GND5
93 A11 A11
94 A12 A12
95 A13 A13
96 A14 A14
97 A15 A15
98 A16 A16
99 A17 A17
100 A18 A18
101 A19 A19
102 A20 A20
103 A21 A21
104 VDD4 VDD4
105 _RCS0 _RCS0 PROGRAM ROM CHIP SELECT
106 _RCS1 NOT-USED FONT ROM CHIP SELECT
107 _RCS2 _RCS2 SRAM CHIP SELECT
108 _RAS0 _RAS0 DRAM ROW ADDRESS STROBE (DEFAULT)
109 _RAS1 NOT-USED DRAM ROW ADDRESS STROBE (OPTION)
110 _CAS0 _CAS0 DRAM LOWER COLUMN ADDRESS STROBE
111 _CAS1 _CAS1 DRAM UPPER COLUMN ADDRESS STROBE
112 _OE _OE MEMORY OUTPUT ENABLE
113 _WE _WE MEMORY WRITE ENABLE
114 GND6 GND6
115 _WBE0 _WBE0 WRITE BYTE ENABLE
116 _WBE1 NOT-USED WRITE BYTE ENABLE
117 _ECS0 _ECS0 MODEM CHIP SELECT
118 _ECS1 _ECS1 DSP CHIP SELECT
119 _ECS2 _ECS2 SDIP4 CHIP SELECT
120 _ECS3 NOT-USED
121 GOP0 GOP0 LIU TXD
122 GIP0 GIP0 LIU RXD
123 GOP1 GOP1 OPE TXD
124 GIP1 GIP1 OPE RXD
125 TEST1 TEST1 NORMAL MODE: GND
126 TEST2 TEST2 DEBUG MODE: VCC
127 CHIP5 CHIP5 HEAD CHECK
128 CLKSEL CLKSEL MASTER CLK SELECT: H
129 _RESET _RESET SYSTEM RESET
130 GND7 GND7
131 MCLK MCLK MASTER CLK (30MHZ)
132 GND8 GND8
133 GOP5 GOP5 RX CONTROL
134 VDD5 VDD5
135 GIP2 GIP2 _MODEM INTERRUPT REQUEST
7-8 Samsung Electronics
Pin No. KS32C6500 ATLAS used pin Pin Description
136 GIP3 GIP3 TX INT
137 GIP4 GIP4 _XDREQ (SDIP4)
138 GOP2 GOP2 _XDACK (SDIP4)
139 LFIA0 LFIA0 LF MOTOR PHASE CONTROL
140 LFPHA LFEN LF MOTOR ENABLE
141 LFIA1 LFIA1 LF MOTOR PHASE CONTROL
142 LFIB0 LFIB0 LF MOTOR PHASE CONTROL
143 LFPHB NOT-USED
144 LFIB1 LFIB1 LF MOTOR PHASE CONTROL
145 EEDATA NOT-USED
146 EECLK NOT-USED
147 GND9 GND9
148 GOP3 GOP3 KEY CLICK
149 GOP4 GOP4 POR CONTROL
150 GOP8 NOT-USED
151 GOP9 GOP9 SDIP4 CLK (30MHZ)
152 GOP10 GOP10 _RESET OUT
153 GOP11 NOT-USED
154 GOP6 NOT-USED
155 GOP7 NOT-USED
156 VDDRTC VDDRTC RTC BACK-UP
157 RXI RXI RTC CLK IN
158 RXO RXO RTC CLK OUT
159 _PHGA13 NOT-USED
160 _PHGA12 NOT-USED
Circuit Description
7-1-3. Memory
System memory consists of 512 kB ROM, 32 kB SRAM and 1024 kB DRAM. All of SRAM is backed up. ROM
and SRAM are selected by chip select lines, and data is accessed by the units position of the byte.
5V power is applied to SRAM through VSB. This facsimile machine uses a Lithium battery for memory backup.
A, 820 ohm resistor in series with the positive battery terminal is for battery protection.
7-1-4. Modem and TX- and RX- Related Circuits
These circuits control transmission between the internal MODEM and the LIU or a remote MODEM.
The KS16117 is a single-chip fax-MODEM having features to detect and generate DTMF tones. TX OUT is the
MODEM output port, and RX IN is the input port. /PORI is the Jupiter-2 signal which enables MODEM
initialization at system power on. D0 - D7 are data buses. RS0 - RS4 are internal register select signals which
determine the mode. /CS is the chip select signal, and /RD /WR are the read and write control signals. RLSD
is used for v.24 interface-related signals and /IRQ is the MODEM interrupt.
Samsung Electronics 7-9
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