The main circuit board consists of a Jupiter-2 Chip (KS32C6500), memory, TX- and RX-related circuitry, and
some portions of the Line interface Unit, and controls the system.
7-1-2. System Control Part
This circuit consists of the EP-ROM and SRAM, External Real Time Clock crystal, RTC and memory back-up,
and the Jupiter-2 Chip (KS32C6500). The Jupiter-2 Chip is an integrated 14400bps modem, image processor, 16bit MPU, peripheral control, and analog front end circuit on a single-chip.
The modem is 14400 bps half duplex. It is a monolithic device incorporating an over sampling Σ∆ AFE, digital
filters, a digital signal processor (SDIP4) and CPU-Interface logic.
Memory Map
The external memory of the CPU is divided into 32kB RAM (0000H through 7FFFH), 512kB ROM (FC0000H
Figure 7-1 KS32C6500 External Memory Map
Samsung Electronics7-1
Page 2
Circuit Description
OPERATING
PANEL
SERIAL
COMMUNICATION
HEAD
DRIVER
RTC
CRYSTAL
(32, 768KHZ)
SDIP4TAD PART
KS32C6500
MOTOR
DRIVER
(CR, LF
MOTOR)
DATA
MEMORY
(SRAM)
PROGRAM
MEMORY
(EPROM)
DRAM.
(USER MEMORY)
GENERAL
PURPOSE I/ 0
TXD
A0~A5
D0~D15 D0~D7
CONTROL
RXD
PHINA~D
CONTROL
+24
XIN
ONLY SF3000T
XOUT
/DMS
/RD/WR
D0~D7
A0~A14
/RD
/LCAS
/RASO~
/UCAS
D0~D15
A0~A17
/A16
/PMS
/RD/WR
D0~D7
A0~A4
/RESET
/RESTO
MODEM
Jupiter-2 Chip
KS32C6500 internal logic generates chip select
signals for both memory chips and peripherals. To
support external access, from one to three wait
cycles can be inserted under program control during
external accesses. A chip select signal line goes
active (low) whenever its corresponding device is
accessed over the external interface. The peripheral
addresses are located in data memory.
/SRAMCS : SRAM chip select active (low)
/ ROMCS : EP-ROM chip select active (low)
D0–D15 : 16 bit data bus
A0–A17 : address bus
System Clock
The 30 MHz internal system clock frequency is
supplied by an external clock generator.
Figure 7-2 Hardware Interface Signals
7`-2Samsung Electronics
Page 3
32.768 KHz
15 BIT
PRESCALER
1HZCO=60CO=60CO=24
6 BIT
SECONDS
6 BIT
MINUTES
5 BIT
HOURS
BUSY
DETECT
5 BIT
DAYS
4 BIT
MONTHS
5 BIT
YEARS
MONTH
DECODER
LEAP YEAR
DECODER
3 STATE
DRIVER
BUSY FLAG CLEARBUSY FLAG
CO=28,29,
30,or 31
CO=12
Circuit Description
CPU Bus
SclkCtrlLo
SclkCtrlHi
Baud Gen (8x)
Tx/Rx Control
IRQ control
SARTCmd
Internal Register
SartlRQ
SCLK
RXD
TXD
RxShift Reg
(SARTData)
RxBuffer
(SARTData)
TxShiftReg
JUPITER - 2
Real Time Clock (RTC)
The circuit receives clock pulses from an external 32.768 kHz crystal, which it divides into hours, minutes,
seconds, year, month, and day. A battery maintains operation when power is off. KS32C6500 can up-track 100
years, begining with 1998.
Figure 7-3 RTC Block Diagram
Operation Panel Control
A Synchronous/Asynchronous Receiver/Transmitter (SART) controls serial data transmission between the
main circuit and the operator panel.
. Serial Communication Signals
The KS32C6500 has two full-duplex serial communication ports. One port is used for I-LIU communication,
Figure 7-4 SART Block Diagram
and the other for OPE communication.
Samsung Electronics7-3
Page 4
Circuit Description
Reset
To initialize the chip’s internal logic, the reset input
(/RESET) must be held to 0 Volt for at least 22 CPU
clocks. During this time, Vdd must be greater than 3
volt. The watchdog timer can also invoke a system
reset.
[+5V Power Monitoring]
If 5 Volt power to KIA7045P drops to between 4.65V
and 4.35V (typically 4.5V), power failure will be
indicated and the output of KIA7045P will go ‘low’
(GND5). This causes the KS16118 to become active
(‘low’=reset).
The KS32C6500 reset causes the /RESET terminal to
be reset. The output terminal of KIA7045P is an
open-drain configuration, and is connected to
KS32C6500 through a 10 kohm pull-up resistor.
Carriage Return Motor Driver
The CR motor drives the head in two directions to
print data on the recording paper.
Motor type : Step Bipolar
Operation Voltage : +24V DC
Resistance : 5 ohm +/-10%
IC : PBL3717 x2EA
STEP MOTOR DRIVER OUTPUT SIGNAL
StandbyFull Step
CRIAO
CRIA 1
PHA
PHB
CRIBO
CRIB 1
500mA
IMA
-500mA
500mA
IMB
-500mA
INPUT
OUTPUT
Line Feed Motor Driver
The LF motor feeds paper in and out.
Motor type : Step Unipolar
Operation Voltage : +24V DC
Holding Voltage : +5V DC
Resistance : 50 ohm ±10%
IC : STA471A
Head Nozzle Driver
The nozzle control circuit is composed as follows:
Number of nozzle : 56 nozzles for mono
Driving Voltage : +24V DC +/-2%
Driving Pulse Width : 3.6 us for mono
Operation Frequency : 5 kHz
Resistance : 30 ohm for mono
IC : SGS Thomson L6451 or Allegro A5817
The IC decodes four input signals (PHINA, PHINB,
PHINC, PHIND) and enables the selected using
OEA and OEB signal input.
9_PHGA3PHINCINK NOZZLE ENABLE CONTROL SIGINAL
10_PHGA2PHINBINK NOZZLE ENABLE CONTROL SIGINAL
11_PHGA1PHINAINK NOZZLE ENABLE CONTROL SIGINAL
12GND1GND1
13PHOE16_HOEDINK NOZZLE DECODING SIGNAL
14PHOE15_HOECINK NOZZLE DECODING SIGNAL
15PHOE14_HOEBINK NOZZLE DECODING SIGNAL
16PHOE13_HOEAINK NOZZLE DECODING SIGNAL
17PHOE12NOT-USED
18PHOE11NOT-USED
19PHOE10NOT-USED
20PHOE9NOT-USED
21VDD1VDD1
22PHOE8NOT-USED
23PHOE7NOT-USED
24PHOE6NOT-USED
25PHOE5NOT-USED
26PHOE4NOT-USED
27PHOE3NOT-USED
28PHOE2NOT-USED
29PHOE1NOT-USED
30GND2GND2
31GOP12GOP12TX CONTROL
32DC_CRIA0CRIA0CRPHA, CRPAB: PHASE A, B DIRECTION
33CRPHA/CHXCRPHACONTROL SIGNAL
34DC_CRI41CRIA1CRIA, CRIB: PHASE A, B CURRENT CONTROL
35CRIB0CRIB0SIGNAL
36CRPHB/CHYCRPHBL L : HIGH H L : MEDIUM
37CRIB1CRIB1L H : LOW H H : NO
38GPIO0GPIO0
39GPIO1GPIO1
40GPIO2GPIO2
41GPIO3GPIO3
42GPIO4GPIO4
43_FAULTNOT-USED
136GIP3GIP3TX INT
137GIP4GIP4_XDREQ (SDIP4)
138GOP2GOP2_XDACK (SDIP4)
139LFIA0LFIA0LF MOTOR PHASE CONTROL
140LFPHALFENLF MOTOR ENABLE
141LFIA1LFIA1LF MOTOR PHASE CONTROL
142LFIB0LFIB0LF MOTOR PHASE CONTROL
143LFPHBNOT-USED
144LFIB1LFIB1LF MOTOR PHASE CONTROL
145EEDATANOT-USED
146EECLKNOT-USED
147GND9GND9
148GOP3GOP3KEY CLICK
149GOP4GOP4POR CONTROL
150GOP8NOT-USED
151GOP9GOP9SDIP4 CLK (30MHZ)
152GOP10GOP10_RESET OUT
153GOP11NOT-USED
154GOP6NOT-USED
155GOP7NOT-USED
156VDDRTCVDDRTCRTC BACK-UP
157RXIRXIRTC CLK IN
158RXORXORTC CLK OUT
159_PHGA13NOT-USED
160_PHGA12NOT-USED
Circuit Description
7-1-3. Memory
System memory consists of 512 kB ROM, 32 kB SRAM and 1024 kB DRAM. All of SRAM is backed up. ROM
and SRAM are selected by chip select lines, and data is accessed by the units position of the byte.
5V power is applied to SRAM through VSB. This facsimile machine uses a Lithium battery for memory backup.
A, 820 ohm resistor in series with the positive battery terminal is for battery protection.
7-1-4. Modem and TX- and RX- Related Circuits
These circuits control transmission between the internal MODEM and the LIU or a remote MODEM.
The KS16117 is a single-chip fax-MODEM having features to detect and generate DTMF tones. TX OUT is the
MODEM output port, and RX IN is the input port. /PORI is the Jupiter-2 signal which enables MODEM
initialization at system power on. D0 - D7 are data buses. RS0 - RS4 are internal register select signals which
determine the mode. /CS is the chip select signal, and /RD /WR are the read and write control signals. RLSD
is used for v.24 interface-related signals and /IRQ is the MODEM interrupt.
Samsung Electronics7-9
Page 10
Circuit Description
DATA MEMORY
CPU
DMA Controller
SCAN/ MOTOR
DRIVER
IMAGE
PROCESSOR
HALF FLASH ADC
SCANNER
DOCUMENT IMAGE
ADDR-BUS
DATA-BUS
ADDR-BUS
DATA-BUS
CLK_NINE
CLK_PIX
LINE_PERIOD
AGC_PERIOD
ADSAMPLE
SI
CLKI
CLKI_
ΦR
Tx_A_Tx_B_Tx_A_Tx_B_
T
R
D
M
A
A
C
K
T
R
D
M
A
R
E
Q
B-BIT
VIDEO SIGNAL
(analog)
[SDIP4]
Transmit Circuit
This circuitry controls transmission of analog signals
from the MODEM. Output voltage from the
MODEM is buffered through the LIU board and OP
Receive Circuit
In receive mode, analog signals from the LIU board
are transferred to RX IN through the BPF and
smoothing filter.
amp after signal smoothing and filtering, and finally
output to the line.
7-1-5. Image Processor / Motor Driver (SDIP4)
• Scan driver generates the control signals to acquire the document data from the scanner and to operate the
Image Processor.
• Motor driver generates the control signals to drive the Tx-Motor according to programmed motor speed.
Figure 7-7 Block Diagram of Scanner Control Function
7-10Samsung Electronics
Page 11
Circuit Description
AGC MODULE
(A/D, D/A I/F)
A/D data[7:0]
Initial Data[7.0]
CPU
I/F
MODULE
(Register Files)
SHADING
CORRECTION
MODULE
GAMMA
CORRECTION
MODULE
DECIMATION/
INTERPOLATION
MODULE
EDGE-
ENHANCEMENT
/EMPHASIS
MODULE
ERROR-
DIFFUSION
MODULE
[IMAGE - PROCESSOR]
Image Data
Memory
I/F
MODULE
BINARY Decision &
Output
MODULE
CPU - Data Bus[15:0]
CPU - Addr Bus[26:0]
CPU - read
CPU - write
IP_CS_
RAM - Data Bus[7:0]
RAM - Addr Bus[14:0]
RAM _read_
RAM _write_
Tr_DMA_request
Tr_DMA_acknowledge
pclk
pdata
ERM-Mode
Edge-Strength
Half-Tone enable
Vpeak_IN[7:0]
Vpeak_OUT[7:0]
Gamma Corrected Value[7:0]
Shading Factor[7:0]
Shade Corrected Value[7:0]
Gamma Corrected Value[7:0]
ERM_Data[7:0]
Edge_Data[7:0]
Error-Diffused Data[7:0]
Figure 7-8 Hardware Block Diagram of Image Processor
HARDWARE BLOCK DIAGRAM
Samsung Electronics7-11
Page 12
Circuit Description
500 KHZ (L:DUTY 75%)
SI
CLOCK
SIG
1 LINE
Image Sensor
This shading wave is formed by scanning the white roller prior to a document. The slice level is determined by
the shading wave, and compensates for shading distortion according to the CIS characteristics. The wave
format from the CIS is converted into a 6 bit digital value in the SDIP4 image processor, and then processed in
B/W or intermediate mode.
CIS Driver
The CIS driver clock (CLK) frequency is 500
kHz. A low duty cycle of 75% is used to
lengthen the charging time. Astart signal (SI) is
provided every 5 ms to match the line scanning
time. Actual image signal (VIN) is provided in
less than 3.4 ms, using the 500 kHz clock,
taking A4 paper size into consideration.
Figure 7-9 CIS Diver Clock Timing
Sensor Detection Circuit
PE SENSOR 1,2
This sensor detects whether paper is loaded in the automatic sheet feeder. If no paper is detected, the output
signal turns high. While paper is feeding to print, the output turns low.
HOME DETECTION CIRCUIT
This circuit detects whether the head is in home position. When power turns on and head is capped, the circuit
is activated. If the head is in the home position, the output turns high.
Scan Motor Controller
The SF3000/SF3000T model facsimile machines perform their send function utilising a single 24 volt motor.
This motor has a winding resistance of 120 ohms. Three drive strobe pulses are used to operate the motor.
SI OCCD/CIS line clear signal pin.
CLK1 OSensor Drive signal output pin.
CLK2 O
DREQODMA data request signal output pin.active : H
DACKIDMA data acknowiedge output pin.active : L
RAM_RDOIP-SRAM read signal pin.
RAM_WROIP-SRAM write signal pin.
RAM_addr[14:0]OIP-SRAM address bus.
RAM_data[7:0]OIP-SRAM data bus.
Tx_AO
Tx_BO
Tx_AOMotor drive signal pins.
Tx_BO
Tx_en1O
Tx_en2O
Tx_intOMotor drive interrupt pin.
GPI[7:0]IGeneral purpose input pins.
GPO[7:0]OGeneral purpose output pins.
GPIO[7:0]BGeneral purpose input/output pins.
7-14Samsung Electronics
Page 15
7-1-6. TAD (SF3000T Only)
TAD circuit consists of a voice coprocessor to record and play voice messages in voice memory.
Circuit Description
Recording path
R62 provides power to the condenser microphone.
Voice signal from the microphone is passed through
active filter U22, R60 and C51, R58, C48 to clear
aliasing noise occuring while sampling and
amplifying the signal. Q5 and Q4 compose ALC
(Automatic Level Control) circuit. CODEC (U29)
converts the voice signal to digital and converts the
digital signal from voice coprocessor into analog for
line output.
Mic input path
Transmit path functions as MIC input path.
Outgoing messages and memo messages from
CODEC are stored in the voice memory (4Mb
DRAM) through the DSPG DRAM controller.
Line input and play path
Incoming signals from line are stored in the voice
memory (4Mb DRAM) through CODEC and DSPG
DRAM controller. When played, DSPG processes
the data stored in voice memory and sends it out to
LIU through CODEC and R93. To playback through
the speaker, DSPG sends the signal to speaker
through R93, MUX (U25, U26), and op amp.
DSPG
This circuit consists of Host Interface, Memory
Interface, CODEC Interface, and DSP core. Host
Interface sends and receives data to and from IFC.
Memory Interface sends and receives the
compressed voice data to and from DRAM to play
back and record voice data. DSP core communicates
with host IFC through Host Interface.
Voice backup
+5V is supplied for voice memory through VBT
when power is on. When power is off, +5V is
supplied from the 9V backup battery.
Samsung Electronics7-15
Page 16
Circuit Description
7-1-7. LIU PBA
The LIU (Line Interface Unit) interfaces the MODEM and telephone to the telephone line. The FAX and
telephone portions of the LIU are active with machine power on. When machine power is off, only the
telephone circuity operates, powered by telephone line voltage. The FAX portion of LIU consists of the interface
between MODEM and telephone line, and the circuits for DC loop feeding, DP signal, loop current and ring
detect. The telephone portion is divided into ringer, dialling and speech circuits. Refer to the schematic and
connection diagram sections of this manual.
FAX section
MODEM/LINE INTERFACE
Following is the path for data and remote control
signals:
• CML1 relay: Switches telephone line between FAX
and telephone circuits.
• U1 pin 3TIT: Single ended input for transformer
(T2)
TIT: Transformer Input from Transformer
• U1 pin 40 ROT: Output for driving transformer
(T3) with an AC impedance greater than 10 Kohm.
ROT: Receive Output Transformer
• C57: DTMF and CNG detect path to T1 20Kohm
winding under idle conditions, and DC blocking
for 20Kohm winding.
• AC impedance: The AC impedance of U1 (I-LIU)
is set to 1000 ohm by external capacitor (C32) at
U1 pin 8 CI (Complex Impedance Input) port.
With the external resistor (R38) at U1 pin 34 ACI
port, it can be programmed to 600ohm. U1 pin 35
CS (Current Shunt control output) port is an
N-channel open drain output to control the
external high power shunt transistor for
synthesizing AC and DC impedance.
• DC conditions: The normal operating mode is
from 15mA to 100mA. An operating mode with
reduced performance is from 5mA to 15mA. In the
line hold range from 0mA to 5mA, the device is in
a power down mode and the voltage at U1 pin 37
LI (Line Input) port is reduced to a maximum of
3.5V. The DC characteristic is determined by the
voltage at U1 pin 37 LI port and R45 resistor
between U1 pin 37 LI and pin 39 LS port. It can be
calculated by the following equation: V
LINE X 45.
I
LS = VLI +
RING DETECT
• U1 pin 28 (MO) is ring melody output port and
this signal drives FET3 which drive Photo coupler
U4 for artificial ring.
MF DIAL
• U1 pin 2 DMS (Dial Mode Selection) port is set to
VDD by R46. It has M/B ratio of 33:66, and in no
power operation mode operates only DP.
• MF signal appears (tone level of low group:
typical - 14 dBm) at U1 pin 4 MFO (DTMF
Generator Output). This signal is leveled by R32,
R28 and C29, then to amplier U1 pin 9 MFI
(DTMF Amplier Input).
• Line dial signals appear at U1 pin 39 LS (Line
Current Sense Input).
(Same as telephone section)
DP DIAL (Same as telephone section)
• U1 pin 2 (DMS) is set to Vdd (33/66) or VSS
(40/60) by R46 or R52 resistor.
• Dial pulses originate at U1 pin 27 (DPN), which
toggles Q5, which drives Q2. The resulting
intermittent voltage interrupts the telephone line.
• Pulse M/B ratio is set by U1 pin 2 DMS port.
Vdd = 33/66, and Vss = 40/60.
• U1 pin 35 CS port: Modulation of line voltage and
shorting the line during make period of pulse
dialling.
7-16Samsung Electronics
Page 17
LLC (Line Loss Compensation) LOOP
CURRENT DETECT
Circuit Description
• The LLC is a pin option. When it is activated, the
transmit and receive gains for both I/O are
decreased by 6dB at line currents from 20mA
when the U1 pin 31 LLC is connected to AGND,
from 75mA when this pin is connected to VDD.
The LLC is deactivated when LLC pin is
connected VSS.
• When the CML1 relay or Hook Switch switches to
telephone line, the U1 in the LIU board and CPU
(U1) in the Main board srart communication. The
U1 send <Ack> message contains the line current
information. Using this line current information
Main CPU can recognize a parallel phone.
Baud Rate 9600
Start Bit 1
Stop Bit 1
Data Bits 8
Parity Bit None
LSB is transferred prior to MSB.
Telephone Section
• Line ring voltage passes through bridge diode
BD1, CML relay and Hook Switch to FET3 (BS170)
pin 3, C21, R19.
• The ring frequency discriminator of U1 assures
that only signals with a frequency between 13Hz
and 70Hz are regarded as valid ring signals.
• When a valid ring signal is present for 73ms
continuously, the ring melody generator (pin 28,
MO) is activated and remains active as long as a
valid ring signal is present.
• U1 filters the ring signals and output is pin 28
(MO).
• The 3 basic melody frequencies are : F1 = 880 Hz,
F2 = 1067 Hz and F3 = 1333 Hz. The repetition
rate is set to 4 which means that the sequence of
F1, F2, F3, F1, F2, F3 is repeated 4 times within a
second.
SPEECH CIRCUIT
• U1 (STI9510) and associated components.
• Handset transmitting circuit. Condensor MIC of
handset is filtered by R25, C28, C27, C20, C19,
C24, C22 and C30, and then amplified by U1 pin
32 and 33 (M1, M2)
• Handset receiving circuit. Receiving (Dynamic
unit) of handset is filtered by R49, C45, C40, C44
and C23, and then applied by U1 pin 1 (ROH) and
VSS.
• U1 pin 39 (LS) is audio output to telephone line.
RINGER CIRCUIT
SIDETONE CIRCUIT
• When a ringing signal is applied to the line, Vdd
of U1 (I-LIU) is charged up via an external path.
After Vdd has reached the operating voltage the
oscillator starts and U1 discriminates the ring
frequency.
After a valid ring frequency is applied to the U1
pin 25 RFD (Ring Frequency Discrimination) port,
the ring melody generator of U1 sends out a 3tone melody via the U1 pin 28 MO (Ring Melody
Output)port.
• U1: I-LIU and associated components.
• Ring frequency passes through DC blocking
capacitor C3 or C4 (for Switzerland or Austria)
and Zener-diode ZD2 or ZD3 (for Switzerland or
Austria) to U1 pin 25 RED port.
Samsung Electronics7-17
• Sidetone audio characteristics are controlled by
R37, R51, R5, R26, and C41 connected to U1 pin 7
STB.
Page 18
Circuit Description
Document
Detect
Sensor
Connector
MICOM
Z-8601
LCD
16 x 1 lines
Key Matrix
LEDs
1 (SF3000T
Only)
8
Y
X
7
11
2
UART
Reset
7-1-8. OPE PBA
OPE PBA consists of U300 (MICOM Z8601), LCD, key matrix, LED indicators, and the document detect and
scan position sensors. Refer to OPE Schematic Diagram and Wiring Diagram sections of this manual.
• Signals from the key matrix and delivered to U300 X/Y input pin group (P1-X).
• U300 pin 4 (RX DATA) is UART code to MAIN PBA.
• Display from controller is received at U300 pin 5 (TX DATA).