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Samsung Electronics Digital Printing
CS Group
Copyright (c) 2001. 11
This manual is made and
described centering around
circuit diagram
and circuit description needed
in the repair center
in the form of appendix.
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1
1-1
Samsung Electronics
BLOCK DIAGRAM
Repair Manual
1. Block Diagram
Only SCX-5312F
Only SCX-5312F
Only SCX-5312F
LCD
OPE
MICOM
- LCD Drive
- Key Scan
FLAT
D-SUB
CONN.
FLAT MOTOR
ADF
MOTOR
DRIVER
ADF MOTOR
PAPER SENSOR
POS, DET
3P X 2EA
ADF OPTION
CCD MODULE
22P
ARM7TDMI
UART * 2
MEMORY I/F
CACHE (8K)
DMA CNTR
PVC
GEU
I/O I/F
USB
IEEE1284
MOTOR
DRIVER
SW2918 / TEA3718
EXTERNAL
GPIO
74HC245
74HC273
11P
8P
2P
3P3P3P
4P4P2P
2P X 3EA
3P X 2EA
6P X 1EA
4P X 1EA
LSU
THE RMISTOR
FAN
DEV_ID
TONER_TX
TONER_RX
PTL
SOLENOID
PICK_UP, DUPLEX, MP
PAPER SENSOR
FEED+P.EMP, EXIT, MP,BIN-FULL
COVER OPEN S/W
+24V / +5V
LIU
LINE1
EXTERNAL
PHONE
TRANSFORMER
600 / / 600
TX : RX
MODEM &
EXT_PHONE
PAPER A TING
PART
EXTER NAL
PHONE
INTE RFACE
PART
LINE
INTERFACE
MODEM
33.6Kbps
14P
UNICON
USB CABLE
CENTRONICS
CABLE
Image Processor
12bit ADC
I/O PORT
Motor CNTR
DMA I/F
CIP3
FAST SRAM
(1Mbit)
MOTOR
DRIVER
CCD
I/F PART
15P D-SUB
24P
5P
RTC
Back-up Part
SRAM
(32KB)
FLASH ROM
(1MB) X 2EA
F/W
FLASH ROM
(1MB) X 2EA
PCL
DRAM
(8MB)
DRAM
(8MB)
FONT ROM
KM23C8105 H/L
PCL
SPGPe+
MAIN
24P
MOTOR 1
MOTOR 2
SMPS / HVPS
+5V/+24V/+12V/+24Vs/Fuser
T
H
V
M
H
V
DEV
SUPPLY
BLADE
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2
2-1
Samsung Electronics
CONNECTION DIAGRAM
Repair Manual
2. Connection Diagram
MAI N
FLAT
LS
U
CCD MO DUL E
THERMISTOR
D
UPLEX SOL.
DEV_I D
MP S OL.
LI U
SMPS / HVPS
1.GND_5 2. +5 V 3.
GND_5
4.+5V 5.GND_5
6. + 5V 7 .
GND_12
8.+12V 9.
GND_ 24
10.+24V 11.
GND_24
12. +24V 13.
GND_24
14. +24V 15.
THV_PWM
16 . +2 4V S 1 1 7 .
THV_EN
18. +24VS1
19.
THVREAD
20.
FUSER_ON
21.
MHV_PWM
22.SPK+ 23.
DEV_P W M
24. SPK-
1.nHSYNC
2.+5VS
3.GND_5
4.nLD_ON
5.nVDO
6.NC
7.LSU_CLK
8.nLREADY
9.PMOTOR
10. GND_24
11. +24VS1
123 45678 91011
123 456
7
8
9
1
0
1
1
1.
GND_24
2.+24V 3. +5V 4.GND_24 5.
ADF_PH A6.GND_57.ADF_I A( 1)
8.
ADF_I A( 0)9.ADF_I B(0 )
10 . A D F_ P HB11.
MODULE_DETECT
12. ADF _I B(1)
13.
ADF_P_POS14.ADF_P_DET
15.NC 16.
ADF_P_REGI
17.OPE_RXD
18.OPE_RST 19. OPE_TXD 20
.FLAT_COVER
21 . T M_A 2 2.
TM_NA
23. TM_B
24. TM_NB
123 45678 9101112131415161718192021222324
1 2 3 45 6 7 8 910 11121314 151617181920212223 24
2 1 4 36 5 8 7 109 12111413 161518172019222124 23
1,2. INV_POWER
3,4.GND_12
5.CCD_HOME
6,7. +12V
8.CCD_TG
9.GND_5
10.CCD_CLK1
11.GND_5
12.CCD_CLK2
13.GND_5
14.CCD_RS
15.GND_5
16.CCD_CP
17.GND_5
18.GND_12
19.
VOUT _
VOUT _
VOUT _
R
20. G
21. B
22. GND_12
PC
Parallel Port
36pin
USB Port
4pin
214 36587 1091211141316151817201922212423
FLAT
MOTOR
1.FLAT_A
2.FLAT_NA
3.FLAT_B
4.FLAT_NB
OPE
1.GND_5
2.+5V
3.OPE_TXD
4.OPE_RST
5.OPE_RXD
D-SUB
CONN.
15P D-SUB
ADF
1.+24V
2,3. GND_2 4
4.+5V
5.GND_5
6.ADF_PHA
7.ADF_IA( 0)
8.ADF_IA( 1)
9.ADF_PHB
10.ADF_IB(0)
11.ADF_IB(1)
12.
MODULE_DETECT
13. ADF_P
ADF_P
ADF_P
_DET
14. _POS
15. _REGI
16. NC
ADF
MOTO R
1.ADF_A
2.ADF_NA
3.ADF_B
4.ADF_NB
1.+5V
2.
SI GN AL
SI GN AL
3.GND_5
GND_5
1.+5V
2
3.
4,5. NC
SCANNER PART
DET EC T
SENSOR
SENSOR
POSI ON
EXIT
SENSOR
1.+5V
2.S IGNAL
3.GND_5
1
.
T
H
E
R
M
1
2
.
T
H
E
R
M
2
JOI N T T YP E
1
.
T
H
E
R
M
1
2
.
T
H
E
R
M
2
DC FAN
1.+24V
2.NC
3.Control
1.
MTR1
MTR1
MTR1
MTR1
MTR2
MTR2
MTR2
MTR2
_I B ( 0 )
2.
_I B ( 1 )
3.
_I A ( 0 )
4.
_I A ( 1 )
5.
_I A ( 0 )
6.
_I A ( 1 )
7.
_I B ( 0 )
8.
_I B ( 1 )
MOTOR_1
1
2
3
4
MOTOR_2
5
6
7
8
1.+24V
2.Control
1.DEV_I D1
2.NC
3.DEV_I D
RX
1.NC
2.S IGNAL
SIGNAL
SIGNAL
SIGNAL
3.GND_5
4.NC
TONER_
TONER_
TX
1.+5V
2.Control
3.NC
1.+5V
2.
3.GND_5
4.+5V
5.
6.GND_5
FEED
SENSOR
1
2
3
P. E M PT Y
SENSOR
4
5
6
PTL
1.+5V
2.Control
MP SOL .
1.+24V
2.Control
MP
SENSOR
1.+5V
2.
3.GND_5
1.+5V
2.+5VS
3.+24V
4.+24VS
MI CRO
SWITCH
1.+24V
2.Control
FOR LSU + 5VS CUT
REMARK
: Normal Connector
:BoardontyoeConnector
1.BLADE
2.NC
3. SU PPLY
4.NC
5.DEV
MHV
THV
1.SPK+
2.SPK
-
1
.
H
O
T
2
.
N
e
u
t
r
a
l
HEAT
LAM P( Fuser )
1
.
H
O
T
2
.
N
e
u
t
r
a
l
POWE R
SW I T CH
AC
IN-LET
110V for U SA
220V for EU
1.MODEM_RX 2. GND_12
3.MODEM_TXA1 4. MODEM_T X A2
5.+12V 6.REMOTE 7 . CML1
8.nHOOK29.nRING_DET
10.+5V 11.DP12.GND_5
13. RECALL 14. nE_DP
1. + 5V
2. HYPER_ TXD
3. HYPER_ RXD
4. GND_5
for System States viewer
Mod ul ar J A CK
Ext r na l L IN E
TEL LINE
CN14
CN11
CN2CN3CN8CN7CN5 CN29CN4
CN9
CN28
CN15
CN16
CN17
CN18
CN19
CN21
CN23
CN25 CN26 CN27
CN20
CN22
P1
CN14
CN2
CN4CN3 CN1
CN3
CN2
CN4
CN3
CN1
C0N3
C0N4 C0N2 C0N1
36pin
IEEE1284 Conn.
4pin
USB Con n.
(ONLY SCX-5312F)
(ONLY SCX-5312F)
1.+5V
2.S IGNAL
3
4. NC
.GND_5
BIN-FULL
SENSOR
1
2
3
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3
3-1
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
3. Circuit Description
3-1 Main PBA
3-1-1 SUMMARY
The main circuit that consists of CPU, MFP controller (built-in 32bit RISC processor core: ARM7TDMI) including various I/O
device drivers, system memory, scanner, printer, motor driver, PC I/F, and FAX transceiver controls the whole system. The
entire structure of the main circuit is as follows :
OSC
20 MHz
POWER
ON RESET
MODEM
CIP3
OSC.(Video)
45.3928 MHz
LIU
OSC.
48 MHz
USB
INTERFACE IC
(UNICON)
USB
RTC
PARALLEL
INTERFACE
OPE PANEL
INTERFACE
PROGRAM
ROM
1MB x 4EA
SRAM
256K
DATA RAM
(DRAM)
8MB x 2EA
PLL
Reset & WDT
Generation
ARM7TDMI
Cache 8KB
ROM/SRAM/
FLASH ROM
Control
(4 Bank)
I/O
Control
(5 Bank)
CPU BUS
Interface Block
GPIO
SYSTEM BUS
Interface Block
[Arbiter]
VIS
ADC
RAM : 512B
UART
(3 CH)
Interrupt
Control
(4 External)
Timer
(3 CH)
Tone
Generator
Engine
Comm. I/F
JBIG
LRAM:1296B
CXRAM:256B
RAM
512B+512B
HPVC
HCT
DMAC
(2 CH)
PPI
PVC
GEU
EDO/FPM
DRAM
Control
(4 Bank)
MA
MD
RAS
CAS
/CS,/RD,/WR
A/D BUS
IMCS
/MIR0,
/RD,/WR
D0~D7
A0~A4
RST_OUT
IOCS
/RST_OUT
/XDACK
/XDREQ
/SDIP CS
/RD,/WR
D0~D15
A0~A5
• Main B’D
<Block Diagram>
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3-2
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
3-2 Circuit Operation
3-2-1 CLOCK
1) System Clock
• KS32C61200 RISC PROCESSOR: drives PLL internally and uses 60MHz.
2) Video Clock
• Fvd =((PAPER 1SCAN LINE sending time * SCAN effective late /1SCAN LINE DOT #)*4
=(600dpi*600dpi*58.208mm/s*216mm*4)/(25.4mm*25.4mm*76.1%)=28.697MHz
•PAPER 1SCAN LINE sending time=SCAN LINE interval/DOCUMENT SPEED (58.208mm/S)
•1SCAN LINE DOT #=MAZ SCAN distance(216mm)*DOT# per 1mm
3)USB Clock
3-2-2 POWER ON/OFF RESET
1) Signal Operation
• POWER ON/OFF DETECT VCC RISING/FALLING 4.5°≠4.6V
• Td=(Ct*V sensing)/I charge (...Ct=33µF, Is=100µA)
2) TIMING CHART
Device Oscillator
Frequency 20MHz±%
Device Oscillator
Frequency 45.3928 MHz±%
Device Oscillator
Frequency 48MHz±%
Input Signal +5V Power Line (VCC)
Output Signal KS32C61200 nRESET 29F800B nRESET
RESET TIME (Td) 1.48~1.52ms
and SENSEV
CC
Threahold Voltage
V
V
CC
CC
3.6V
V
CC
2V
Output
Undefined
RESET
d
t
d
t
Output
Undefined
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3-3
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
3-2-3 RISC MICROPROCESSOR
1) RISC MICROPROCESSOR PIN & INTERFACE
No Pin Name I/O Reset Value Description PAD
1 DATA0 I/O Input CPU Data Bus 0 PHBTT8, 8 mA
2 DATA1 I/O " CPU Data Bus 1 "
3 DATA2 I/O " CPU Data Bus 2 "
4 DATA3 I/O " CPU Data Bus 3 "
5 Vsso Vss - 5VGnd
6 DATA4 I/O Input CPU Data Bus 4 PHBTT8, 8 mA
7 Vddo Vdd - 5V
8 DATA5 I/O Input CPU Data Bus 5 PHBTT8, 8 mA
9 DATA6 I/O " CPU Data Bus 6 "
10 DATA7 I/O " CPU Data Bus 7 "
11 DATA8 I/O " CPU Data Bus 8 "
12 Vssi Vss - 3.3 V Gnd
13 DATA9 I/O Input CPU Data Bus 9 PHBTT8, 8 mA
14 Vddi Vdd 3.3 V
15 DATA10 I/O Input CPU Data Bus 10 PHBTT8, 8 mA
16 DATA11 I/O " CPU Data Bus 11 "
17 DATA12 I/O " CPU Data Bus 12 "
18 DATA13 I/O " CPU Data Bus 13 "
19 Vsso Vss - 5VGnd
20 DATA14 I/O Input CPU Data Bus 14 PHBTT8, 8 mA
21 DATA15 I/O " CPU Data Bus 15 "
22 DATA16 I/O " CPU Data Bus 16 "
23 DATA17 I/O " CPU Data Bus 17 "
24 Vsso Vss - 5VGnd
25 DATA18 I/O Input CPU Data Bus 18 PHBTT8, 8 mA
26 DATA19 I/O " CPU Data Bus 19 "
27 DATA20 I/O " CPU Data Bus 20 "
28 DATA21 I/O " CPU Data Bus 21 "
29 Vddi Vdd - 3.3 V
30 DATA22 I/O Input CPU Data Bus 22 PHBTT8, 8 mA
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3-4
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
No Pin Name I/O Reset Value Description PAD
31 Vssi Vss - 3.3 V Gnd
32 DATA23 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
33 DATA24 I/O " CPU Data Bus 23 "
34 Vddp Vdd - 5V
35 DATA25 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
36 Vssp Vss - 5VGnd
37 DATA26 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
38 DATA27 I/O " CPU Data Bus 23 "
39 Vddo Vdd - 5V
40 DATA28 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
41 Vsso Vss - 5VGnd
42 DATA29 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
43 DATA30 I/O " CPU Data Bus 23 "
44 DATA31 I/O " CPU Data Bus 23 "
45 Vssi Vss - 3.3 V Gnd
46 LFIA0 / OP4 O H Line Feed Motor Phase A PHOB4, 4mA
47 Vddi Vdd - 3.3 V
48 LFIA1 / OP5 O H Line Feed Motor Phase /A PHOB4, 4mA
49 LFIB0 / OP6 O " Line Feed Motor Phase B "
50 LFIB1 / OP7 O " Line Feed Motor Phase /B "
51 TnRST I TAP Controller Reset PHIT
52 TMS I TAP Controller Mode Sel PHIT
53 TDI I TAP Controller Data In "
54 TCK I TAP Controller Clock "
55 TDO O TAP Controller Data Out PHOB4
56 AVdd Vcca - Analog 3.3 V
57 AVin[0] I - Analog Input 0 PICA
58 AVin[1] I - Analog Input 1 "
59 AVss Vssa - Analog Gnd
60 AVssAVin[2] I - Analog Input 2 PICA
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3-5
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
No Pin Name I/O Reset Value Description PAD
61 AVref I - Analog Positve Reference PICA
62 nIOCS0 O H IO Chipselect 0 PHOB4, 4 mA
63 nIO CS2/ToneOut O " IO Chipselect 2 / ToneOut "
64 nIOCS3/BufferSel O " IO Chipselect 2 / BufferSel "
65 Vssi Vss - 3.3 V Gnd
66 nSELECTIN I - Select Input PHIL, ST
67 nFAULT O H Fault for Error Condition PHOB8, 8 mA
68 nAUTOFD I - Auto Feed PHIL, ST
69 nINIT I - Initialization "
70 SELECT O L Parallel Port Select PHOB8, 8 mA
71 Vddp Vdd - 5V
72 PERROR O L Paper Error PHOB8, 8 mA
73 BUSY O " Parallel Port Busy PHOB8, 8 mA
74 nACK O H Parallel Port Acknowledge PHOB8, 8 mA
75 Vssp Vss - 5VGnd
76 PD0 I/O Input Parallel Port Data 0 PHBTT8, 8 mA
77 PD1 I/O " Parallel Port Dat a "
78 Vddi Vcca - 3.3 V f or Ring OSC
79 PD2 I/O Input Parallel Port Dat a PHBTT8, 8 mA
80 PD3 I/O " Parallel Port Dat a "
81 Vssi Vssa - 3.3 V Gnd for Ring OSC
82 PD4 I/O Input Parallel Port Dat a PHBTT8, 8 mA
83 PD5 I/O " Parallel Port Dat a "
84 Vddo Vdd - 5V
85 PD6 I/O Input Parallel Port Dat a PHBTT8, 8 mA
86 PD7 I/O " Parallel Port Dat a "
87 nSTROBE I - Data Strobe PHIL, ST
88 Vsso Vss - 5VGnd
89 RxD1 / CTin[2] I - Uart 1 Rx Data PHIL, ST
90 TxD1 O H Uart 1 Tx Data PHOB4, 4 mA
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3-6
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
No Pin Name I/O Reset Value Description PAD
91 nDREQ1/RxD2/CTin[1] I - DMA Request1/Uart 2 RxD PHIL, ST
92 nDMACK1 / TxD2 O H DMA Ack1/Uart 2 TxD PHOB4, 4 mA
93 nIOCS1 / nIOCS5 O " IO CS1 / DMA IO1 CS "
94 Vddi Vdd - 3.3 V
95 nDREQ0 /IP1/CTin[0] I - DMA Request0 / Input Port PHIL, ST
96 nDMACK0 / OP1 O H DMA Ack1 / Out Port PHOB4, 4 mA
97 nIO CS4 / O P2 O " DMA IO0 CS / Out Port "
98 EIRQ0 I - External Interrupt 0 PHILU50, ST
99 EIRQ1 I - External Interrupt 1 "
100 EIRQ2 I - External Interrupt 2 "
101 nWait/EIRQ3 I - Wait Request / Ex. IRQ 3 "
102 Vssi Vss - 3.3 V Gnd
103 VCLK I - Video Clock Input PHIC
104 Vddi Vdd - 3.3 V
105 IP[7] / nFSYNC I - Input Port / Frame Sync PHIL, ST
106 nLSYNC I - Line Sync "
107 OP[8] / nPRINT O H OutPort/PrintStart PHOB4, 4 mA
108 Vssi Vss - 3.3 V Gnd
109 VDO O H Video Data Output PHO B16, 16mA
110 Vsso Vss - 5VGnd
111 CCLK / PWM[0] O H Com. Clock / PWM [0] PHOB4, 4 mA
112 nEPRDY / RxD0 I -
Engine Power Ready
/Uart0RxData
PHIL, ST
113 nCBSY / TxD0 O H
Command Busy
/Uart0TxData
PHOB4, 4 mA
114 nEMSG / PWM[1] I/O Input Eng. Message / PWM [1] PHBLT4,ST,4mA
115 nEBSY / nLsuReady I - Eng. Busy / LSU Ready PHIL, ST
116 nCMSG / PWM[ 2] O H Com. Busy / PWM [2] PHOB4, 4 mA
117 Vddo Vdd - 5V
118 nDRAMCAS0 O L DRAM Cas Strobe 0 PHOB8, 8 mA
119 nDRAMCAS1 O " DRAM Cas Strobe 1 "
120 nDRAMCAS2 O " DRAM Cas Strobe 2 "
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3-7
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
No Pin Name I/O Reset Value Description PAD
121 nDRAMCAS3 O L DRAM Cas Strobe 3 PHOB8, 8 mA
122 Vsso Vss - 5VGnd
123 nDRAMOE O H DRAM Data Out Enable "
124 nDRAMWE O H DRAM Data Write Enable "
125 Vssi Vss - 3.3 V Gnd
126 nDRAMRAS0 O L DRAM Ras Strobe 0 PHOB8, 8 mA
127 Vddi Vdd - 3.3 V
128 nDRAMRAS1 O L DRAM Ras Strobe 1 PHOB8, 8 mA
129 nDRAMRAS2 O " DRAM Ras Strobe 2 "
130 nDRAMRAS3 O " DRAM Ras Strobe 3 "
131 Vsso Vss - 5VGnd
132 DRAMD0 I/O Input DRAM Data Bus 0 PHBTT12, 12mA
133 Vddo Vdd - 5V
134 DRAMD1 I/O Input DRAM Data Bus 1 PHBTT12, 12mA
135 DRAMD2 I/O " DRAM Data Bus 2 "
136 DRAMD3 I/O " DRAM Data Bus 3 "
137 DRAMD4 I/O " DRAM Data Bus 4 "
138 Vsso Vss - 5VGnd
139 DRAMD5 I/O Input DRAM Data Bus 5 PHBTT12, 12mA
140 DRAMD6 I/O " DRAM Data Bus 6 "
141 DRAMD7 I/O " DRAM Data Bus 7 "
142 Vssi Vss - 3.3 V Gnd
143 DRAMD8 I/O Input DRAM Data Bus 8 PHBTT12, 12mA
144 Vddi Vdd - 3.3 V
145 DRAMD9 I/O Input DRAM Data Bus 9 PHBTT12, 12mA
146 DRAMD10 I/O " DRAM Data Bus 10 "
147 DRAMD11 I/O " DRAM Data Bus 11 "
148 Vssp Vss - 5VGnd
149 DRAMD12 I/O Input DRAM Data Bus 12 PHBTT12, 12mA
150 Vddp Vdd - 5V
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3-8
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
No Pin Name I/O Reset Value Description PAD
151 DRAMD13 I/O Input DRAM Data Bus 13 PHBTT12, 12mA
152 DRAMD14 I/O " DRAM Data Bus 14 "
153 DRAMD15 I/O " DRAM Data Bus 15 "
154 DRAMD16 I/O " DRAM Data Bus 16 "
155 Vsso Vss - 5VGnd
156 DRAMD17 I/O Input DRAM Data Bus 17 PHBTT12, 12mA
157 Vddo Vdd - 5V
158 DRAMD18 I/O Input DRAM Data Bus 18 PHBTT12, 12mA
159 DRAMD19 I/O " DRAM Data Bus 19 "
160 DRAMD20 I/O " DRAM Data Bus 20 "
161 DRAMD21 I/O " DRAM Data Bus 21 "
162 Vssi Vss - 3.3 V Gnd
163 DRAMD22 I/O Input DRAM Data Bus 22 PHBTT12, 12mA
164 Vddi Vdd - 3.3 V
165 DRAMD23 I/O Input DRAM Data Bus 23 PHBTT12, 12mA
166 DRAMD24 I/O " DRAM Data Bus 24 "
167 DRAMD25 I/O " DRAM Data Bus 25 "
168 DRAMD26 I/O " DRAM Data Bus 26 "
169 Vsso Vss - 5VGnd
170 DRAMD27 I/O Input DRAM Data Bus 27 PHBTT12, 12mA
171 Vddo Vdd - 5V
172 DRAMD28 I/O Input DRAM Data Bus 28 PHBTT12, 12mA
173 DRAMD29 I/O " DRAM Data Bus 29 "
174 DRAMD30 I/O " DRAM Data Bus 30 "
175 DRAMD31 I/O " DRAM Data Bus 31 "
176 Vsso Vss - 5VGnd
177 DRAMA0 O L DRAM Address Bus 0 PHOB8, 8 mA
178 DRAMA1 O " DRAM Address Bus 1 "
179 DRAMA2 O " DRAM Address Bus 2 "
180 DRAMA3 O " DRAM Address Bus 3 "
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3-9
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
No Pin Name I/O Reset Value Description PAD
181 DRAMA4 O L DRAM Address Bus 4 PHOB8, 8 mA
182 Vsso Vss - 5VGnd
183 DRAMA5 O " DRAM Address Bus 5 "
184 DRAMA6 O " DRAM Address Bus 6 "
185 DRAMA7 O " DRAM Address Bus 7 "
186 Vddo Vdd - 5V
187 DRAMA8 O L DRAM Address Bus 8 PHOB8, 8 mA
188 Vsso Vss - 5VGnd
189 DRAMA9 O L DRAM Address Bus 9 PHOB8, 8 mA
190 DRAMA10 O " DRAM Address Bus 10 "
191 DRAMA11 O " DRAM Address Bus 11 "
192 Vssi Vss - 3.3 V Gnd
193 nROMCS0 O H ROM Chip Select 0 PHOB4, 4 mA
194 Vddi Vdd - 3.3 V
195 nROMCS1 O H ROM Chip Select 1 PHOB4, 4 mA
196 nROMCS2 O " ROM Chip Select 2 "
197 nROMCS3 O " ROM Chip Select 3 "
198 nROMRD O " ROMorIORead PHOB8, 8 mA
199 Vssp Vss - 5VGnd
200 nROMWR O H ROMorIOWrite PHOB8, 8 mA
201 Vddp Vdd - 5V
202 ADDR2 O L Address Bus 2 for ROM PHOB8, 8 mA
203 ADDR3 O " Address Bus 3 f or ROM "
204 ADDR4 O " Address Bus 4 f or ROM "
205 Vsso Vss - 5VGnd
206 ADDR5 O L Address Bus 5 for ROM PHOB8, 8 mA
207 ADDR6 O " Address Bus 6 f or ROM "
208 ADDR7 O " Address Bus 7 f or ROM "
209 Vssi Vss - 3.3 V Gnd
210 ADDR8 O L Address Bus 8 for ROM PHOB8, 8 mA
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3-10
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
No Pin Name I/O Reset Value Description PAD
211 ADDR9 O L Address Bus 9 for ROM PHOB8, 8 mA
212 Vddo Vdd - 5V
213 ADDR10 O L Address Bus 10 for RO M PHOB8, 8 mA
214 Vsso Vss - 5VGnd
215 ADDR11 O L Address Bus 11 for RO M PHOB8, 8 mA
216 ADDR12 O " Address Bus 12 for RO M "
217 ADDR13 O " Address Bus 13 for RO M "
218 ADDR14 O " Address Bus 14 for RO M "
219 Vsso Vss - 5VGnd
220 ADDR15/CTO ut[0] O L Address Bus 15 for RO M PHOB8, 8 mA
221 ADDR16/CTO ut[1] O " Address Bus 16 for ROM "
222 ADDR17/CTO ut[2] O " Address Bus 17 for ROM "
223 ADDR18/CTO ut[3] O " Address Bus 18 for ROM "
224 Vsso Vss - 5VGnd
225 ADDR19/CTO ut[4] O L Address Bus 19 for RO M PHOB8, 8 mA
226 ADDR20/CTO ut[5] O " Address Bus 20 for ROM "
227 ADDR21/CTO ut[6] O " Address Bus 21 for ROM "
228 ADDR22/CTO ut[7] O " Address Bus 22 for ROM "
229 Vddo Vdd - 5V
230 ADDR23/PTOut O L Address Bus 23 for RO M PHOB8, 8 mA
231 Vsso Vss - 5VGnd
232 TESTSE I - Scan Enable :Tied to Gnd PHILD50, ST
233 TM I - TestMode:TiedtoGnd "
234 Vddi Vcca - 3.3 V for PLL
235 MCLK I - Master Clock PHIC
236 Vssi Vssa - 3.3 V Gnd for PLL
237 FILTER O -
Charge Pump Out :
Capacitor is connected
POBA
238 CPUTEST I -
CPU Test Mode :
Tied to Gnd
PHILD50, ST
239 nRESET I - Reset Input PHIL, ST
240 nRSTOUT O L Reset Output PHOB8, 8 mA
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3-11
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
3-2-4 PROGRAM ROM (FLASH MEMORY) CONTROL
1) DEVICE
TYPE No...................................AM29F800B
CAPACITY................................4 MBYTE (512K * 16BITS * 4)
2) PROGRAMMING
BEFORE ASS’Y.......................EPROM PROGRAMMER or PROGRAMMING at the factory
AFTER ASS’Y..........................DOWNLOAD from PC
3) OPERA
TING PRINCIPLE
When the RCSO(ROM CHIP SELECT)signal is activated from the CPU after the POWER is ON, it activates RD SIGNAL
and reads the DATA(HIGH/LOW) stored in the FLASH MEMORY to control the overall system.
The FLASH MEMORY may also write. When turning the power on, press and hold the key(power switch) for 2 - 3 seconds,
then the LED will scroll and the PROGRAM DOWNLOAD MODE will be activated. In this mode, you can download the program through the parallel port.
Tr TwTwTwTwTwTwTw TrTrTrTrTdTa
MCLK
nROMCS
A23-2
nTA
ACC+1
HOLD
SETUP
nWR
<Write Timing Diagram for Two Beat Burst Cycle>
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3-12
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
3-2-5 DRAM CONTROL
1) DEVICE
TYPE NO..................................K4E6411D EDO TYPE
CAPACITY................................4MBYTES (1M*16BITS*2)
2) OPERATING PRINCIPLE
DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores data white the CPU
processes data. The address to read and write the data is specified by RAS SIGNALand CAS SIGNAL. DRAMWE*SIGNAL
is activated when writing data and DRAMOE*SIGNAL, when reading. You can expand up to 64MBYTE of DRAM in this system.
0x00
000
00
0xf f f ff f f
bank3 Next
bank3 Base
bank2 Next
bank2 Base
bank1 Next
bank1 Base
bank0 Next
bank0 Base
<DRAM Bank Configuration>
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3-13
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
3-2-5-1 Fpm DRAM reading Timing
Fast Page Mode DRAM can access the page mode. It can read consecutive cells by accessing the page mode while accessing the burst. For FPM DRAM, the data are valid only when the nCAS is active.
While configuring the software, you must set the timing register of SFR considering the clock speed and the DRAM spec.
5Mhz
MCLK
DRAMD
nWE
nOE
DRAMA
nCAS
nRAS
Tr p Trc
Tcas
Tcas
data 1data 0
row address
column address
column address
addr
wait waitdata
data
<FPM Read Timing Diagram>
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3-14
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
3-2-5-2 fpm DRAM write timing
5Mhz
MCLK
DRAMD
nWE
nOE
DRAMA
nCAS
nRAS
Trp Trc Tc as Tcas
data 1
data 0
row address
column address
column address
addr
wait waitdata
data
clock
type
Trp Trc Tcas
cycle
#
register cycle
#
register cycle
#
register
58Mhz
40 ns FPM 2 0x1 2 0x1 1 0x0
50 ns FPM 2 0x1 2 0x1 1 0x0
60 ns FPM 3 0x2 2 0x1 2 0x1
70 ns FPM 3 0x2 2 0x1 2 0x1
<FPM Write Timing Diagram>
<SFR Values Example for FPM>
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3-15
Samsung Electronics
CIRCUIT DESCRIPTION
Repair Manual
3-2-5-3 EDO DRAM read timing
Basically the Extended Data Out DRAM is similar to Fast Page Mode DRAM. For FPM, the data are valid only when the
nCAS is active while reading the internal data, however, it has a latch that the data will be
continuously outputted even after the nCAS is inactivated.
While configuring the software, you must set the timing register of SFR considering the clock speed and the DRAM spec.
5Mhz
MCLK
DRAMD
nWE
nOE
DRAMA
nCAS
nRAS
data 1
data0
row address
column
Trp
Trc Tc as
Tcas
addr
wait
wait
data
data
column
<EDO Read Timing Diagram>
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3-16
CIRCUIT DESCRIPTION
Samsung Electronics
Repair Manual
3-2-5-4 edo DRAM write timing
5Mhz
MCLK
DRAMD
nWE
nOE
DRAMA
nCAS
nRAS
data 1data 0
row address
column
Trp
Trc
Tcas
Tcas
addr
wait
wait
data
data
clock
type
Trp Trc Tcas
cycl e
#
register cycle
#
register cy cle
#
register
58Mhz
40 ns EDO 2 0x1 2 0x1 1 0x0
50 ns EDO 2 0x1 2 0x1 1 0x0
60 ns EDO 3 0x2 2 0x1 1 0x0
70 ns EDO 3 0x2 2 0x1 2 0x1
column
<FPM Write Timing Diagram>
<SFR Values Example for FPM>