Samsung SCX 5015 Circuit Description

Circuit Description

3. Circuit Description

3-1 Main PBA

3-1-1 Summary

The main circuit that consists of CPU, MFP controller (built-in 32bit RISC processor core: ARM946ES) including various I/O device drivers, system memory, scanner, printer, motor driver, PC I/F, and FAX transceiver controls the whole system. The entire structure of the main circuit is as follows :

DEV

SUPPLY

LCD 20x2line

SCAN

BLADE

OPE

CN8

CN2

6NC

24P

SMPS / HVPS

MICOM

Flash DIMM

+5V/+24V/+12V/+24Vs/Fuser

LCD Drive

NetworkCARD

PS3 (2MB)

Key Scan

CN15(100P)

10P

DEV MOTOR

CENTRONICS

36P

CABLE

3CN

SDRAM DIMM

FEED MOTOR

Platen

13NC

16MB

SCF

4NC

11P

LSU

CN15(100P)

15P D-SUB

7NC

D-SUB

1NC

THERMISTOR

OUT

BIN FULL

CONN.

PCNT

1CN

01N

FAN1

11NC

52NC

MAIN PBA

FAN1

HYPER

FLAT MOTOR

DEV CNT

81NC

DEV_ID

Option

23NC

71CN

TONER_TX

OPC

ADF

1NC

12NC

TONER_RX

USB CABLE

62NC

5NC

PTL

MOTOR

DRIVER

22P

CN1

CN28

CN22

COVER OPEN

CN20

CN27

CN30

CN3

CN24

S/W

DADF MOTOR

+24V / +5V

10P

PAPER SENSOR

External

TRANSFORMER

MODEM

LIU

3P x 2EA

CCD MODULE

EXT_PHONE

POS,DET

600/ / 600

Auditron

14P

SEPRATING

Tx: Rx

LINE1

PART

LINE

EXTERNAL

PHONE

EXTERNAL

SOLENOID

INT ERFACE

INTERFACE

PAPER

PHONE

PART

PICK_UP,DUPLEX,MP

SENSOR

FEED+P.EMP,EXIT,MP

3-1

Circuit Description

3-2 Circuit Operation

3-2-1 Clock

1) System Clock

Device	Oscillator

Frequency	12MHz

• ARM946ES RISC PROCESSOR: drives PLL internally uses 120MHz and external Bus uses 60 MHz.

2) Video Clock

Device	Oscillator

Frequency	57.0167MHz

• Fvd =((PAPER 1SCAN LINE sending time * SCAN effective late /1SCAN LINE DOT #)*4 =(600dpi*600dpi*58.208mm/s*216mm*4)/(25.4mm*25.4mm*76.1%)=28.697MHz

•PAPER 1SCAN LINE sending time=SCAN LINE interval/DOCUMENT SPEED (58.208mm/S) •1SCAN LINE DOT #=MAZ SCAN distance(216mm)*DOT# per 1mm

3)USB Clock

Device	Oscillator

Frequency	48MHz

3-2-2 POWER ON/OFF RESET

1) Signal Operation

Input Signal

+3.3V Power Line (VCC)

Output Signal

ARM946ES nRESET and 29LU16ø

• POWER ON/OFF DETECT VCC RISING/FALLING 4.5°≠ 4.6V

RESET TIME (Td)

1.48~1.52ms

• Td=(Ct*V sensing)/I charge (...Ct=33µF, Is=100µA)

2) TIMING CHART

MCLK

nRESET

5.461 ms

20 MCLK

nPWRGD

(65535 MCLK)

HICLK

reRESETn

CLK falling

5.461 ms

RESETn

(65535 MCLK)

15 HCLK

3-2

Circuit Description

3-2-3 RISC MICROPROCESSOR

1) RISC MICROCESSOR PIN & INTERFACE(SPGPm)

Ball No	Pin No	Pin Name	I/O	Description	PAD

B1	1	SD15	I/O	SDRAM Bus Data[15]	BD8TARP_TC

C2	2	VSS_PLL1	-	VSS for Core PLL	-

D2	3	VDD_PLL1	-	VDD for Core PLL (1.8V)	-

D3	4	DATA0 / GPI1	I/O	ROM Bus Data[0] / GPI[1]	BD8TRP_FT

E4	5	MCLK	I	Core PLL Clock Input (12MHz)	TLCHT_TC

C1	6	DATA6 / GPI7	I/O	ROM Bus Data[6] / GPI[7]	BD8TRP_FT

D1	7	DATA1 / GPI2	I/O	ROM Bus Data[1] / GPI[2]	BD8TRP_FT

E3	8	DATA5 / GPI6	I/O	ROM Bus Data[5] / GPI[6]	BD8TRP_FT

E2	9	VDD_RING_OSC	-	VDD for Ring Oscillator (1.8V)	-

E1	10	DATA3 / GPI4	I/O	ROM Bus Data[3] / GPI[4]	BD8TRP_FT

F3	11	DATA9 / GPI10	I/O	ROM Bus Data[9] / GPI[10]	BD8TRP_FT

G4	12	GND	-	GROUND_RING	-

F2	13	DATA8 / GPI9	I/O	ROM Bus Data[8] / GPI[9]	BD8TRP_FT

F1	14	DATA7 / GPI8	I/O	ROM Bus Data[7] / GPI[8]	BD8TRP_FT

G3	15	DATA12 / GPI13	I/O	ROM Bus Data[12] / GPI[13]	BD8TRP_FT

G2	16	DATA11 / GPI12	I/O	ROM Bus Data[11] / GPI[12]	BD8TRP_FT

G1	17	DATA10 / GPI11	I/O	ROM Bus Data[10] / GPI[11]	BD8TRP_FT

H3	18	DATA4 / GPI5	I/O	ROM Bus Data[4] / GPI[5]	BD8TRP_FT

H2	19	DATA15 / GPI16	I/O	ROM Bus Data[15] / GPI[16]	BD8TRP_FT

H1	20	DATA14 / GPI15	I/O	ROM Bus Data[14] / GPI[15]	BD8TRP_FT

J4	21	VDD_CORE	-	VDD for CORE (1.8V)	-

J3	22	DATA19	I/O	ROM Bus Data[19]	BD8TRP_FT

J2	23	DATA18	I/O	ROM Bus Data[18]	BD8TRP_FT

J1	24	DATA17	I/O	ROM Bus Data[17]	BD8TRP_FT

K2	25	DATA16	I/O	ROM Bus Data[16]	BD8TRP_FT

K3	26	DATA22	I/O	ROM Bus Data[22]	BD8TRP_FT

K1	27	DATA13 / GPI14	I/O	ROM Bus Data[14] / GPI[14]	BD8TRP_FT

L1	28	DATA20	I/O	ROM Bus Data[20]	BD8TRP_FT

L2	29	DATA21	I/O	ROM Bus Data[21]	BD8TRP_FT

L3	30	DATA25	I/O	ROM Bus Data[25]	BD8TRP_FT

L4	31	DATA26	I/O	ROM Bus Data[26]	BD8TRP_FT

M1	32	DATA23	I/O	ROM Bus Data[23]	BD8TRP_FT

M2	33	DATA24	I/O	ROM Bus Data[24]	BD8TRP_FT

M3	34	DATA29	I/O	ROM Bus Data[29]	BD8TRP_FT

M4	35	DATA30	I/O	ROM Bus Data[30]	BD8TRP_FT

N1	36	DATA27	I/O	ROM Bus Data[27]	BD8TRP_FT

N2	37	DATA28	I/O	ROM Bus Data[28]	BD8TRP_FT

N3	38	VDD_ARM	-	VDD for ARM	-

P1	39	DATA31	I/O	ROM Bus Data[31]	BD8TRP_FT

P2	40	DATA2 / GPI3	I/O	ROM Bus Data[2] / GPI[3]	BD8TRP_FT

R1	41	VDD_CORE	-	VDD for CORE (1.8V)	-

P3	42	nROMCS2	O	ROM Bank2 Select_n	B4TR_TC

3-3

Circuit Description

Ball No	Pin No	Pin Name	I/O	Description	PAD

R2	43	nRD	O	ROM Bus Read_n	B4TR_TC

T1	44	nROMCS0	O	ROM Bank0 Select_n	B4TR_TC

P4	45	nROMCS3 / nIOCS3 /	O	ROM Bank3 Select_n / IO Bank3	B4TR_TC
		GPO1		Select_n / GPO[1]

R3	46	nWR	O	ROM Bus Write_n	B4TR_TC

T2	47	nROMCS1	O	ROM Bank1 Select_n	B4TR_TC

U1	48	ADDR12	O	ROM Bus Addr[12]	B8TR_TC

T3	49	ADDR10	O	ROM Bus Addr[10]	B8TR_TC

U2	50	ADDR13	O	ROM Bus Addr[13]	B8TR_TC

V1	51	ADDR15	O	ROM Bus Addr[15]	B8TR_TC

T4	52	ADDR11	O	ROM Bus Addr[11]	B8TR_TC

U3	53	ADDR14	O	ROM Bus Addr[14]	B8TR_TC

V2	54	ADDR16	O	ROM Bus Addr[16]	B8TR_TC

W1	55	ADDR19	I/O	ROM Bus Addr[19]	BD8TRP_TC

V3	56	ADDR17	I/O	ROM Bus Addr[17]	BD8TRP_TC

W2	57	ADDR20	I/O	ROM Bus Addr[20]	BD8TRP_TC

Y1	58	nIOCS0	O	IO Bank0 Select_n	B4TR_TC

W3	59	ADDR21	I/O	ROM Bus Addr[21]	BD8TRP_TC

Y2	60	nIOCS1	O	IO Bank1 Select_n	B4TR_TC

W4	61	ADDR22	I/O	ROM Bus Addr[22]	BD8TRP_TC

V4	62	ADDR18	I/O	ROM Bus Addr[18]	BD8TRP_TC

U5	63	ADDR7	O	ROM Bus Addr[7]	B8TR_TC

Y3	64	VDD_CORE	O	VDD for CORE (1.8V)	-

Y4	65	nIOCS2 / nDACK0 /	O	IO Bank2 Select_n / DMA IO Bank0	B4TR_TC
		GPO2		ACK_n / GPO[2]

V5	66	ADDR1	O	ROM Bus Addr[1]	B8TR_TC

W5	67	ADDR8	O	ROM Bus Addr[8]	B8TR_TC

Y5	68	ADDR9	O	ROM Bus Addr[9]	B8TR_TC

V6	69	ADDR4	O	ROM Bus Addr[4]	B8TR_TC

U7	70	ADDR6	O	ROM Bus Addr[6]	B8TR_TC

W6	71	ADDR2	O	ROM Bus Addr[2]	B8TR_TC

Y6	72	ADDR3	O	ROM Bus Addr[3]	B8TR_TC

V7	73	ADDR5	O	ROM Bus Addr[5]	B8TR_TC

W7	74	VDD_ARM	-	VDD for ARM Hard Macro(1.8V)	-

Y7	75	VDD_CORE	-	VDD for CORE (1.8V)	-

V8	76	EINT0 / TnRST	I	Ext. Interrupt0 / TAP Controller	SCHMITT_FT
				Reset_n

W8	77	EINT1 / TCK	I	Ext. Interrupt1 / TAP Controller	SCHMITT_FT
				Clock

Y8	78	EINT2 / nRXD2 / TMS	I	Ext. Interrupt2 / UART RX DATA[2] /	SCHMITT_FT
				TAP Controller Mode Select

U9	79	EINT3 / nTXD2 / GPO9	I/O	Ext. Interrupt3 / UART TX Data[2] /	BD4STRP_FT
				GPO[9]

V9	80	nRxD0	I	UART RX Data[0]	SCHMITT_FT

W9	81	nRxD1 / GPI17 / TDI	I	UART RX Data[1] / GPI[17] / TAP	SCHMITT_FT
				Controller Data In

Y9	82	nTxD0	O	UART TX Data[0]	B4TR_TC

W10	83	TESTMODE	I	TESTMODE (Nomal : 0)	SCHMITT_TC

3-4

					Circuit Description

Ball No	Pin No	Pin Name	I/O	Description	PAD

V10	84	nTxD1 / GPO10 / TDO	O	UART Tx Data[1] / GPO[10] / Tap	B4TR_TC
				Controller Data Out

Y10	85	TESTSE	I	TESTSE (Normal : 0)	SCHMITT_TC

Y11	86	VDD_CORE	-	VDD for CORE (1.8V)	-

W11	87	RXERR / GPI25	I	MAC RX Error / GPI[25]	SCHMITT_TC

V11	88	GND	-	GROUND_RING	-

U11	89	RX_DV / GPI20	O	MAC RX Data Valid / GPI[20]	SCHMITT_TC

Y12	90	RXD0 / GPI21	O	MAC RX Data[0] / GPI[21]	SCHMITT_TC

W12	91	nLFPHB1 / nPRINT	O	Motor Out B_n / Print Start_n	B4TR_TC

V12	92	nLFPHB0 / nCMSG	O	Motor Out B / Command	B4TR_TC
				Message_n

U12	93	nLFPHA0 / CCLK	O	Motor Out A / Communication Clock	B4TR_TC

Y13	94	RXD1 / GPI22	I	MAC RX Data[1] / GPI[22]	SCHMITT_TC

W13	95	VDO	O	Video Data Out	B8TR_TC

V13	96	SPD / nDREQ3	I/O	DIMM Detect / DMA REQ[3]_n	BD4SRTP_TC

Y14	97	nWAIT1 / CRS	I	Wait_n / MAC Carrier Sensor	SCHMITT_TC

W14	98	COL / EINT4	I	MAC Collision Detect / Ext.	SCHMITT_TC
				Interrupt4

Y15	99	TX_EN	O	MAC TX Enable	B4TR_TC

V14	100	MDIO	I/O	MAC Management Data Inout	BD4STRUQP_TC

W15	101	TXD3 / GPO14	O	MAC TX Data[3] / GPO[14]	B4TR_TC

Y16	102	TXD2 / GPO13	O	MAC TX Data[2] / GPO[13]	B4TR_TC

U14	103	MDC / GPO15	O	MAC Management Data Clock /	B4TR_TC
				GPO[15]

V15	104	TXCLK / GPI18	I	MAC TX Clock(25MHz) / GPI[18]	SCHMITT_TC

W16	105	TXD1 / GPO12	O	MAC TX Data[1] / GPO[12]	B4TR_TC

Y17	106	PD4	I/O	Parallel Port Data[4]	BD4STRP_FT

V16	107	TXD0 / nIOCS3	O	MAC TX Data[0] / IO Bank3	B4TR_TC
				Select_n

W17	108	RXD3 / GPI24	I	MAC RX Data[3] / GPI[24]	SCHMITT_TC

Y18	109	PD2	I/O	Parallel Port Data[2]	BD4STRP_FT

U16	110	PD6	I/O	Parallel Port Data[6]	BD4STRP_FT

V17	111	RXD2	I	MAC RX Data[2] / GPI[23]	SCHMITT_TC

W18	112	PWMOUT2	O	PWM Output[2]	B4TR_TC

Y19	113	VCLK	I	Video Reference Clock	TLCHT_TC

V18	114	RXCLK / GPI19	I	MAC RX Clock(25MHz) / GPI[19]	SCHMITT_TC

W19	115	PD1	I/O	Parallel Port Data[1]	BD4STRP_FT

Y20	116	nINIT	I	Parallel Port Initialization_n	SCHMITT_FT

W20	117	VSS_ADC	-	VSS for ADC	-

V19	118	ATEST_OUT	O	ADC Test Output	ANA_TC

U19	119	AIN2	I	ADC Channel2 Input	ANA_TC

U18	120	AIN1	I	ADC Channel1 Input	ANA_TC

T17	121	AIN0	I	ADC Channel0 Input	ANA_TC

V20	122	VDD_ADC	-	Analog power for ADC (3.3V)	-

U20	123	VDD_CORE	-	VDD for CORE (1.8V)	-

T18	124	GND	-	GROUND_RING	-

T19	125	VDD_CORE	-	VDD for CORE (1.8V)	-

3-5

Circuit Description

Ball No	Pin No	Pin Name	I/O	Description	PAD

T20	126	VDD_CORE	-	VDD for CORE (1.8V)	-

R18	127	VBUS	I	USB Detect	SCHMITT_FT

P17	128	nLREADY / nEBSY	I	LSU Ready_n / Engine Busy_n	SCHMITT_FT

R19	129	nSELECTIN	I	Parallel Port Select Input_n	SCHMITT_FT

R20	130	LSUCLK / nCBSY /	O	LSU Clock / Command Busy_n /	B4TR_TC
		GPO11		GPO[11]

P18	131	PD7	I/O	Parallel Port Data[7]	BD4STRP_FT

P19	132	PWMOUT1	O	PWM Output[1]	B4TR_TC

P20	133	PWMOUT0	O	PWM Output[0]	B4TR_TC

N18	134	nEMSG / nDACK3 /	I/O	Engine Message_n / DMA	BD4STRP_FT
		PWMOUT3		ACK[3]_n / PWM Output[3]

N19	135	nFSYNC / nLFPHA1	I/O	Frame Sync_n / Motor Out A_n	BD4STRP_FT

N20	136	nHSYNC	I	Line Sync_n	SCHMITT_FT

M17	137	nSTROBE	I	Parallel Port Data Strobe_n	SCHMITT_FT

M18	138	PD5	I/O	Parallel Port Data[5]	BD4STRP_FT

M19	139	nWAIT0 / PDE	I/O	Wait_n / Parallel Port Data Enable	BD4STRP_TC

M20	140	nIOCS5 / nSCS4 /	O	DRAM Bank4 / IO Bank5 Select_n /	BD8TARP_TC
		GPO3 / TONEOUT		GPO[3] / Tone Pulse Out

L19	141	PD3	I/O	Parallel Port Data[3]	BD4STRP_FT

L18	142	nFAULT	O	Parallel Port Fault_n	B4TR_TC

L20	143	nDREQ0 / GPI0 /	I/O	DMA REQ[0]_n / GPI[0] / ADDR[23]	BD4STRP_TC
		ADDR23

K20	144	nRESET	I	External Reset_n Input	SCHMITT_TC

K19	145	PERROR	O	Parallel Port Paper Error	B4TR_TC

K18	146	nAUTOFD	I	Parallel Port Auto Feed_n	SCHMITT_FT

K17	147	nDACK2 / DQM7 /	O	DMA ACK[2]_n / DQM[7] / GPO[5]	BD8TARP_TC
		GPO5

J20	148	nDREQ2 / DQM6 /	I/O	DMA REQ[2]_n / DQM[6] / GPO[6]	BD8TARP_TC
		GPO6

J19	149	nDREQ1 / DQM4 /	I/O	DMA REQ[1]_n / DQM[4] / GPO[8]	BD8TARP_TC
		GPO8

J18	150	VDD_CORE	-	VDD for CORE (1.8V)	-

J17	151	nSCS0	O	SDRAM Bank0 Select_n	BD8TARP_TC

H20	152	nSCS2	O	SDRAM Bank2 Select_n	BD8TARP_TC

H19	153	nCAS	O	SDRAM Column Address Select_n	BD8TARP_TC

H18	154	nSCS1	O	SDRAM Bank1 Select_n	BD8TARP_TC

G20	155	nIOCS4 / nSCS3 /	O	IO Bank4 / SDRAM Bank3 Select_n	BD8TARP_TC
		GPO4		/ GPO[4]

G19	156	BUSY	O	Parallel Port Busy	B4TR_TC

F20	157	PD0	I/O	Parallel Port Data[0]	BD4STRP_FT

G18	158	SLCT_OUT	O	Parallel Port Selection Out	B4TR_TC

F19	159	nACK	O	Parallel Port Acknowledge_n	B4TR_TC

E20	160	nDACK1 / DQM5 /	O	DMA ACK[1]_n / DQM[5] / GPO[7]	BD8TARP_TC
		GPO7

G17	161	nRSTOUT / CLKOUT /	O	Internal Reset_n Out / Internal Sys-	B8TR_TC
		GPO0		tem Clock Out / GPO[0]

F18	162	SA7	O	SDRAM Bus Addr[7]	BD8TARP_TC

E19	163	SA9	O	SDRAM Bus Addr[9]	BD8TARP_TC

3-6

					Circuit Description

Ball No	Pin No	Pin Name	I/O	Description	PAD

D20	164	VDD_USB	-	VDD for USB Hard Macro (1.8V)	-

E18	165	SA10	O	SDRAM Bus Addr[10]	BD8TARP_TC

D19	166	SA12	O	SDRAM Bus Addr[120	BD8TARP_TC

C20	167	BA0	O	SDRAM Bus Bank Select Addr[0]	BD8TARP_TC

E17	168	nRAS	O	SDRAM Row Address Select_n	BD8TARP_TC

D18	169	DQM2	O	SDRAM Bus DQM[2]	BD8TARP_TC

C19	170	DQM1	O	SDRAM Bus DQM[1]	BD8TARP_TC

B20	171	BA1	O	SDRAM Bus Bank Select Addr[1]	BD8TARP_TC

C18	172	DQM0	O	SDRAM Bus DQM[0]	BD8TARP_TC

B19	173	DQM3	O	SDRAM Bus DQM[3]	BD8TARP_TC

A20	174	RREF	I/O	USB PHY Register Reference	ANA_FT

A19	175	VSSL	-	VSS for Deserialisation Flip ﬂops	-

B18	176	VDDL	-	VDD for Deserialisation Flip ﬂops	-
				(1.8V)

B17	177	VSSB	-	VSS for buffers	-

C17	178	DMNS	I/O	USB2 DATA-	ANA_FT

D16	179	DPLS	I/O	USB2 DATA+	ANA_FT

A18	180	VDD3_USB	-	VDD for USB1.1 FS compliance	-
				(3.3V)

A17	181	VSSC	-	VSS for DLL and Xor tree	-

C16	182	VDDC	-	VDD for DLL and Xor tree (1.8V)	-

B16	183	VDDB	-	VDD for buffers (1.8V)	-

A16	184	VDD_USB	-	VDD for USB Hard Macro (1.8V)	-

C15	185	UCLK	I	USB PLL Input Clock (12MHz)	TLCHT_TC

D14	186	VSS_PLL2	-	VSS for USB PLL	-

B15	187	VDD_PLL2	-	VSS for USB PLL (1.8V)	-

A15	188	SA11	O	SDRAM Bus Addr[11]	BD8TARP_TC

C14	189	SA6	O	SDRAM Bus Addr[6]	BD8TARP_TC

B14	190	SA5	O	SDRAM Bus Addr[5]	BD8TARP_TC

A14	191	SA8	O	SDRAM Bus Addr[8]	BD8TARP_TC

C13	192	SA3	O	SDRAM Bus Addr[3]	BD8TARP_TC

B13	193	SA2	O	SDRAM Bus Addr[2]	BD8TARP_TC

A13	194	SA4	O	SDRAM Bus Addr[4]	BD8TARP_TC

D12	195	SA0	O	SDRAM Bus Addr[0]	BD8TARP_TC

C12	196	SA1	O	SDRAM Bus Addr[1]	BD8TARP_TC

B12	197	CKE	O	SDRAM Clock Enable	BD8TARP_TC

A12	198	nWE	O	SDRAM Write Enable_n	BD8TARP_TC

B11	199	SD30	I/O	SDRAM Bus Data[30]	BD8TARP_TC

C11	200	SD31	I/O	SDRAM Bus Data[31]	BD8TARP_TC

A11	201	SD29	I/O	SDRAM Bus Data[29]	BD8TARP_TC

A10	202	SD25	I/O	SDRAM Bus Data[25]	BD8TARP_TC

B10	203	SD26	I/O	SDRAM Bus Data[26]	BD8TARP_TC

C10	204	SD27	I/O	SDRAM Bus Data[27]	BD8TARP_TC

D10	205	SD28	I/O	SDRAM Bus Data[28]	BD8TARP_TC

A9	206	SD21	I/O	SDRAM Bus Data[21]	BD8TARP_TC

B9	207	SD22	I/O	SDRAM Bus Data[22]	BD8TARP_TC

3-7

Circuit Description

Ball No	Pin No	Pin Name	I/O	Description	PAD

C9	208	SD23	I/O	SDRAM Bus Data[23]	BD8TARP_TC

D9	209	SD24	I/O	SDRAM Bus Data[24]	BD8TARP_TC

A8	210	SD18	I/O	SDRAM Bus Data[18]	BD8TARP_TC

B8	211	SDCLK0	O	SDRAM Clock Output0	BD8TARP_TC

C8	212	SD20	I/O	SDRAM Bus Data[20]	BD8TARP_TC

A7	213	SD14	I/O	SDRAM Bus Data[14]	BD8TARP_TC

B7	214	SD19	I/O	SDRAM Bus Data[19]	BD8TARP_TC

A6	215	SD11	I/O	SDRAM Bus Data[11]	BD8TARP_TC

C7	216	SD16	I/O	SDRAM Bus Data[16]	BD8TARP_TC

B6	217	SDCLK1	O	SDRAM Clock Output1	BD8TARP_TC

A5	218	SD12	I/O	SDRAM Bus Data[12]	BD8TARP_TC

D7	219	SD17	I/O	SDRAM Bus Data[17]	BD8TARP_TC

C6	220	SD13	I/O	SDRAM Bus Data[13]	BD8TARP_TC

B5	221	SD8	I/O	SDRAM Bus Data[8]	BD8TARP_TC

A4	222	SD5	I/O	SDRAM Bus Data[5]	BD8TARP_TC

C5	223	SD9	I/O	SDRAM Bus Data[9]	BD8TARP_TC

B4	224	SD6	I/O	SDRAM Bus Data[6]	BD8TARP_TC

A3	225	SD3	I/O	SDRAM Bus Data[3]	BD8TARP_TC

D5	226	SD10	I/O	SDRAM Bus Data[10]	BD8TARP_TC

C4	227	SD7	I/O	SDRAM Bus Data[7]	BD8TARP_TC

B3	228	SD4	I/O	SDRAM Bus Data[4]	BD8TARP_TC

B2	229	SD1	I/O	SDRAM Bus Data[1]	BD8TARP_TC

A2	230	SD0	I/O	SDRAM Bus Data[0]	BD8TARP_TC

C3	231	SD2	I/O	SDRAM Bus Data[2]	BD8TARP_TC

3-8

					Circuit Description
2) RISC MICROCESSOR PIN & INTERFACE(CIP4)

No	Pin Name	I/O	Description	Pad Type	Current drive

1	GND2	P	Vss Supply	vss2i	-

2	NTEST	I	Nand Tree Test Mode Selection	pticd	-

3	TM	I	Global Test Mode Selection	pticd	-

4	TEST1	I	Test Mode Selection 1	pticd	-

5	GND17	P	Vss Supply	vss3op	-

6	TEST2	I	Test Mode Selection 2	pticd	-

7	XDACK1	I	DMA Acknowledge Signal 1	ptis	-

8	XDREQ1	O	DMA Request Signal 1	phob4	4mA

9	VDD1	P	Vdd Supply	vdd2i	-

10	XDACK2	I	DMA Acknowledge Signal 2	ptis	-

11	XDREQ2	O	DMA Request Signal 2	phob4	4mA

12	XDACK3	I	DMA Acknowledge Signal 3	ptis	-

13	XDREQ3	O	DMA Request Signal 3	phob4	4mA

14	nRESET	I	Global Reset	ptis	-

15	CLK_OUT	O	PLL Clock Out	phob12	12mA

16	GND3	P	Vss Supply	vss2i	-

17	XP	I	Clock Oscillation Input	phsoscm26	10~40MHz

18	XPOUT	O	Clock Oscillation Output	phsoscm26	10~40MHz

19	GNDD16	P	Vss Supply	vss2t_abb	-

20	FILTER*	O	PLL Filter Pump Out	poar50_abb	-

21	GND1	P	Vss Supply	vbb_abb	-

22	VDDA9,VDDD9	P	Vdd Supply	vdd2t_abb	-

23	GND24,GND33	P	Vss Supply	vss3t_abb	-

24	RTC_XO	O	RTC Clock Oscillation Output	poar50_abb	-

25	RTC_XI	I	RTC Clock Oscillation Input	piar50_abb	-

26	VDD8,VDD18	P	Vdd Supply	vdd3t_abb	-

27	IRQ	O	Interrupt Request Signal	phob4	4mA

28	nCS	I	CIP4 Chip Select	ptis	-

29	GND4	P	Vss Supply	vss2i	-

30	nRD	I	CIP4 CPU Read Control	ptis	-

31	nWR	I	CIP4 CPU Write Control	ptis	-

32	BA1	I	Bank Address Bus [1]	ptis	-

33	BA0	I	Bank Address Bus [0]	ptis	-

34	GND19	P	Vss Supply	vss3op	-

35	A5	I	CPU Address Bus [5]	ptis	-

36	A4	I	CPU Address Bus [4]	ptis	-

37	A3	I	CPU Address Bus [3]	ptis	-

38	VDD2	P	Vdd Supply	vdd2i	-

39	A2	I	CPU Address Bus [2]	ptis	-

40	A1	I	CPU Address Bus [1]	ptis	-

41	A0	I	CPU Address Bus [0]	ptis	-

42	GND5	P	Vss Supply	vss2i	-

43	D31	B	CPU Data Bus [31]	phbst8	8mA

3-9

Circuit Description

No	Pin Name	I/O	Description	Pad Type	Current drive

44	D30	B	CPU Data Bus [30]	phbst8	8mA

45	D29	B	CPU Data Bus [29]	phbst8	8mA

46	D28	B	CPU Data Bus [28]	phbst8	8mA

47	GND20	P	Vss Supply	vss3op	-

48	D27	B	CPU Data Bus [27]	phbst8	8mA

49	D26	B	CPU Data Bus [26]	phbst8	8mA

50	D25	B	CPU Data Bus [25]	phbst8	8mA

51	VDD11	P	Vdd Supply	vdd3op	-

52	D24	B	CPU Data Bus [24]	phbst8	8mA

53	D23	B	CPU Data Bus [23]	phbst8	8mA

54	D22	B	CPU Data Bus [22]	phbst8	8mA

55	D21	B	CPU Data Bus [21]	phbst8	8mA

56	GND6	P	Vss Supply	vss2i	-

57	D20	B	CPU Data Bus [20]	phbst8	8mA

58	D19	B	CPU Data Bus [19]	phbst8	8mA

59	D18	B	CPU Data Bus [18]	phbst8	8mA

60	GND21	P	Vss Supply	vss3op	-

61	D17	B	CPU Data Bus [17]	phbst8	8mA

62	D16	B	CPU Data Bus [16]	phbst8	8mA

63	D15	B	CPU Data Bus [15]	phbst8	8mA

64	D14	B	CPU Data Bus [14]	phbst8	8mA

65	VDD3	P	Vdd Supply	vdd2i	-

66	D13	B	CPU Data Bus [13]	phbst8	8mA

67	D12	B	CPU Data Bus [12]	phbst8	8mA

68	D11	B	CPU Data Bus [11]	phbst8	8mA

69	GND7	P	Vss Supply	vss2i	-

70	D10	B	CPU Data Bus [10]	phbst8	8mA

71	D9	B	CPU Data Bus [9]	phbst8	8mA

72	D8	B	CPU Data Bus [8]	phbst8	8mA

73	D7	B	CPU Data Bus [7]	phbst8	8mA

74	GND22	P	Vss Supply	vss3op	-

75	D6	B	CPU Data Bus [6]	phbst8	8mA

76	D5	B	CPU Data Bus [5]	phbst8	8mA

77	D4	B	CPU Data Bus [4]	phbst8	8mA

78	VDD12	P	Vdd Supply	vdd3op	-

79	D3	B	CPU Data Bus [3]	phbst8	8mA

80	D2	B	CPU Data Bus [2]	phbst8	8mA

81	D1	B	CPU Data Bus [1]	phbst8	8mA

82	D0	B	CPU Data Bus [0]	phbst8	8mA

83	GND8	P	Vss Supply	vss2i	-

84	TX_EN1	O	Motor Control Tx Enable 1	phob4	4mA

85	TX_EN2	O	Motor Control Tx Enable 2	phob4	4mA

86	TX_A	O	Motor Control Tx Channel A	phob4	4mA

87	TX_B	O	Motor Control Tx Channel B	phob4	4mA

88	GND23	P	Vss Supply	vss3op	-

3-10

					Circuit Description

No	Pin Name	I/O	Description	Pad Type	Current drive

89	nTX_A	O	Motor Control Tx Channel A	phob4	4mA

90	nTX_B	O	Motor Control Tx Channel A	phob4	4mA

91	MOTOR_POL	I	Motor Polarity	ptis	4mA

92	VDD4	P	Vdd Supply	vdd2i	-

93	PItg1	O	CIS/CCD PItg1 Signal	phob8	8mA

94	PI1	O	CIS/CCD PI1 Signal	phob8	8mA

95	PI2	O	CIS/CCD PI2 Signal	phob8	8mA

96	GND9	P	Vss Supply	vss2i	-

97	PIrs	O	CIS/CCD PIrs Signal	phob8	8mA

98	PIcp	O	CIS/CCD PIsh Signal	phob8	8mA

99	ADC_CLK	O	AFE ADC Clock	phob8	8mA

100	VDD13	P	Vdd Supply	vdd3op	-

101	CDS2_CLK	O	AFE CDS2 Clock	phob8	8mA

102	SCLK1	O	AFE SIO Sync. Clock	phob8	8mA

103	SLOAD1	O	AFE SIO Read/Write Control Signal	phob8	8mA

104	VDD10	P	Vdd Supply	vdd3op	-

105	SDO1	O	AFE SIO Serial Output 1	phob8	8mA

106	SDIO1	B	AFE SIO Serial Inout/Output 1	phbst8	8mA

107	SDIO2	B	AFE SIO Serial Inout/Output 2	phbst8	8mA

108	GND10	P	Vss Supply	vss2i	-

109	AFE_D9	I	A/D Converted Data Bus [9]	ptis	-

110	AFE_D8	I	A/D Converted Data Bus [8]	ptis	-

111	AFE_D7	I	A/D Converted Data Bus [7]	ptis	-

112	AFE_D6	I	A/D Converted Data Bus [6]	ptis	-

113	VDD5	P	Vdd Supply	vdd2i	-

114	AFE_D5	I	A/D Converted Data Bus [5]	ptis	-

115	AFE_D4	I	A/D Converted Data Bus [4]	ptis	-

116	AFE_D3	I	A/D Converted Data Bus [3]	ptis	-

117	GND25	P	Vss Supply	vss3op	-

118	AFE_D2	I	A/D Converted Data Bus [2]	ptis	-

119	AFE_D1	I	A/D Converted Data Bus [1]	ptis	-

120	AFE_D0	I	A/D Converted Data Bus [0]	ptis	-

121	GND11	P	Vss Supply	vss2i	-

122	SRAM_A15	O	SRAM Address Bus [15]	phob8	8mA

123	SRAM_A14	O	SRAM Address Bus [14]	phob8	8mA

124	SRAM_A13	O	SRAM Address Bus [13]	phob8	8mA

125	SRAM_A12	O	SRAM Address Bus [12]	phob8	8mA

126	VDD14	P	Vdd Supply	vdd3op	-

127	SRAM_A11	O	SRAM Address Bus [11]	phob8	8mA

128	SRAM_A10	O	SRAM Address Bus [10]	phob8	8mA

129	SRAM_A9	O	SRAM Address Bus [9]	phob8	8mA

130	GND26	P	Vss Supply	vss3op	-

131	SRAM_A8	O	SRAM Address Bus [9]	phob8	8mA

132	SRAM_A7	O	SRAM Address Bus [9]	phob8	8mA

133	SRAM_A6	O	SRAM Address Bus [9]	phob8	8mA

3-11

Circuit Description

No	Pin Name	I/O	Description	Pad Type	Current drive

134	SRAM_A5	O	SRAM Address Bus [9]	phob8	8mA

135	GND12	P	Vss Supply	vss2i	-

136	SRAM_A4	O	SRAM Address Bus [9]	phob8	8mA

137	SRAM_A3	O	SRAM Address Bus [9]	phob8	8mA

138	SRAM_A2	O	SRAM Address Bus [9]	phob8	8mA

139	SRAM_A1	O	SRAM Address Bus [9]	phob8	8mA

140	VDD6	P	Vdd Supply	vdd2i	-

141	SRAM_A0	O	SRAM Address Bus [9]	phob8	8mA

142	SRAM_nWR	O	SRAM Write Enable Signal	phob8	8mA

143	SRAM_D15	B	SRAM Data Bus [15]	phbst8	8mA

144	SRAM_D14	B	SRAM Data Bus [14]	phbst8	8mA

145	GND27	P	Vss Supply	vss3op	-

146	SRAM_D13	B	SRAM Data Bus [13]	phbst8	8mA

147	SRAM_D12	B	SRAM Data Bus [12]	phbst8	8mA

148	SRAM_D11	B	SRAM Data Bus [11]	phbst8	8mA

149	GND13	P	Vss Supply	vss2i	-

150	SRAM_D10	B	SRAM Data Bus [10]	phbst8	8mA

151	SRAM_D9	B	SRAM Data Bus [9]	phbst8	8mA

152	SRAM_D8	B	SRAM Data Bus [8]	phbst8	8mA

153	SRAM_D7	B	SRAM Data Bus [7]	phbst8	8mA

154	VDD15	P	Vdd Supply	vdd3op	-

155	SRAM_D6	B	SRAM Data Bus [6]	phbst8	8mA

156	SRAM_D5	B	SRAM Data Bus [5]	phbst8	8mA

157	SRAM_D4	B	SRAM Data Bus [4]	phbst8	8mA

158	GND28	P	Vss Supply	vss3op	-

159	SRAM_D3	B	SRAM Data Bus [3]	phbst8	8mA

160	SRAM_D2	B	SRAM Data Bus [2]	phbst8	8mA

161	SRAM_D1	B	SRAM Data Bus [1]	phbst8	8mA

162	SRAM_D0	B	SRAM Data Bus [0]	phbst8	8mA

163	GND14	P	Vss Supply	vss2i	-

164	GPO7/PItg2	O	General Purpose Output [7]	phob8	8mA

165	GPO6/RLED	O	General Purpose Output [6]	phob8	8mA

166	GPO5/GLED	O	General Purpose Output [5]	phob8	8mA

167	GPO4/BLED	O	General Purpose Output [4]	phob8	8mA

168	VDD7	P	Vdd Supply	vdd2i	-

169	GPO3/PItg3	O	General Purpose Output [3]	phob8	8mA

170	GPO2/PIsh	O	General Purpose Output [2]	phob8	8mA

171	GPO1/	O	General Purpose Output [1]	phob8	8mA
	LEVEL_SHIFT

172	GPO0	O	General Purpose Output [0]	phob8	8mA

173	GND29	P	Vss Supply	vss3op	8mA

174	GPIO2B/AFE_D11	B	General Purpose Input/Output 2 [11]	phbst8	8mA

175	GPIO2A/AFE_D10	B	General Purpose Input/Output 2 [10]	phbst8	-

176	GPIO29/AFE_D9	B	General Purpose Input/Output 2 [9]	phbst8	8mA

177	GND30	P	Vss Supply	vss3op	8mA

178	GPIO28/AFE_D8	B	General Purpose Input/Output 2 [8]	phbst8	8mA

3-12

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