Samsung SCX 4920N Circuit Description

Circuit Diagram

Service Manual

11-1

11. Circuit Description

11.1 System Configurations

SCX-4920N is roughly made up Main Control part, Operation Panel part, Scanner part, Line Interface part and

Power part. Each Part is separated Module which focus on common and standard design of different kind products. main control part adopting Fax & LBP Printer exclusive Controller is composed of 2 CPU and 1 Board. Scanner part is composed of ADF and Platen and is connected with Main by Harness . Line Interface part is designed to apply TBR21 standard(Domestic, Europe,etc..)

MHV

+5V/ +12V +24V +24VS

INLET &

POWER S/W

PAPER EMPTY

SENSOR

EXIT SENSOR

MP EMPTY

SENSOR

FEED SENSOR

COVER S/W

AC PWR

SUPPLY

DEV

THV

OPC GND

SPGPm

ARM946ES

CACHE(16K*2)

SDRAM Control

ROM Control DMA Control

PVC

GEU/HCT/gCOD

I/O I/F

Engine Control

IEEE1284/USB2.0

MAIN MOTOR

DRIVER

A3977S LR

Reset

THERM

26P

MODEM SFM336

33.6KBP

AUDIO Drv.

600 DPI, COLOR CCD

MAIN MOTOR

FLATEN MOTOR

FAST SRA M

(128 KB yte)

CIP4

Image P rocesser

AFE I/F

I/O PORT

Motor Control

DMA Control

RTC

JBIG Codec

CIP 4 AFE

FLATEN MOTOR DRIVER

TEA3718 X 2EA

CCD DRIVING

PART

USB 2.0

IEEE1284

NETWORK

ADF UNIT

P-REGI, P-DET, P-POS

SENSOR

ADF MOTOR DRIVER

TEA3718 X 2EA

FLAT COVER SENSOR

LCD, 16*2 LINES

14P

FUSER

FAN

NE TWORK INTERFAC E CA RD

SCF (Option)

BootROM

(1MBX2ea or 2MBX2ea)

MEMO RY DIMM

Smart DAA

CX20493

PS3 / PCL6 DIMM(SEC)

SRAM

(128KByte) or

Not Used

SDRAM(16MB or 32MB)

DRAM Backup logic

PCL6(2MB x 2ea)

PS3(2MB x 2 ea) : DELL

LINE

EXT. PHONE

LSU

11P

PTL

DEV_FUSE

MAIN CLUTCH

MP CLUTCH

TONER RX

CARIDGE INFO.

TONER TX

AC 110V/220V

MICOM LCD/LED Drive Key Scan

OPE

MAIN

SMPS

HVPS

Service Manual

Circuit Diagram

11-2

CPU Part

1) CPU : Use 32Bit RISC Processor, ARM946ES,which is exclusive controller to execute Printer & FAX Function and to execute operation block by flash memory within system program, and to control whole system.

- Main function block

- Completely Integrated System for Embedded Applications,

- 32 Bit Risc Architecture, Efficient and Powerful ARM9 Core.

- LSU Interface Module for Interfacing PVC or HPVC with LSU

- 2 Channel General Purpose DMA Controller for High Speed I/O

- Dual Memory Bus Architecture

- Operation Frequency : AHB Bus: 60MHz, Internal System Bus: 120MHz

- Operation Voltage : 3.3V

- POWER ON RESET TIME :

Laser MFP 1600n CONNECTION DIAGRAM

LCD MODUL E

16 X 2LINE

OPE B’d

1:DGND 2:+5V 3:OPE_TXD 4:OPE_RST 5:OPE_RXD 6 : nLED8

FLATE N

COVER

SENSOR

1:+5V 2:SIGNAL 3:GND

1,3,5,7,8 :DGND 2 : CCD_VOB 4 : CCD_VOR 6 : CCD_VOG 12,16,17,20 : DGND 9,10,11 : CCD_PI_TG 13 : CCD_PI_RS 14 : CCD_PI2 15 : CCD_PI1 16,17,20,24 : DGND 18 : CCD_PI_CP 19 : +5V 21 : CCD_HOME 22 : +24V 23 : INV_POWER

CCD MODULE

FLATEN

MOTOR

1:MA 2:MB 3:MA 4:MB

ADF MOTOR DRIVER

SENSOR

-P_POS

-P_PEG

-P_DET

ADF

MOTOR

1:MA 2:MB 3:MA 4:MB

1,4,11,15 : DGND 2:+24V 3:+5V 5:ADF_NA 6:ADF_PHB 7:ADF_PHA 8:ADF_B 9:ADF_NA 10 : ADF_NA 12 : nADF_P_DET 13 : nADF_DET 14 : nADF_P_REG 16 : nADF_P_POS

SCF Unit

1:+3.3V 2 : nS CF_STATUS 3:SCF_CMD 4:SCF_CLK 5:SCF_READY 6:+24V 7,8 : DGND

MAIN

MOTOR

1:MA 2:MB 3:MA 4:MB

1 : P_ EMPT Y 3,4 : +5V 7:+12V 13 : MP_EMPTY 15,22,23 : N.C 17 : N.C 19 : THV_EN 21 : MHV_PWM 25 : FUSER_ON

SMPS / HVPS

MAIN

CLUTCH

PTL

1:SIGNAL 2:N.C 3:+4VS

1:+24VS 2:SIGNAL

1:+5V 2:SIGNAL

TONER

CARTRIDGE

1:SIGNAL 2:N.C 3:+24VS

1:+24VS 2:SIGNAL

1:+3.3V 2:CART_DIN

SENSOR

-MPSENSOR

-P_EMPSEN.

-EXITSEN.

- FEED SEN SWITCH

-DOOROPEN

2:P_FEED 5,6,8,9,10 : GND 11,12 : +24VS 14 : +24V 16 : THV_READ 18 : THV_PWM 20 : DEV_PWM 24 : FAN 26 : P_EXIT

1:LSUCLK 3:nPMOTOR 5:+24VS 7:+5V

LSU

2:nLREADY 4,8,9,11 : DGND 6:nHSYNS 10 : VDO

FAN

PWR

S/W

LIU

LINE / EXT. Phone

1:LINE1 2:LINE2 3:EXT.PHONE

MAIN B’d

SPK

1 : SPK+ 2 : SPK-

THERMISTOR

1 : THERMISTER 2 : THERMISTER

FUSER

3 : CART_DOUT 4:DGND

Circuit Diagram

Service Manual

11-3

2) Flash Memory : Record System Program, and download System Program by PC INTERFACE. FAX for Journal List, and Memory for One Touch Dial, Speed Dial List.

- Size : 4M Byte

- Access Time : 70 nsec

3) SDRAM : is used as Swath Buffer in Printing, Scan Buffer in Scanning, ECM Buffer in FAX receiving, and

System Working Memory Area

- size 32MB : 32Mbyte(Basic). TBD MB :System Working Memory Area and Scan Buffer TBD MB :FAX Memory Receive Area TBD MB :Printing System Working Memory Area

- Max Frequency : 133MHz

- store Fax Receive Memory Data by using Battery

MAIN

CONTROLLER

(CPU, DMAC)

SRAM

ANALOG

FRONT END

DATA

MEMORY

IMAGE SENSOR

CIP4

data bus address bus

control signals

data bus address bus

Service Manual

Circuit Diagram

11-4

11.2 FAX Section

11.2.1 Modem Part

11.2.1.1 BLOCK DIAGRAM

DSP SSD

System Side Dervice

CX20493 LSD Line Side Dervice

Transformer

Capacitor

Ext Line

Implemented by based on Conexant DAA (Data Access Arrangement) Solution , and is roughly composed of two kinds Chip Solution

- CX82500(SFM336) : Existing Modem Chip which adds SSD (System Side Device) for interfacing between -

- LSD and DIB of FM336Plus Core

- CX20493(LSD) : LIU (Line Interface Unit) Chip which is controlled by SSD and satisfies each PSTN requirements by modulating internal Configuration with connecting Tel Line.

Circuit Diagram

Service Manual

11-5

11.2.1.2 Modem(SFM336) specification

• 2-wire half-duplex fax modem modes with send and receive data rates up to 14,400 bps V.17, V.33, V.29, V.27 ter, and V.21 Channel 2

- Short train option in V.17 and V.27 ter

• PSTN session starting

- V.8 and V.8bis signaling

• HDLC support at all speeds

- Flag generation, 0-bit stuffing, ITU CRC-16 or CRC-32 calculation and generation

- Flag detection, 0-bit deletion, ITU CRC-16 or CRC-32 check sum error detection

- FSK flag pattern detection during high-speed receiving

• Tone modes and features

- Programmable single or dual tone generation

- DTMF receiver

- Tone detection with three programmable tone detectors

• Receive dynamic range:

- 0 dBm to –43 dBm for V.17, V.33, V.29, V.27 ter and V.21 Channel 2

• Programmable transmit level: -9 to –15 dBm

• Serial synchronous data

• Parallel synchronous data

• TTL and CMOS compatible DTE interface

- ITU-T V.24 (EIA/TIA-232-E) (data/control)

- Microprocessor bus (data/configuration/control)

Service Manual

Circuit Diagram

11-6

1) Line Interface Signal of Tel Line and LSD is Analog Signal.

2) there is A/D, D/AConverter in LSD, so Analog Signal from Tel Line is transited in Digital through A/D Converter in DAA and transfer to SSD by DIB Capacitor Digital Signal from SSD is converted to Analog by D/A Converter in DAA and transfer to Tel Line

3) Transformer transfer Clock from SSD to LSD and Clock Frequency is 4.032MHz. LSD fullwave rectifies Clock to use as inner Power supply and also use as Main Clock for DIB Protocol Sycn between LSD and SSD. Transformer transfer Clock by separatin Primary and Secondary, and amplifies Clock Level to LSD by Coil Turns Ratio 1:1.16.

11.2.1.3 Clock

- Clock is supplied by transformer from SSD to LSD, and There is PWROUT to adjust output impedance of

Clock Out Driver is inside SSD and CLKSHIGH Registor to adjust duty of HLPWR Registor and Clcok. Clock from SSD to LSD has Differential structure of 180 phase difference for Noise Robustness DIB Data transfer Data From SSD to LSD By Capacitor, and also transfer specific data from LSD to SSD. after transfering data to SSD, RSP is transfered and LSD recognize RSP and change LSD to output Driver transfer Data to SSD. DIB Data form SSD to LSD by Capacitor has Differential structure of 180 phase difference between DIBP and DIBN for Noise Robustness

Tel Line

CX20493 LSD Line Side Device

CX82500(SFM336)

SSD

System Side Device

DSP

Capacitor

Transformer

Primary Parts

Ext Line

LSD

SSD

CLKP

CLKN

DIBP

DIBN

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Samsung SCX 4920N Circuit Description

Specifications and Main Features

Frequently Asked Questions

User Manual