Samsung SCX-1100 Schematics Diagram

Repair Manual

1. Block Diagram

2. Connection Diagram

3. Circuit Description

4. Schematic Diagrams

CONTENTS

INKJET RINTER(MFP)

SCX-1100

1-1

Samsung Electronics

BLOCK DIAGRAM

Repair Manual

1. Block Diagram

SMPS

(15)

Main

Controller

(U21)

Image

Processor

OA-980

Main Clock

10MHz

RESET

CONTROLLER

FLASH ROM

ADC

16bit

(U16)

SDRAM

1M* 16bit

(U9)

CARRIER

MOTOR

LINE FEED

MOTOR

(30V, 3.3V)

(110~240V)

CCD Module

( COLOR 600DPI )

SCAN MOTOR

( Bi-POLAR STEP )

SCAN STEPPER

MOTOR DRIVER

COLOR

CARTRIDGE

MONO

CARTRIDGE

PRINT HEAD(2PEN)

60DPI DOUBLE HEIGHT

ENCORDER

SENSOR

ENCODER

USB CONN

48MHz

(AU1)

BUZZER

(U27)

SDRAM

(4M 16bit)

1284 CONN

(U1)

HEAD

Driver

/REQ /ACK

KEY PANNEL

LCD

Mcro Controller (U1)

(U5)

(U10,U14)

POWER

MAIN

OPE

SCANNER

+30V

+5V

+12V

+3.3V

PAPER EXIT

SENSOR

(U4)

Motor

Driver

& Regul at or

(U13)

(U7)

ARM7TDM

MEM CNTR

Head Control I/F

SCAN CNTR

DERASTERIZER

UART 3

IEEE 1284

TIMERS

I/O PORT

INT. CNTR

USEB

DM 2

2-1

Samsung Electronics

CONNECTION DIAGRAM

Repair Manual

2. Connection Diagr am

• Reffer to the Schematic diagram(see page 4-2)

3-1

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3. Circuit Description

3-1. GENERAL DESCRIPTION

Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-in RISC Processor Core: ARM7TDMI), system memory part, OA980 controlling input of image received from media and con version, CF(COMP ACTstorage card) interface part. The following nomenclatures by section is the same as those listed in the circuit diagram.

3-2. MEMORY MAP

The entire Addressing area provided by MAIN CONTROLLER(S3C46MOX(Jupiter3)) is 256MBytes from 0x00000000 to 0x10000000, and the Max. Address Range for each External Chip Select is 32M Byte or Half word from 0x000000 to 0x01FFFFFF and embodied with Big-Endian Bus interface. MEMORY area is divided into EXTERNAL ROM and RAM areas(See (Figure 1)), and the areas actually used are 2M/8M BYTES SDRAM and 1M BYTES ROM(FLASH MEMORY). In case of SDRAM, it uses 0xC200000h ~ 0xC3FFFFFh(2MB), and ROM uses 0x0000000h ~ 0x0FFFFFh area.

◊ MAIN PBA

3-2

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

3-3.DETAILED DESCRIPTION

3-3-1 BLOCK DIAGRAM and MAIN CONTROLLER description

3-3-1-1 GENERAL DESCRIPTION

MAIN CONTROLLER(S3C46MOX(Jupiter3),U15) consists of this system consists of CPU(ARM7TDMI RISC PROCESSOR), 8K BYTES CACHE, DATAand ADDRESS BUS, PLLderiding input frequency and CLOCK CONTROL part, SERIAL COMMUNICATION part supporting UART, PRINT HEAD control part, PARALLELPORT INTERFACE part, USB INTERFACE part, External DMApart for receiving data from external COLOR IMAGE PROCESSOR(OA980,U21), MEMORY and EXTERNAL BANK control part, SYNCHRONOUS SERIAL INTERFACE control part for interfacing Thunderbolt, and LF/CR Motor drive control and general purpose I/O control parts.(See Figure 2 )

3-3-2 S3C46MOX(Jupiter3) FUNCTION DESCRIPTION

3-3-2-1 SYSTEM CLOCK

There are two ways of Clock input method. One is the method to make Master Clock(MCLK) at the internal PLLby connecting X-tal and Capacitor to the outside, and another method is to use MCLK(When inputting 40MHz) directly, which supplies maximum 40MHz Clock to the EXTCLK terminal(PIN65). The range of frequency being input in case of using X-tal is limited to 4MHz~10MHz. This system uses SSCG(FS781) with a 10MHZ X-tal outside to make MCLK, and supplies Clock to the XIN terminal(PIN67) of ASIC by expanding Spectrum with bandwidth about 1.5% in comparison with the basic frequency by using this IC. Inside the ASIC, the PLL makes 66MHz MCLK signal, which is the basic operation frequency of the System. Also, this PLLmakes 48MHz, the operation frequency of USB Controller.

3-3-2-2 DATAAND ADDRESS BUS CONTROL

1. /RD & /WR

/RD & /WR SIGNAL are synchronized with the inside MCLK(66MHZ) and becomes active to Low. These signal are Strobe Signal used to Read or Write data when each Chip Select becomes active connected to /RD,/WR PIN of RAM, ROM, OA-980.

2. CHIP SELECT (/ROMCS, /IP_CS,/MED_CS,/SCS0,/SCS1)

- /ROMCS : FLASH MEMORY(U7) CHIP SELECT (LOW ACTIVE)

- /IP_CS : OA-980(U21) CHIP SELECT (LOW ACTIVE)

- /SCS1 : SDRAM(OPTION)(U12) CHIP SELECT(LOW ACTIVE)

In case each Chip Select is low, it may Read or Write data.

3. D0 ~ D15

- 16BIT DATA BUS

4. A0 ~ A24

- ADDRESS BUS (A23 ~ A24 RESERVED)

3-3

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

SMPS

(15)

Main

Controller

(U21)

Image

Processor

OA-980

Main Clock

10MHz

RESET

CONTROLLER

FLASH ROM

ADC

16bit

(U16)

SDRAM

1M* 16bit

(U9)

CARRIER

MOTOR

LINE FEED

MOTOR

(30V, 3.3V)

(110~240V)

CCD Module

( COLOR 600DPI )

SCAN MOTOR

( Bi-POLAR STEP )

SCAN STEPPER

MOTOR DRIVER

COLOR

CARTRIDGE

MONO

CARTRIDGE

PRINT HEAD(2PEN)

60DPI DOUBLE HEIGHT

ENCORDER

SENSOR

ENCODER

USB CONN

48MHz

(AU1)

BUZZER

(U27)

SDRAM

(4M 16bit)

1284 CONN

(U1)

HEAD

Driver

/REQ /ACK

KEY PANNEL

LCD

Mcro Controller (U1)

(U5)

(U10,U14)

POWER

MAIN

OPE

SCANNER

+30V

+5V

+12V

+3.3V

PAPER EXIT

SENSOR

(U4)

Motor

Driver

& Regul at or

(U13)

(U7)

ARM7TDM

MEM CNTR

Head Control I/F

SCAN CNTR

DERASTERIZER

UART 3

IEEE 1284

TIMERS

I/O PORT

INT. CNTR

USEB

DM 2

3-4

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

EXTCLK

nGCSx

ADDR

tRWD

tRAD

Tacs

tRCD

nWE

DATA

nBEx

Tacc

Toch

Tcah

Tocs

tRCD

tRWD

tRDD

tRAD

tRDH

’1’

EXTCLK

ADDR

nGCSx

nWE

nGCSx

nBEx

DATA

tRAD

tRCD

Tacs

tRWD

Tocs

tRWBED

Tcos

tRDD

Tacc

tRAD

tRCD

Tcah

tRWD

Toch

tRWBED

Toch

tRDD

3-5

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

’1’

tSAD

tSCSD

tSRD

Trp Trcd

tSCD

tSBED

Tcl

tSWD

tSDS

tSDH

3-6

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

SCLK

’1’

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

tSCSD

tSRD

Trp

Trcd

tSWD

tSDD

tSBED

tSCD

3-7

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc

3-8

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc

3-9

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

’HZ’

tSWD

’HZ’

’1’

tCKED

tSAD

tSCSD

tSRD tSRD

tSCD

tSCSD

tSAD

tCKED

Trc

Trp

3-10

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

Parameter Symbol Min T yp. Max Unit

ROM/SRAM Address Delay

RAD - 12 - ns

ROM/SRAM Chip select Delay

RCD - 11 - ns

ROM/SRAM Output enable Delay

ROD - 1 1 - ns

ROM/SRAM read Data Setup time

RDS - 1 - ns

ROM/SRAM read Data Hold time

RDH - 5 - ns

ROM/SRAM Byte Enable Dalay

RBED - 13 - ns

ROM/SRAM Write Byte Enable Delay

RWBED - 14 - ns

ROM/SRAM output Data Delay

RDD - 14 - ns

ROM/SRAM external Wait Setup time

WS - 1 - ns

ROM/SRAM external Wait Hold time

WH - 5 - ns

ROM/SRAM Write enable Delay

RWD - 14 - ns

DRAM Address Delay

DAD - 12 - ns

DRAM Row active Delay

DRD - 11 - ns

DRAM Read Column active Delay

DRCD - 1 1 - ns

DRAM Output enable Delay

DOD - 12 - ns

DRAM read Data Setup time

DDS - 1 - ns

DRAM read Data Hold time

DDH - 5 - ns

DRAM Write Cas active Delay

DWCD - 14 - ns

DRAM Cbr Cas active Delay

DCCD - 12 - ns

DRAM Write enable Delay

DWD - 13 - ns

DRAM output Data Delay

DDD - 14 - ns

SDRAM Address Delay

SAD - 4 - ns

SDRAM Chip Select Delay

SCSD - 4 - ns

SDRAM Row active Delay

SRD - 4 - ns

SDRAM Column active Delay

SCD - 4 - ns

SDRAM Byte Enable Delay

SBED - 5 - ns

SDRAM Write enable Delay

SWD - 5 - ns

SDRAM read Data Setup time

SDS - 4 - ns

SDRAM read Data Hold time

SDH - 0 - ns

SDRAM output Data Delay

SDD - 8 - ns

SDRAM Clock Eable Delay

CKED - 5 - ns

< ROM/SRAM Bus Timing Constants >

DDP

: 3.3V, V

DDI

: 2.5V, Ta =25˚C, PLCAP=70pf, Max/Min=typ. ±30%)

3-11

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

3-3-2-3 EXTERNAL DMA part

The function of this part is to bring data from external DEVICE(OASIS:U21) by using GENERAL DMA. If DMA REQUEST(/IP_REQ) is sent from external DEVICE to S3C46MOX(JUPITER3:U15), DMA ACKNOWLEDGE SIGNAL(/IP_ACK) is activated and the GENERAL DMAis driven, so READ STROBE(/RD) in the external DEVICE to bring data from the external DEVICE requiring CHANNEL. To transfer this DATAto the DESTINATION MEMOR Y, the ADDRESS of the DESTINATION MEMORY, CHIP SELECT and WRITE STROBE(/WR) are generated to store.

That is, if the EXTERNAL DMAis required by the external DEVICE, S3C46MOX(Jupiter3:U15) responds to drive the inside DMA CONTROLLER and then allocate GENERAL DMA to external CHANNEL so that the data may be transferred to MEMORY TO MEMORY or external DEVICE TO MEMORY.

• For more details, see the circuit description, see the circuit description part of IMAGE PROCESSOR (5.3).

3-3-2-4 DRAM control part

Since S3C46MOX(Jupiter3) has the DRAM CONTROLLER build-in, it may be used by connecting DRAM with external memory.

The Control mode of DRAM CONTROLLER provided by S3C46MOX(Jupiter3) is available for EARLY WRITE, NORMAL READ, PAGE MODE, and BYTE/HALF WORD ACCESS, and is supported even by EDO DRAM,and SDRAM as well as, Fast page DRAM.

This system uses SDRAM, and the signal used for READ/WRITE uses /RD,/WR signal used for SYSTEM BUS CONTROL. It is supported with auto REFRESH and also by the Self-refresh mode for DRAM

BACK UP. It con-

sists of 2 Banks connected to co

mmon /SCS[1:0], /SCAS, /SRAS, /SCLK, /SCKE, /DQM[1:0], each of them may use up to 2M ~ 32M HALF WORD.

In this system, 2 MB is applied as system memory. The area of DRAM is specified in the DRAM MEMORY MAP of Fig. 1, while the related TIMING DIAGRAM in Fig. 5, 6, 7, 8, 9.

3-3-2-5 RTC (REAL TIME CLOCK) part

The RTC related circuit part is not applied because the fax function is not applied, in this system.

3-3-2-6 P ARALLELPORT INTERFACE division

S3C46MOX(Jupiter3) has the Parallel Port Interface part enabling Parallel Interface with PC. This part is connected to PC through Centronics Connector in this system, which consists of /ERROR, PE, BUSY, /ACK, SLCT, /INIT, /SLCTIN, /AUTOFD, /STB and 245DIR as the part generating the main control signal used to drive PARALLEL COMMUNICATION. Data transmission method between this part and PC supports the method specified in P1284 Parallel Port Standard (http://www.fapo.com/ieee1284.html) of IEEE. That is, the Compatibility mode, the fundamental transmission method of print data, supports the Nibble Mode(4bits data) supporting the Data Uploading to PC, Byte Mode(8bits data), and ECP(Enhanced Capabilities Port : 8 bits data transmission & receiving) supporting two-way high speed transmission to PC. The Compatibility mode and ECP mode may be simply explained as follows. The Compatibility mode is generally called Centronics mode and is the protocol used for transmitting data by most of PC. The ECP mode provides two-way high speed communication as the protocol suggested for improved communication with peripheral equipments such as printer and scanner. The ECP mode provides two types of cycles in two-way transmission. They are data and command cycles. Command cycle again has Run-length count and Channel addressing types. First, RLE (Run Length Encoding) type, having 64-fold compressibility , is available for the real time data compression, and is used usefully for printer and scanner, which have to transmit large capacity of raster image having a series of same data. Next, Channel Addressing is proposed for addressing single structure of multi-device. For example, although the printer channel is processing the printer image when the fax/printer/scanner have one structure like this system, they may use parallel port for another use. This system does not apply to the parallel port Interface.

3-12

CIRCUIT DESCRIPTION

Samsung Electronics

Repair Manual

1. Write the data to the data register.

2. Program reads the status register to check that the printer is not BUSY.

3. If not BUSY, then Write to the Control Register to assert the STROBE line.

4. Write to the Control register to de-assert the STROBE line.

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD.

2. Host asserts nSTROBE low to indicate valid data.

3. Peripheral acknowledges host by setting BUSY high.

4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral.

5. Peripheral sets BUSY low to indicate that it is ready for the next BYTES.

6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low.

BYTE 0 BYTE 1

3-13

Samsung Electronics

CIRCUIT DESCRIPTION

Repair Manual

1. The host request a reverse channel transfer by setting nINIT low.

2. The peripheral signals that it is OK to proceed by setting PE low.

3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high.

4. Peripheral asserts nACK low to indicate valid data.

5. Host acknowledges by setting nAUTOFD high.

6. Peipheral sets nACK high. This is the edge that should be used to clock the data into the host.

7. Host sets nAUTOFD low to indicate that it is ready for the next BYTES.

8. The cycle repeats, but this time it is a command cycle because BUSY is low.

BYTE 0 BYTE 1

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