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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
S5K3A1EA
(1/3” SXGA CMOS Image Sensor)
Preliminary Specification
Revision 0.4
Jun, 2004
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
DOCUMENT TITLE
1/3” Optical Size 1280x1024(SXGA) 2.8V / 1.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark
0.0 Initial Draft Feb.03, 2004 Preliminary
0.1 DC Characteristics Changed. Mar.29.2004
0.2 Register Map Updated. Apr.09.2004
0.3 Imaging Characteristics Changed Jun.10.2004
0.4 Imaging Characteristics Changed Jun.11.2004
S5K3A1EA13 Product Added
AC Characteristics Changed
Ob_area Recommended Setting Changed
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
INTRODUCTION
The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG
0.18um CMOS image sensor process technology. It is developed for image application to realize high
efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The
sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed
Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to
the external devices, a camera system can be configured easily.
FEATURES
— Process Technology: 0.18µm Dual Gate Oxide SPQM CMOS
— Optical Size: 1/3 inch
— Unit Pixel: 3.8 µm X 3.8 µm
— Effective Resolution: 1280X1024, SXGA
— Line Progressive Read Out.
— 10-bit Raw Image Data Output
— Windowing and Panning
— Sub-Sampling (2X, 4X, 8X)
— Timing Generator for Frame Memoryless Scaler
— Timing Generator for Stepless Zooming
— Continuous and Single Frame Capture Mode
— Programmable Exposure Time and Gain Control
— Auto Dark Level Compensation
— Standby Mode for Power Saving
— Maximum 15 Frames per Second for Full Frame Readout with 24 MHz Output Data Rate
— Bad Pixel Replacement
— Dual Power Supply Voltage: 2.8V/1.8V (2.8V for analog, 1.8V for digital)
— Package Type: 48-CLCC/PLCC
PRODUCTS
Product Code Power Supply Backend Process Description
S5K3A1EA01 2.8V / 1.8 V None Monochrome image sensor
S5K3A1EA02 2.8V / 1.8 V On-chip micro lens
S5K3A1EA03 2.8V / 1.8 V
S5K3A1EA13 2.8V / 1.8 V
High sensitivity monochrome
Image sensor
On-chip color filter
and micro lens
On-chip color filter
and micro lens
3
RGB color image sensor
RGB color image sensor
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
BLOCK DIAGRAM
MCLK
RSTN
STBYN
STRB
VSYNC
HSYNC
DCLK
SCL
SDA
VSSIO
VDDIO
Main Clock
Generator
I2C Interface
VDDD
Divider
Timing
Control
Registers
VSSD
Row
Driver
10-bit Column ADC
Odd Column CDS
Active Pixel
Sensor Array
Even Column CDS
10-bit Column ADC
VSSA
VDDA
Post
Processing
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
PIXEL ARRAY MAP
(TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
10 4
Default Window of Interest
1280X1024
R B G G R B G G RBG
G
R B G
G
R B G
G
GR B G G
RBG
G
R B G G RBG
10
4
Active Pixels
G
RBGGRBGGRBG
GRBGGRBGG
RBG
G
RBGGRBGGRBG
Optical
Black Pixels
10
4
(0,0)
(14,14) read out start
point
4
10
5
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
VSSIO
VSSD
VDDA
VSSA
VSSA
VDDA
VDDA
VSSA
VSSA
VDDA
VDDD
VSSD
VDDIO
VDDD
VDDA
VSSA
VSSA
VDDA
VDDA
VSSA
VSSA
VDDA
VDDD
VSSD
PIN CONFIGURATION
6
5
4
3
MCLK
2
7
48
47
46
45
44
1
43
42
SDA
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DCLK
8
9
10
11
12
13
14
15
16
17
18
19
20
First Readout Pixel
21
22
23
24
25
26
27
28
29
41
40
39
38
37
36
35
34
33
32
31
30
SCL
RSTN
STBYN
STRB
VDDA
VSSA
VREF
TEST2
TEST1
HSYNC
VSYNC
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
MAXIMUM ABSOLUTE RATINGS
Characteristic Symbol Value Unit
Analog maximum absolute voltage
(VDDA supply relative to VSSA )
V
DDH
-0.3 to 3.8
Digital and I/O maximum absolute voltage
V
(VDDIO supply relative to VSSIO
DDL
-0.3 to 2.7
VDDD supply relative to VSSD)
T
T
V
IN
OPR
STG
Input voltage
Operating temperature
Storage temperature
NOTES:
1. The maximum allowed storage temperature for S5K3A1EA01.
2. The maximum allowed storage temperature for S5K3A1EA02 and S5K3A1EA03.
-0.3 to 2.7
-20 to +60
(1)
(2)
-40 to +125
-40 to +85
V
°C
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
DC Characteristics
= -20 to +60°C, CL = 15pF)
(T
A
Characteristics Symbol Condition Min Typ Max Unit
Operating voltage
Input voltage
(1)
Input leakage
(2)
current
Input leakage current
(3)
with pull-down
High level output
(4)
voltage
Low level output
(5)
voltage
High-Z output leakage
(6)
current
Input capacitance
(1)
Supply current
V
DDH
V
DDL
V
V
I
IL
I
ILD
VOH
VOL
I
OZ
C
I
STBL
I
STBH
I
DDL
I
DDH
IH
IL
IN
applied to VDDA pins 2.6 2.8 3.0 V
applied to VDDIO and VDDD pin 1.65 1.8 1.95
VIN = V
VIN = V
I
= -1µA
OH
DDL
DDL
- 1.27 - -
- - - 0.57
-10 - 10
5 18 40
-
V
DDL
- - V
0.05
I
= -4mA
OH
I
= 1µA
OL
= 4mA
I
OL
V
= VSS or V
OUT
STBYN=Low(Active)
DDL
- - - 4 pF
1.2 - -
- - 0.05
- - 0.45
-10 - 10
- - 10
All input clocks = Low
0 lux illumination
applied to VDDIO and VDDD pin
STBYN=Low(Active)
- - 10
All input clocks = Low
0 lux illumination
applied to VDDA pin
f
MCLK
= 12MHz
- 10 15 mA
0 lux illumination
applied to VDDIO and VDDD pin
f
MCLK
= 12MHz
- 20 25 mA
0 lux illumination
applied to VDDA pin
µA
µA
µA
µA
NOTES:
1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pins.
2. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA pins
3. Applied to TEST1, TEST2 pin
4. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin. I
5. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin. I
6. Applied to SDA pin when in High-Z output state
8
: High level output current
OH
: Low level output current
OL
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
9
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical
operating conditions follow the recommended typical values. The control registers are set to the default values.
T
= 25°C if not specified.)
A
Characteristic Symbol Condition Min Typ Max Unit
(2)
(3)
(1)
Saturation level
Sensitivity
Dark level
Dynamic range
Signal to noise ratio
Dark signal non-uniformity
(4)
(5)
(6)
Photo response non-
(7)
uniformity
Vertical fixed pattern noise
(8)
Horizontal fixed pattern noise
NOTES:
1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole
pixel area to eliminate the values from defective pixels.
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values
are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC.
5. 20 log (average output level / RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure
time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median
filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from
defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 rows at 25% of saturation level illumination for exposure time 1/30 sec.
V
SAT
- 600 650 - mV
S - - 1500 - mV/lux sec
V
DARK
T
= 40°C
A
T
= 60°C
A
- 4 8 mV/sec
- 20 40
DR - - 60 - dB
S/N - - 40 -
DSNU
T
= 60°C
A
- - 40 mV/sec
PRNU - - 4 8 %
VFPN - 4 8 %
(9)
HFPN - 4 8 %
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
AC Characteristics
= 2.8V ± 0.25V, V
(V
DDH
DDL
Characteristic Symbol Condition Min Typ Max Unit
Main input clock frequency
Data output clock frequency
Propagation delay time
from main input clock
Propagation delay time
from data output clock
Reset input pulse width
Standby input pulse width
NOTES:
1. T
is the period of the master input clock, MCLK.
MCLK
= 1.8V ± 0.15V, TA = -20 to + 60 °C, C
f
MCLK
f
DCLK
t
PDMV
t
PDMH
t
PDMD
t
PDMO
t
PDDV
t
PDDH
t
PDDO
t
WRST
t
WSTB
Duty = 50% 6 12 48 MHz
- 6 12 30
VSYNC output - - 10 ns
HSYNC output - - 10
DCLK output - - 6
DATA output - - 10
VSYNC output - - 4
HSYNC output - - 4
DATA output - - 4
RSTN=low(active) 5 - -
STBYN=low(active) 4 - -
= 10pF)
L
T
MCLK
(1)
MCLK
DCLK
DATA
HSYNC
VSYNC
0.5VDD
t
PDMD
t
PDMO
t
t
PDDO
t
PDDH
t
PDMH
t
PDDV
t
PDMV
PDMD
t
PDDH
t
PDMH
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
MCLK
RSTN
t
WRST
t
WSTB
STBYN
system
reset
partial
power down
2
I
C Serial Interface Characteristics
(1)
Characteristic Symbol Condition Min Typ Max Unit
Clock frequency
Clock high pulse width
Clock low pulse width
Clock rise/fall time
Data set-up time
Data hold time
START condition setup time
START condition hold time
STOP condition setup time
STOP to new START gap
Capacitance for each pin
Capacitive bus load
Pull-up resistor
NOTES:
1. I2C is a proprietary Phillips interface bus.
2. T
is the period of the master input clock, MCLK.
MCLK
SCL
0.9VDD
0.1VDD
tWL
f
SCL
t
WH
t
WL
t
R/tF
t
DS
t
DH
t
STRS
t
STRH
t
STPS
t
GSS
C
PIN
C
BUS
SCL, SDA to V
R
PU
complete
power down
- - - 400 kHz
SCL 0.6 - -
µs
SCL 1.3 - -
SCL, SDA - - 0.3
SDA to SCL 0.1 - -
SCL to SDA - - 0.9
- 4
- 4
- 4 - -
- 8 - -
SCL, SDA - - 4 pF
SCL, SDA - - 200
1.5 - 10
t
F
tR
t
WH
DD
T
MCLK
(2)
kΩ
t
t
t
STRS
SDA
12
0.9VDD
STRH
0.1VDD
tDH
DS
t
STPS
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
PIN DESCRIPTION
Pin No I/O Name Function
VDDD (6,25,48) Power Digital power supply
VDDIO (5) Power
For logical circuit (V
For I/O circuit (V
DDL
DDL
)
)
VSSD (19,26,47) Power 0V (GND)
VSSIO (20) Power 0V (GND)
VDDA(1,4,21,24,
Power Analog power supply
For analog circuit (V
DDH
)
28,29,37,44,45)
VSSA(2,3,22,23,
Power 0V (GND)
27,30,36,43,46)
MCLK (7) I Master clock Master clock pulse input for all timing generators.
RSTN (40) I Reset Initializing all the device registers. (Active low)
STBYN (39) I Standby Activating power saving mode.
( high=normal operation, low=power saving mode )
STRB (38) I Strobe Triggering the integration start and stop when single
frame capture mode.
DATA0~DATA9
(8 ~ 17)
O Image data output 10-bit image data outputs. When ADC resolution is
reduced, the unused lower bits are set to 0.
DCLK (18) O Data clock Image data output synchronizing pulse output.
HSYNC (32) O Horizontal sync clock Horizontal synchronizing pulse or data valid signal
output.
VSYNC (31) O Vertical sync clock Vertical synchronizing pulse or line valid signal output.
SCL (41) I Serial interface clock I2C serial interface clock input
SDA (42) I/O Serial interface data I2C serial interface data bus
(external pull-up resistor required)
VREF (35) I/O Reference voltage For proper operation, the external capacitor larger than
0.1uF must be connected between VREF and VDDA.
TEST1 (33) I Test input 1 Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
TEST2 (34) I Test input 2 Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
CONTROL REGISTERS
Address
(Hex)
00h 01h
Reset
Value
Bits Mnemonic Description
[7]
[6]
[5]
[4:2]
[1]
[0]
01h 00h
[7]
[6]
[5]
[4]
[3:2]
[1:0]
02h 00h [2:0]
03h 0Eh [7:0]
04h 00h [2:0]
05h 0Eh [7:0]
06h 04h [2:0]
07h 00h [7:0]
08h 05h [2:0]
09h 00h [7:0]
0Ah 80h [7:0]
p2_r_con
bprm
ccsm
mcdiv
shutc
adcres
shut_err_cor
Not_use
mircv
mirch
subsr
subsc
wrp_high
wrp_low
wcp_high
wcp_low
wrd_high
wrd_low
wcw_high
wcw_low
offsdef
(Factory use only) CDS timing control
Bad pixel replacement mode
0b: disabled (default), 1b: enabled
Color channel separation mode
0b: not separated (default), 1b: separated
Main clock divider
000b: DCLK=MCLK(default), 001b: DCLK=MCLK÷2
010b: DCLK=MCLK÷4, 011b: DCLK=MCLK÷8
100b: DCLK=MCLK÷16, 101b: DCLK=MCLK÷32
111b: forbidden value
Electronic shutter mode
0b: disabled (default), 1b: enabled
ADC resolution
0b: 8-bit, 1b: 10-bit (default)
Shutter error correction register
Vertical mirror control
0b: normal (default), 1b: mirrored
Horizontal mirror control
0b: normal (default), 1b: mirrored
Row sub-sampling mode
00b: disabled (default),
01b: 2X, 10b: 4X, 11b: 8X
Column sub-sampling mode
00b: disabled (default),
01b: 2X, 10b: 4X, 11b: 8X
Row start point for window of interest
wrp[10:0] = 14d(default)
Column start point for window of interest
wcp[10:0] = 14d(default)
Row depth for window of interest
wrd[10:0] = 1024d(default)
Column width for window of interest
wcw[10:0] = 1280d(default)
(Factory use only) Analog offset reference
offsdef[7:0] = 128d (default)
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
Address
(Hex)
Reset
Value
Bits Mnemonic Description
0Bh 04h [7:0]
0Ch 65h [7:0]
0Dh 04h [7:0]
0Eh 65h [7:0]
0Fh 00h [7:0]
10h 00h [7:0]
11h 00h
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
12h 01h [7:0]
sint_high
sint_low
cintr_high
cintr_low
cintc_high
cintc_low
hspolar
hsdisp
vspolar
vsdisp
global_mod
roll_mod
mech_mod
sfcen
vswd
Integration time in single frame capture mode
sint[15:0] = 1125d (default)
Row-step integration time in continuous frame
capture mode
cintr[15:0] = 1125d (default)
Column-step integration time in continuous frame
capture mode
cintc[15:0] = 0d (default)
HSYNC polarity
0: active high (default), 1: active low
HSYNC display mode
0: sync mode (default), 1: data valid mode
VSYNC polarity
0: active high (default), 1: active low
VSYNC display mode
0: sync mode (default), 1: data valid mode
Single frame capture integration mode
Field shift shutter mode
Single frame capture integration mode
Rolling shutter mode
Single frame capture integration mode
simultaneous frame integration with mechanical
shutter
Single frame capture mode enable
0b: disabled (default), 1b: enabled
VSYNC width
vswd[7:0] = 1d (default)
13h 00h [7:0]
14h 00h [7:0]
15h 00h [7:0]
16h 65h [7:0]
17h 20h [7:0]
18h 00h [7:0]
19h 00h [7:0]
1Ah 00h [7:0]
1Bh 8Eh [7:0]
15
vsstrt_high
vsstrt_low
vblank_high
vblank_low
hswd
hsstrt_high
hsstrt_high
hblank_high
hblank_low
VSYNC start position
vsstrt[9:0] = 0d (default)
Vertical blank depth
vblank[12:0] = 101d (default)
HSYNC width
hswd[7:0] = 32d (default)
HSYNC start position
hsstrt[9:0] = 0d (default)
Horizontal blank depth
hblank[15:0] = 142d (default)
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
Address
(Hex)
Reset
Value
Bits Mnemonic Description
1Ch 00h [6:0]
1Dh 00h [6:0]
1Eh 00h [6:0]
1Fh 00h [6:0]
20h 0Fh [4:0]
21h 0Fh [4:0]
22h 0Fh [4:0]
23h 0Fh [4:0]
pgcr
pgcg1
pgcg2
pgcb
sgg1
sgg2
sgg3
sgg4
Red channel gain
pgcr[6:0] = 0d (default)
Green(Red row) channel gain
or all channel gain (ccsm=0)
pgcg1[6:0] = 0d (default)
Green(Blue row) channel gain
pgcg2[6:0] = 0d (default)
Blue channel gain
pgcb[6:0] = 0d (default)
1st quadrisectional global gain
sgg1[4:0] = 0F(default)
2nd quadrisectional global gain
sgg2[4:0] = 0F(default)
3rd quadrisectional global gain
sgg3[4:0] = 0F(default)
4th quadrisectional global gain
sgg4[4:0] = 0F(default)
24h 80h [7:0]
25h 80h [7:0]
26h 80h [7:0]
27h 80h [7:0]
[7]
[6:0]
29h 00h [7:0]
offsr
offsg1
offsg2
offsb
clipen
pthresh
adcoffs
Red channel analog offset
Offsr[7:0] = 128 (default)
Green(Red row) channel analog offset or
all channel offset (ccsm=0) offsg1[7:0] = 128
(default)
Green(Blue row) channel analog offset
offsg2[7:0] = 128 (default)
Blue channel analog offset
offsb[7:0] = 128 (default)
(Factory use only) Reset clipping enable 28h 14h
Bad pixel threshold
pthresh[6:0] = 20d (default)
ADC offset (count delay register)
adcoffs[7:0] = 0d (default)
ADLC formula : D
= D(n) + adcoffs
final
When adcoffs[7] is 1 , adc offset is +adcoffs[6:0],
else adc offset is - adcoffs[6:0]
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
Address
(Hex)
Reset
Value
Bits Mnemonic Description
[7:5]
[4:0]
2Bh 00h [7:0]
2Ch 00h [7:0]
2Dh 02h
[7:6]
[5]
[4]
[3:2]
[1]
[0]
2Eh 06h
[7]
[6]
[5]
[4]
[3:2]
[1:0]
stbystrt
stbystp
rxstrt
blank
Not_use
id_inv
sck_inv
Not_use
i2ctest
nandtree
adlc_mod_d
adlc_mod_c
adlc_mod_b
adlc_mod_a
feedback_gain_B
feedback_gain_A
(Factory use only) Stand-by start 2Ah 40h
(Factory use only) Stand-by stop
(Factory use only) Reset start control
Blank register for general purpose
(Factory use only) Line color inversion
(Factory use only) Column color inversion
(Factory use only) IIC test mode
(Factory use only) NAND tree test mode
Adlc mode always enable when this register is high.
0b: disabled (default), 1b: enabled
Adlc mode works when gain values are changed
0b: disabled (default), 1b: enabled
Adlc mode works when shutter values are changed
0b: disabled (default), 1b: enabled
Adlc mode works till adlc length value
0b: disabled (default), 1b: enabled
Feedback gain value about ADLC
00b : 0, 01b : 0.5(default),
10b : 0.75, 11b : 1
ADLC formula : D
= D(n) + adcoffs
final
D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1)
Feedback gain value about ADLC
00b : 0, 01b : 0.5,
10b : 0.25(default), 11b : 0.125
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
Address
(Hex)
Reset
Value
2Fh 00h
30h 02h
Bits Mnemonic Description
[7]
dckout_en
DCK pad control
0b : output enable (default), 1b : stable value
[6]
[5]
dfo
fixvs
I/O driver fan-out control register.
VSYNC always high at frame start point.
0b: disabled (default), 1b: enabled
[4]
[3]
isp_sel
ob_sel
(Factory use only)
ADLC formula : D = D(n) + adcoff
D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1)
0b : OB(n-1) = OB(n-1) (default)
1b : OB(n-1) = OB(n)
[2]
ob_area
OB area selection
0b:128*8 (default), 1b:512*2 (recommended)
[1:0]
adlc_length
ADLC function works only during this value when
adlc_mod_a enabled,
00b : 1 frame, 01b : 2 frames,
10b : 3 frames, 11b : 4 frames
[7:6]
[5]
Not_use
pwr_save2
(Factory use only)
rx & tx signals are enable only active area.
0b: disabled (default), 1b: enabled
[4]
pwr_save1
(Factory use only)
0b: disabled (default), 1b: enabled
[3]
[2]
[1]
[0]
31h 1Eh [7:0]
32h 32h [7:0]
33h 00h [5:0]
34h
35h
00h [7:0]
CCh
[7:4]
[3:0]
36h
CCh
[7:4]
[3:0]
ggo_en
rsm_en
gbmod
stpless_mod
gb_start
gb_end
vs_postc_high
vs_postc_low
p12_stp
p11_stp
p2r_stp
p2_stp
(Factory use only)
0b: disabled (default), 1b: enabled
(Factory use only)When this register is zero, H-sync
keeps same period in one frame.
Guardband mode
0b: disabled, 1b: enabled(default)
Stepless mode enable
0b: disabled (default), 1b: enabled
Guardband start position
Guardband end position
Keep the same frame in zoom mode.
This register compensates remainder of frame.
(Factory use only) CDS timing control
(Factory use only) CDS timing control
(Factory use only) CDS timing control
(Factory use only) CDS timing control
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
Address
(Hex)
Reset
Value
Bits Mnemonic Description
37h 00h [7:0]
38h 00h [7:0]
39h 0Ah [7:0]
3Ah 1Ah
[7]
[6]
[5]
[4]
[3:0]
holdline_high
holdline_low
vsend_ofset-high
Not use
tx_add
shutx_sel
cal_en
cal_stp
Active output delay about its register value
This register value is must larger than OB line.
(Factory use only)Add tg to reduce NIT.
(Factory use only)Enlarge shutter TX width to reduce
NIT.
(Factory use only) calibration enable
(Factory use only) calibration signal control
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
OPERATION DESCRIPTION
1. Output Data Format
1-1. Main Clock Divider
All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing
the input main clock (MCLK). The dividing ratio is 1, 2, 4, 8, 16, and 32 according to main clock dividing control
register (mcdiv). For 10-bit ADC and SXGA resolution, dividing ratio of 1 is required. If dividing ratio of 1 is used,
the duty must be within 40% to 60%.
1-2. Synchronous Signal Output
The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width,
polarity and position are programmable by control registers (ref. timing chart). When display mode is enabled, the
sync signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1).
1-3. Window of Interest Control
Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned
anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row
depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of
color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and
green column of Bayer pattern. Figure 1 refers to a pictorial representation of the WOI on the displayed pixel
image.
0 1307
0
(wcp,wrp)
wrd
Window Of Interest
wcw
1051
Figure 1. WOI definition.
1-4. Vertical Mirror and Horizontal Mirror Mode Control
The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction
normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be
flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to
top in vertical mirror mode. The horizontal and the vertical mirror mode can be programmed by Horizontal Mirror
Control Register (mirch) and Vertical Mirror Control Register (mircv).
1-5. Sub-sampling Control
The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling
can be done in four rates : full, 1/2, 1/4 and 1/8. The user controls the sub-sampling using the Sub-sampling
20
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space. In Figure 2, the
Bayer space sub-sampling examples are shown.
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
subsr=01b, subsc=01b
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
subsr=00b, subsc=10b
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
R G
G B
Figure 2. Bayer Space Sub-Sampling Examples
1-6. Line Rate and Frame Rate Control (Virtual Frame)
The line rate and the frame rate can be changed by varying the size of virtual frame. The virtual frame’s width
and depth are controlled by effective WOI and blank depths. The effective WOI is scaled by the subsampling
factors from WOI set by register values. For CDS and ADC function, the virtual column width must be larger than
(adcres+1)*256/(2^mcdiv)+264, where adcres is the ADC resolution control register value. The horizontal and
vertical blanking time (hblank, vblank) should be over 60 and 4, respectively. The detailed restriction of h-blank
period is shown in table 1.
Table 1. Restriction of h-blank period (minimum 1H-period(dck)
minimum 1H-period(dck)
mcdiv[2:0] adcres = 1 adcres = 0
0 1412 548
1 836 404
2 548 332
3 404 300
4 332 278
5 300 270
Setting procedure of hblank, vblank and vs_postc is as follows.
Frame cycle = ((wcw>>subsc) + hblank) x ((wrd>>subsr) + vblank) + vs_postc
vblank >= 4 (isp_sel=1)
vs_postc < 1H ( (wcw>>subsc) + hblank) )
1-7. Continuous Frame Capture Mode(CFCM) Integration Time Control (Electronic Shutter Control)
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when
shutter control register (shutc) is set to “1”. In shutter operation, the integration time is determined by the Row
Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc)
In CFCM integration time control. There are two different modes. One is normal shutter mode. The other is
shutter TX wide mode to reduce nonlinear integration time. The effective integration time(EIT) formulas of each
mode are as follows.
1) normal mode (00h[2] = 1, 01h[7] = 1, 3Ah[5] = 1)
EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck)
restriction of cintr?
1 <= cintr <= (wrd>>subsr) + vblankr –1
restriction of cintc?
0 <= cintc <= (wcw>>subsc) + hblank - 7
2) shutter TX wide mode (00h[2] = 1, 01h[7] = 0, 3Ah[5] = 1)
EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck)
restriction of cintr?
1 <= cintr <= (wrd>>subsr) + vblankr - 1
restriction of cintr?
case of (1 <= cintr <= (wrd>>subsr) + vblankr - 2)
0 <= cintc <= (wcw>>subsc) + hblank - 7
case of (cintr = (wrd>>subsr) + vblankr - 1)
0 <= cintc <= (wcw>>subsc) + hblank - 195
1-8. Single Frame Capture Mode(SFCM) Integration Time Control
To capture a still image, SFCM can be set by Single Frame Capture Enable Register(sfcen). There are two
types of integration mode implemented. In the rolling shutter mode (sfcim=0), the integration time is controlled by
SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows.
The integration time is expressed as :
Integration Time = sint * (1 line time)
In the mechanical shutter mode (sfcim=1), the integration time for all rows is the period during the external input
signal, STRB is active. After STRB goes to be inactive, the external mechanical shutter should shut off incident
lignt on image sensor and the data readout sequence starts.
2. Analog to Digital Converter ( ADC)
The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color
channel gain and offset control.
2-1. ADC resolution
The default value of ADC resolution is 10bit and can be changed to 8bit or 9bit by control the ADC Resolution
Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of
effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have values of “0”.
2-2. Correlated Double Sampling ( CDS )
The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
and some fixed pattern noise by the in-pixel amplifier offset deviation. To eliminate those noise components, a
correlated double sampling(CDS) circuit is used before converting to digital. The output signal of each pixel is
sampled twice, once for the reset level and once for the actual signal level.
2-3. Programmable Gain and Offset Control
The user can controls the gain of individual color channel by the Programmable Gain
Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset by Offset Control Registers
(offsr, offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled
(ccsm=0), pgcg1 and offsg1 change the gains and offsets for all channels. As increasing
the gain control register, the ADC conversion input range decreases and the gain
increases as following equation and the relative channel gain is shown in figure 3
Channel Gain = 128 / (128 – Programmable Gain Control Register Value[6:0])
10
9
8
7
6
5
4
Relative Channel Gain
3
2
1
0 16 32 48 64 80 96 112 128
Programm able Gain Control
45
40
35
30
25
20
15
Channel Gain (dB)
10
5
0
0 163248648096112128
Program m able Gain Contr ol
R G1
G2 B
R G1
G2 B
R G1
G2 B
R G1
G2 B
Figure 3. Relative Channel Gain
2-4. Quadrisectional Global Gain Control
The user can controls the global gain to change the gain for all color channels by the Global Gain Control
Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and
each register value decides the gain for each quarter section of output code level. At MCLK=12MHz and
ggo_en=L, the global gain is determined by the following formula.
Global Gain = (sgg[4:0]+1) / 16
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
2.2
2
1.8
1.6
1.4
1.2
1
Relative Global Gain
0.8
0.6
0.4
0.2
0
0 4 8 121620242832
Programmable Gain Control
10
5
0
-5
-10
Global Gain (dB)
-15
-20
-25
0 4 8 121620242832
Programmable Gain Control
Figure 4. Relative Global Gain
The ADC gain is dependent on MCLK frequency (not on DCLK frequency) and ADC resolution. The default
global gain is set for typical MCLK frequency (12MHz) and 10-bit ADC. When the frequency and ADC resolution
is changed, the global gain should be changed to maintain the resulting gain over unity for assuring appropriate
ADC conversion range. The recommended minimum global gain setting depending on ggo_en and adcres is
shown in figure 5 and table 2.
30
28
26
24
22
20
18
16
14
12
10
Minimum Global Gain
10-bit ADC resolution
8
6
8-bit ADC resolution
4
2
0
024681012141618202224262830323436384042444648
MCLK Frequency (MHz)
Figure 5. Recommended Minimum Global Gain Control Value (ggo_en = L)
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
Table 2. Recommended Minimum Global Gain Setting (adcres = H)
MCLK
[MHz]
ggo_en = L ggo_en=H
Decimal Hexadecimal Decimal Hexadecimal
6 31 1F - -
7 27 1B - -
8 23 17 - -
9 21 15 - -
10 19 13 - -
11 17 11 - -
12 15 0F 31 1F
13 14 0E 29 1D
14 13 0D 27 1B
15 12 0C 25 19
16 11 0B 23 17
17 11 0B 22 16
18 10 0A 21 15
19 10 0A 20 14
20 9 09 19 13
21 9 09 18 12
22 8 08 17 11
23 8 08 16 10
24 7 07 15 0F
25 7 07 15 0F
26 7 07 14 0E
27 7 07 14 0E
28 6 06 13 0D
29 6 06 13 0D
30 6 06 13 0C
30 6 06 13 0D
31 6 06 12 0C
32 5 05 11 0B
33 5 05 11 0B
34 5 05 11 0B
35 5 05 10 0A
36 5 05 10 0A
37 5 05 10 0A
38 5 05 10 0A
39 4 04 9 09
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
40 4 04 9 09
41 4 04 9 09
42 4 04 9 09
43 4 04 8 08
44 4 04 8 08
45 4 04 8 08
46 4 04 8 08
47 4 04 8 08
48 3 03 7 07
By appropriately programming these four register values, the different output resolution according to the
signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application,
the sectional global gain control can be used as a rough gamma correction with four sectional linear
approximation curve as shown in Figure 6.
sgg1 sgg2 sgg3 sgg4
ADC input signal
255 0
ADC output code at 10-bit resolution
511 767 1023
Figure 6. Quadrisectional Glabal Gain Control
sgg1=11111b
sgg2=01111b
sgg3=00111b
sgg4=00011b
sgg1=01111b
sgg2=01111b
sgg3=01111b
sgg4=01111b
26
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
3. Post Processing
3-1. Dark Level Compensation
The dark level of Image sensor is defined as average output level without illumination. It includes pixel ouput
caused by leakage current of the photodiodes and ADC offset. To compensate the dark level, the output level of
optical black(OB) pixels can be a good reference value. When Auto Dark Level Compensation Register (dlcm) is
set, the image sensor detects the OB pixel level at the start of every frame and anglog-to-digital conversion range
is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost
zero under dark state. If user wants the dark level which is not zero, the ADC Offset Register (adcoffs) can be
used. The lower 7-bit value represent the offset value in outout code for compensation and the MSB is the sign to
define whether the offset is positive (adcoffs[7]=0) or negative (adcoffs[7]=1). When not in auto dark level
compensation mode, the adcoffs[7:0] act as a output code value to subtract the output image data. Please notify
that the all the 8-bit data are used for an offset value without sign bit.
ADLC formula : D
= D(n) + adcoffs
final
D(n) = (feed_gain_a)*(OB(n) + OB(n-1)) + (feed_gain_b)*D(n-1)
3-2. Bad Pixel Replacement
When the Bad Pixel Replacement Register (bprm) is enabled, the image sensor check that the image data is
less or greater than horizontally neighboring pixels in same color channel by the preset threshold value (pthresh).
If satisfied, the output of the pixel is replaced by the averaged value of the neighboring two pixels. The detectable
defected pixels are rare and the bad pixel replacement action can remove defected image effectively. But it
reduces the line resolution in horizontal direction.
2
4. I
C Serial Interface
2
The I
C is an industry standard serial interface. The I2C contains a serial two-wire half duplex interface that
features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and
clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The
image sensor operates in salve mode only and the SCL is input only. The I
2
C bus interface is composed of
following parts : START signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit,
an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP
signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the
high-to-low transition of SCL.
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
X
SCL
SCL
SDA
SDA
SCL
SDA
Start
“0” “0” “1” “0” “0” “0” “1”
Start
I2C Bus Address
D7 D6 DDDDDD
Data to Write Stop Ack
Figure 7. I2C Bus Write Cycle
“0” “0” “1” “0” “0” “0” “1”
I2C Bus Address
Write Ack
D7 D6 D
D7 D6 D
D D D D D
I2C Register Address
D D D D D
I2C Register Address Write Ack Ack
Ack
SCL
SDA
Re-Start
“0” “0” “1” “0” “0” “0” “1”
I2C Bus Address
Figure 8. I
D7 D6 D
Read Ack Ack
2
C Bus Read Cycle
D D D D D
Data to be Read
Stop
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
TIMING CHART
VERTICAL TIMING DIAGRAM
Continuous Frame Capture Mode
( Default Case )
VSYNC
HSYNC
10 rows = vsend_ofset
DATA
( Delayed Vertical Sync Case)
VSYNC
HSYNC
10 rows = vsend_ofset
DATA
1 frame = wrd + vblank ( 1125 rows )
vswd (1row)
wrp(14th row)
wrd (1024 rows)
1 frame = wrd + vblank ( 1125 rows )
vsstrt vswd
wrp(14th row)
vblank (101 rows)
( Vertical Data Valid Mode Case) vsdisp=1
VSYNC
10 rows = vsend_ofset
HSYNC
(hsdisp=0)
HSYNC
(hsdisp=1)
DATA
29
2rows
2rows
wrp(14th row)
wrd (1024 rows) vblank (101 rows)
Page 30
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
VERTICAL TIMING DIAGRAM (continued)
( Short OB Line & Fixed Vertical Sync mode) isp_sel = 1& fix_vs = 1
VSYNC
HSYNC
vswd (1row)
4 rows = vsend_ofset
1 frame = wrd + vblank ( 1125 rows )
Normal frame output
DATA
wrp(14th row)
wrd (1024 rows) vblank (101 rows)
( Short OB Line & Normal Sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d
DEFAULT
VSYNC
VSYNC
HSYNC
vswd (2rows)
4 rows = vsend_ofset
1 frame = wrd + vblank ( 1125 rows )
Normal frame output
vsstrt (1117 rows)
wrp(14th row)
DATA
wrp(14th row)
wrd (1024 rows)
vblank (101 rows)
wrp(14th row)
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
VERTICAL TIMING DIAGRAM (continued)
Single Frame Capture Mode
( Rolling Shutter Case, sfcen = 1 & roll_mod = 1 )
Normal frame output
STRB
Integration time for 1st readout row
Integration time for 2nd readout row
Integration time for 3rd readout row
VSYNC
HSYNC
DATA
sint X (1 row time) = integration time
( Mechanical Shutter Case, sfcen=1 & mech_mod = 1 )
STRB
VSYNC
Integration time for all pixels
HSYNC
Integration time for 4th readout row
wrp(14th row)
wrd (1024 rows)
Normal frame output
DATA
External
Mechanical
Shutter
wrp(14th row)
wrd (1024 rows)
Can be opened
31
Should be closed
Page 32
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
( Global Shutter Case, sfcen=1 & global_mod = 1 )
STRB
VSYNC
HSYNC
DATA
Normal frame output
Integration time for all pixels
wrp(14th row)
wrd (1024 rows)
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
HORIZONTAL TIMING DIAGRAM
( Default Case )
VSYNC
HSYNC
hswd
10 DCLK
DCLK
DATA
( 14th column)
( Delayed Horizontal Sync Case )
VSYNC
HSYNC
DCLK
hsstrt
1 row = wcw + hblank ( 1422 columns )
wcp
wcw ( 1280 columns )
1 row = wcw + hblank
hswd
hblank ( 142 columns )
DATA
( Horizontal Data Valid Mode Case ) hsdisp=1
VSYNC
HSYNC
DCLK
DATA
wcw
wcw
hblank
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
PACKAGE DIMENSION
48pin CLCC
(unit = mm)
7
14.22SQ +0.30/-0.13
6 43481
42
TOP VIEW
Center of Image Area
(X=+0.088 ± 0.15, Y=0.002± 0.15
from package center)
Max. Chip Rotation = ±1.5 degree
Max. Chip Tilt = 0.05mm
18
19 30
Glass
SIDE VIEW
31
0.55 ± 0.05
1.65 ± 0.18
11.176 ± 0.13
1.016 ± 0.08
48 1
BOTTOM VIEW
R 0.15
4 Corners
0.51 ± 0.08
1.016 ± 0.18
34
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