SAMSUNG S5K3A1EA User Manual

1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
S5K3A1EA
(1/3” SXGA CMOS Image Sensor)
Preliminary Specification
Revision 0.4
Jun, 2004
1
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
DOCUMENT TITLE
1/3” Optical Size 1280x1024(SXGA) 2.8V / 1.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark
0.0 Initial Draft Feb.03, 2004 Preliminary
0.1 DC Characteristics Changed. Mar.29.2004
0.2 Register Map Updated. Apr.09.2004
0.3 Imaging Characteristics Changed Jun.10.2004
0.4 Imaging Characteristics Changed Jun.11.2004
S5K3A1EA13 Product Added
AC Characteristics Changed
Ob_area Recommended Setting Changed
2
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
INTRODUCTION
The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG
0.18um CMOS image sensor process technology. It is developed for image application to realize high efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to the external devices, a camera system can be configured easily.
FEATURES
Process Technology: 0.18µm Dual Gate Oxide SPQM CMOS
Optical Size: 1/3 inch
Unit Pixel: 3.8 µm X 3.8 µm
Effective Resolution: 1280X1024, SXGA
Line Progressive Read Out.
10-bit Raw Image Data Output
Windowing and Panning
Sub-Sampling (2X, 4X, 8X)
Timing Generator for Frame Memoryless Scaler
Timing Generator for Stepless Zooming
Continuous and Single Frame Capture Mode
Programmable Exposure Time and Gain Control
Auto Dark Level Compensation
Standby Mode for Power Saving
Maximum 15 Frames per Second for Full Frame Readout with 24 MHz Output Data Rate
Bad Pixel Replacement
Dual Power Supply Voltage: 2.8V/1.8V (2.8V for analog, 1.8V for digital)
Package Type: 48-CLCC/PLCC
PRODUCTS
Product Code Power Supply Backend Process Description
S5K3A1EA01 2.8V / 1.8 V None Monochrome image sensor
S5K3A1EA02 2.8V / 1.8 V On-chip micro lens
S5K3A1EA03 2.8V / 1.8 V
S5K3A1EA13 2.8V / 1.8 V
High sensitivity monochrome
Image sensor
On-chip color filter
and micro lens
On-chip color filter
and micro lens
3
RGB color image sensor
RGB color image sensor
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
BLOCK DIAGRAM
MCLK
RSTN
STBYN
STRB
VSYNC HSYNC
DCLK
SCL SDA
VSSIO
VDDIO
Main Clock
Generator
I2C Interface
VDDD
Divider
Timing
Control
Registers
VSSD
Row
Driver
10-bit Column ADC
Odd Column CDS
Active Pixel
Sensor Array
Even Column CDS
10-bit Column ADC
VSSA
VDDA
Post
Processing
DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
4
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
PIXEL ARRAY MAP
(TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
10 4
Default Window of Interest
1280X1024
R B G G R B G G RBG
G
R B G
G
R B G
G
GR B G G
RBG
G
R B G G RBG
10
4
Active Pixels
G
RBGGRBGGRBG
GRBGGRBGG
RBG
G
RBGGRBGGRBG
Optical Black Pixels
10
4
(0,0)
(14,14) read out start point
4
10
5
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
VSSIO
VSSD
VDDA
VSSA
VSSA
VDDA
VDDA
VSSA
VSSA
VDDA
VDDD
VSSD
VDDIO
VDDD
VDDA
VSSA
VSSA
VDDA
VDDA
VSSA
VSSA
VDDA
VDDD
VSSD
PIN CONFIGURATION
6
5
4
3
MCLK
2
7
48
47
46
45
44
1
43
42
SDA
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DCLK
8
9
10
11
12
13
14
15
16
17
18
19
20
First Readout Pixel
21
22
23
24
25
26
27
28
29
41
40
39
38
37
36
35
34
33
32
31
30
SCL
RSTN
STBYN
STRB
VDDA
VSSA
VREF
TEST2
TEST1
HSYNC
VSYNC
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
MAXIMUM ABSOLUTE RATINGS
Characteristic Symbol Value Unit
Analog maximum absolute voltage (VDDA supply relative to VSSA )
V
DDH
-0.3 to 3.8
Digital and I/O maximum absolute voltage
V
(VDDIO supply relative to VSSIO
DDL
-0.3 to 2.7
VDDD supply relative to VSSD)
T
T
V
IN
OPR
STG
Input voltage
Operating temperature
Storage temperature
NOTES:
1. The maximum allowed storage temperature for S5K3A1EA01.
2. The maximum allowed storage temperature for S5K3A1EA02 and S5K3A1EA03.
-0.3 to 2.7
-20 to +60
(1)
(2)
-40 to +125
-40 to +85
V
°C
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S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
DC Characteristics
= -20 to +60°C, CL = 15pF)
(T
A
Characteristics Symbol Condition Min Typ Max Unit
Operating voltage
Input voltage
(1)
Input leakage
(2)
current
Input leakage current
(3)
with pull-down
High level output
(4)
voltage
Low level output
(5)
voltage
High-Z output leakage
(6)
current
Input capacitance
(1)
Supply current
V
DDH
V
DDL
V
V
I
IL
I
ILD
VOH
VOL
I
OZ
C
I
STBL
I
STBH
I
DDL
I
DDH
IH
IL
IN
applied to VDDA pins 2.6 2.8 3.0 V
applied to VDDIO and VDDD pin 1.65 1.8 1.95
VIN = V
VIN = V
I
= -1µA
OH
DDL
DDL
- 1.27 - -
- - - 0.57
-10 - 10
5 18 40
-
V
DDL
- - V
0.05
I
= -4mA
OH
I
= 1µA
OL
= 4mA
I
OL
V
= VSS or V
OUT
STBYN=Low(Active)
DDL
- - - 4 pF
1.2 - -
- - 0.05
- - 0.45
-10 - 10
- - 10 All input clocks = Low 0 lux illumination applied to VDDIO and VDDD pin
STBYN=Low(Active)
- - 10 All input clocks = Low 0 lux illumination applied to VDDA pin
f
MCLK
= 12MHz
- 10 15 mA 0 lux illumination
applied to VDDIO and VDDD pin
f
MCLK
= 12MHz
- 20 25 mA 0 lux illumination
applied to VDDA pin
µA
µA
µA
µA
NOTES:
1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pins.
2. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA pins
3. Applied to TEST1, TEST2 pin
4. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin. I
5. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin. I
6. Applied to SDA pin when in High-Z output state
8
: High level output current
OH
: Low level output current
OL
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
9
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. T
= 25°C if not specified.)
A
Characteristic Symbol Condition Min Typ Max Unit
(2)
(3)
(1)
Saturation level
Sensitivity
Dark level
Dynamic range
Signal to noise ratio
Dark signal non-uniformity
(4)
(5)
(6)
Photo response non-
(7)
uniformity
Vertical fixed pattern noise
(8)
Horizontal fixed pattern noise
NOTES:
1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels.
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC.
5. 20 log (average output level / RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 rows at 25% of saturation level illumination for exposure time 1/30 sec.
V
SAT
- 600 650 - mV
S - - 1500 - mV/lux sec
V
DARK
T
= 40°C
A
T
= 60°C
A
- 4 8 mV/sec
- 20 40
DR - - 60 - dB
S/N - - 40 -
DSNU
T
= 60°C
A
- - 40 mV/sec
PRNU - - 4 8 %
VFPN - 4 8 %
(9)
HFPN - 4 8 %
10
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
AC Characteristics
= 2.8V ± 0.25V, V
(V
DDH
DDL
Characteristic Symbol Condition Min Typ Max Unit
Main input clock frequency
Data output clock frequency
Propagation delay time from main input clock
Propagation delay time from data output clock
Reset input pulse width
Standby input pulse width
NOTES:
1. T
is the period of the master input clock, MCLK.
MCLK
= 1.8V ± 0.15V, TA = -20 to + 60 °C, C
f
MCLK
f
DCLK
t
PDMV
t
PDMH
t
PDMD
t
PDMO
t
PDDV
t
PDDH
t
PDDO
t
WRST
t
WSTB
Duty = 50% 6 12 48 MHz
- 6 12 30
VSYNC output - - 10 ns
HSYNC output - - 10
DCLK output - - 6
DATA output - - 10
VSYNC output - - 4
HSYNC output - - 4
DATA output - - 4
RSTN=low(active) 5 - -
STBYN=low(active) 4 - -
= 10pF)
L
T
MCLK
(1)
MCLK
DCLK
DATA
HSYNC
VSYNC
0.5VDD
t
PDMD
t
PDMO
t
t
PDDO
t
PDDH
t
PDMH
t
PDDV
t
PDMV
PDMD
t
PDDH
t
PDMH
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