Samsung S524L50D51 Datasheet

S524L50D51

16K-bit

Serial EEPROM

Data Sheet

OVERVIEW

The S524L50D51 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced CMOS technology. One of its major features is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524L50D51 is its support for fast mode and standard mode.

FEATURES

I2C-Bus Interface

• Two-wire serial interface

• Automatic word address increment

EEPROM

• 16 Kbits (2,048 bytes) storage area

• 16-byte page buffer

• Typical 3 ms write cycle time with

auto-erase function

• Hardware-based write protection for the entire EEPROM (using the WP pin)

• EEPROM programming voltage generated on chip

• 1,000,000 erase/write cycles

• 100 years data retention

Operating Characteristics

• Operating voltage: 2.0 V to 5.5 V

• Operating current

— Maximum write current: < 3 mA at 5.5 V — Maximum read current: < 200 µA at 5.5 V — Maximum stand-by current: < 2 µA at 2.0 V

• Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial)

• Operating clock frequencies — 100 kHz at standard mode — 400 kHz at fast mode

• Electrostatic discharge (ESD) — 5,000 V (HBM) — 400 V (MM)

Packages

• 8-pin DIP, SOP, and TSSOP

5-1

S524L50D51 SERIAL EEPROM DATA SHEET

SDA

SCL

A0 A1 A2

Start/Stop

Logic

Slave Address

Comparator

Control Logic

Word Address

Pointer

Row

decoder

HV Generation Timing Control

EEPROM Cell Array

2,048 x 8 bits

Column Decoder

Data Register

DOUT and ACK

Figure 5-1. S524L50D51 Block Diagram

5-2

DATA SHEET S524L50D51 SERIAL EEPROM

VCC WP SCL SDA

S524L50D51

A0 A1 A2 VSS

NOTE: The S524L50D51 is available in

8-pin DIP, SOP, and TSSOP package.

Figure 5-2. Pin Assignment Diagram

Table 5-1. S524L50D51 Pin Descriptions

Name Type Description Circuit

A0, A1, A2

VSS

– No internal connection – – Ground pin. –

SDA I/O Bi-directional data pin for the I2C-bus serial data interface. Schmitt

trigger input and open-drain output. An external pull-up resistor must be connected to V

DD.

SCL Input Schmitt trigger input pin for serial clock input. 2

WP Input Input pin for hardware write protection control. If you tie this pin to

the write function is disabled to protect previously written data

CC,

in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to V

VCC

NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.

– Single power supply. –

SS.

Type

5-3

S524L50D51 SERIAL EEPROM DATA SHEET

Figure 5-3. Pin Circuit Type 1

SDA

VSS

SCL

Noise

Filter

Figure 5-4. Pin Circuit Type 2

Data Out

Noise

Filter

Data In

Figure 5-5. Pin Circuit Type 3

5-4

DATA SHEET S524L50D51 SERIAL EEPROM

FUNCTION DESCRIPTION

I2C-BUS INTERFACE

The S524L50D51 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a

pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is

a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Only one S524L50D51 devices can be connected to the I2C-bus as slaves (see Figure 5-

6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines

which bus operating mode would be active.

SDA

SCL

Master

Bus Master

(Transmitter/

Receiver)

Figure 5-6. Typical Configuration

Slave

S524L50D51

5-5

S524L50D51 SERIAL EEPROM DATA SHEET

I2C-BUS PROTOCOLS

Here are several rules for I2C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy.

— MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remains stable whenever the clock line (SCL) is High.

The I2C-bus interface supports the following communication protocols:

• Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active.

• Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in

High level. All bus commands must be preceded by a start condition.

• Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 5-7).

SCL

SDA

Start

Condition

Data or

ACK Valid

Data

Change

Stop

Condition

Figure 5-7. Data Transmission Sequence

• Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited.

• ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress.

In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors

the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode.

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