Samsung S524A40X10, S524A40X20, S524A40X40 Datasheet
S524A40X10/40X20/40X40
1K/2K/4K-bit
Serial EEPROM for Low Power
with software write protect
Data Sheet
OVERVIEW
The S524A40X10/40X20/40X40 serial EEPROM has a 1,024/2,048/4,096-bit (128/256/512-byte) capacity,
supporting the standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced CMOS
technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). Important features
are a hardware-based write protection circuit for the entire memory area and software-based write protection logic
for the lower 128 bytes. Hardware-based write protection is controlled by the state of the write-protect (WP) pin.
The software-based method is one-time programmable and permanent. Using one-page write mode, you can
load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the
S524A40X10/40X20/40X40 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 1K/2K/4K-bit (128/256/512-byte) storage area
• 16-byte page buffer
• Typical 3 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• Software-based write protection for the lower
128-byte EEPROM
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
Operating Characteristics
• Operating voltage
— 1.8 V to 5.5 V
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 1 µA at 5.5 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
2-1
S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET
SDA
WP
SCL
A0
A1
A2
Start/Stop
Logic
Slave Address
Comparator
Control Logic
Word Address
Pointer
Row
decoder
HV Generation
Timing Control
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
Column Decoder
Data Register
DOUT and ACK
Figure 2-1. S524A40X10/40X20/40X40 Block Diagram
2-2
DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM
VCC WP SCL SDA
S524A40X10/
40X20/40X40
A0 A1 A2 VSS
NOTE: The S524A40X10/40X20/40X40 is available
in 8-pin DIP, SOP, and TSSOP package.
Figure 2-2. Pin Assignment Diagram
Table 2-1. S524A40X10/40X20/40X40 Pin Descriptions
Name Type Description Circuit
Type
A0, A1, A2
Input Input pins for device address selection. To configure a device address,
these pins should be connected to the VCC or V
of the device.
SS
These pins are internally pulled down to VSS.
VSS
– Ground pin. –
SDA I/O Bi-directional data pin for the I2C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
Typical values for this pull-up resistor are 4.7 kΩ
CC.
(100 kHz) and 1 kΩ (400 kHz).
SCL Input Schmitt trigger input pin for serial clock input. 2
WP Input
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to VSS, the write function is enabled.
This pin is internally pulled down to VSS.
1
3
1
VCC
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
– Single power supply. –
2-3
S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET
A0, A1,
A2, WP
Figure 2-3. Pin Circuit Type 1
SDA
SCL
Noise
Filter
Figure 2-4. Pin Circuit Type 2
Data Out
VSS
Noise
Filter
Figure 2-5. Pin Circuit Type 3
Data In
2-4
DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524A40X10/40X20/40X40 supports the I2C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524A40X10/40X20 (four for
S524A40X40) devices can be connected to the same I2C-bus as slaves (see Figure 2-6). Both the master and
slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would
be active.
V
CC
V
CC
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
S524A40X20
Tx/Rx
A0 A1 A2
To VCC or V
NOTE: The A0 does not affect the device address of the S524A40X40.
SS
Slave 2
S524A40X20
Tx/Rx
A0 A1 A2
To VCC or V
SS
Slave 3
S524A40X20
Tx/Rx
A0 A1 A2
To VCC or V
SS
Slave 8
S524A40X20
A0 A1 A2
To VCC or V
Figure 2-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
Tx/Rx
SS
R
R
2-5
S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
• Bus not busy: The SDA and the SCL lines remain High level when the bus is not active.
• Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High
level. All bus commands must be preceded by a start condition.
• Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains
High level. All bus operations must be completed by a stop condition (see Figure 2-7).
~
~
SCL
~
~
SDA
Start
Condition
Data or
ACK Valid
Data
Change
Stop
Condition
Figure 2-7. Data Transmission Sequence
• Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
• ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of
data (see Figure 2-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.
2-6
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