Samsung S1L9251X Datasheet

CD-ROM 48X RF AMP S1L9251X
INTRODUCTION
CD-ROM 48X RF AMP Chip is RF pre signal processor and processes signals from optical pick-up. This chip processes main signal through summing amp, AGC block, EQ block, and generates SERVO error signals for SERVO control. It can playback CD-ROM and CD-RW disc.
MAIN FEATURES (FEATURES, CHARACTERISTICS)
CD-ROM 48X
Support CD-R/RW disc
RF Amp & Equalizer
Focus Error Amp
Tracking Error Amp (3-Beam)
Mirror (RFCT, RFRP) Signal Detection
Defect Signal Detection
Built-in AGC Function
ALPC (Automatic Laser Power Control) Block
Built-in RF Envelop Detector
SBAD Signal Generation
Signal Generation for Center Position Servo
Built-in Serial Interface Port
Power Down Mode
1
S1L9251X CD-ROM 48X RF AMP
BLOCK DIAGRAM
Internal Block Diagram
LDO
PD
SUM
VCC
VR
CLPF
44 43 42 41 40 39 38 37 36 35 34
1
+
-
Peak
Bottom
Peak
AGCLPF
DVCC
Vbg
2
3
4
A
B
5
6
C
7
D
8
9
­+
VCC
­+
+
-
+
-
+
-
+
-
Peak
Bottom
+
-
­+
offset
+
-
­+
DVC
­+
+
-
Peak
+
-
RFRPICP_ENVRFEQOAGCINCAGCPLLFLPFADJRFOCM8CM4
33
RFRP
32
CP2
31
CB2
30
RFCT
CDFCT
29
28
+
-
DVCC
­+
CC2
CC1
27
26
DFCT
25
VDD
-
E
10
11
F
12 13 14 15 16 17 18 19 20 21 22
GND DVCC DVC SBADFE TE RFCLK
­+
+
­+
VSS
­+
CSERVOCSERC
SERIAL
I/F
SEROUT
24
RFEN
23
RFDATA
2
CD-ROM 48X RF AMP S1L9251X
External Application
RF Output
LD PD
SUM
A B C D E F
LASER PICK UP
2.5V Analog Voltage Output
VCC
VR
44 43 42 41 40 39 38 37 36 35 34
RFO
CM8
CM4
1
LDO
2
PD
3
SUM
4
A
5
B
6
C
7
D
8
VCC
9
VR
10
E
11
F
GND
DVCC
DVC
12 13 14 15 16 17 18 19 20 21 22
LPFADJ
FE
PLLF
SBAD
CLPF
TE
VCCDSP
CAGC
VSS
AGCIN
CSERC
RFEQO
CSERVO
CP_ENV
SEROUT
RFRPI
RFRP
CP2
CB2
RFCT
CDFCT
CC2
CC1
DFCT
VDD
RFEN
RFDATA
RFCLK
33
32
31
30
29
28
27
26
25
24
23
RFRP Output
VR
VR
RFCT Output
DFCT Output
VDD
Enable Signal Input
Serial Data Input
GND
DVCC
1.65V SBAD Output
FE Output
TE Output
Center Servo
Output
Clock Input
3
S1L9251X CD-ROM 48X RF AMP
PIN DESCRIPTION
No Name I/O Description Related Block
1 LDO O Output of ALPC block ALPC 2 PD I Input for ALPC block ALPC 3 SUM I Input for ABCD signal RFSUM 4 A I Input for A signal RFSUM 5 B I Input for B signal RFSUM 6 C I Input for C signal RFSUM 7 D I Input for D signal RFSUM 8 VCC P
9 VR O 2.5V Reference voltage output Bias 10 E I Input for E signal TE Amp 11 F I Input for F signal TE Amp 12 GND P Ground for Analog Block Analog 13 DVCC P Power input for Digital Block DSP 14 DVC O 1.65V Reference Voltage output Bias 15 FE O Focus Error signal output FE Amp 16 SBAD O Sub Beam ADD output SBAD 17 TE O Tracking Error signal output TE Amp 18 VSS P Digital GND Digital 19 CSERC I Time constant setting for center position servo SERVO 20 CSERVO O Time constant setting for center position servo SERVO 21 SEROUT O Error signal output for center position servo SERVO 22 RFCLK I Clock input for serial interface S I/F 23 RFDATA I Data input for serial interface S I/F 24 RFEN I Data Enable input for serial interface S I/F
Power input for Analog Block
Analog
25 VDD P Digital VDD Digital 26 DFCT O Defect Detection Comparator output DFCT 27 CC1 O Bottom Hold output of Defect detection Amp DFCT 28 CC2 I DFCT Bottom Hold DFCT 29 CDFCT I Capacitor for DFCT Bottom Hold DFCT 30 RFCT O RFCT output , ENV output Mirror 31 CB2 O Capacitor for RFRP, RFCT Mirror
4
CD-ROM 48X RF AMP S1L9251X
PIN DESCRIPTION (Continued)
No Name I/O Description Related Block
32 CP2 O Capacitor for RFRP, RFCT Mirror 33 RFRP O RFRP output Mirror 34 RFRPI I Input for MIRR MIRR 35 CP_ENV I Capacitor for Envelope Hold ENV 36 RFEQO O Summing and EQ signa of A,B,C,Dl RFSUM 37 AGCIN I Input for AGC AGC 38 CAGC I Hold Capacitor for AGC AGC 39 CLPF I LPF output buffer REF connecting pin AGC 40 PLLF I RF Frequency control for wide band PLL EQ 41 LPFADJ O LPF Frequency select for wide band PLL EQ 42 RFO O RF Signal Output RFSUM 43 CM8 O EQ Boost frequency for 8X speed EQ 44 CM4 O EQ Boost frequency for 4X speed EQ
SERIAL INTERFACE
Serial Interface Timing Graph
— The Serial Interface controls the Disc type, Speed, AGC, and Laser Diode On/Off. — The Timing Diagram of the Serial Interface is shown below:
RFEN RFDATA RFCLK
— RFCLK : Clock synchronized with data from MICOM — RFDATA : Address and Data from MICOM — RFEN : Indicates Data is Enabled
Address, 8-bit Data, 8-Bit
A7 A0 D7 D0
5
S1L9251X CD-ROM 48X RF AMP
Control signals generated from each Address are as below:
ADDRESS 01H; : RFEQ_SEL : ABCD_ATT
ADDRESS 02H; : EQG_CEN : AGC_LVL : C48_SEL : CAV_SEL
ADDRESS 03H; : AGCON : AGCIN_Z : GAIN_PLLF : PUP_SEL
ADDRESS 04H; : TE_LPF : TE_ATT
ADDRESS 05H; : DFCT_CNST : FE_LPF : FE_ATT
ADD 01H 0 0 0 0 0 0 0 1 ADD 02H 0 0 0 0 0 0 1 0 ADD 03H 0 0 0 0 0 0 1 1 ADD 04H 0 0 0 0 0 1 0 0 ADD 05H 0 0 0 0 0 1 0 1 ADD 06H 0 0 0 0 0 1 1 0 ADD 07H 0 0 0 0 0 1 1 1 ADD 08H 0 0 0 0 1 0 0 0 ADD 09H 0 0 0 0 1 0 0 1 ADD 0AH 0 0 0 0 1 0 1 0 ADD 0BH 0 0 0 0 1 0 1 1 ADD 0FH 0 0 0 0 1 1 1 1
Table 1. Address Number
7 6 5 4 3 2 1 0
ADDRESS 06H; : SERVO_OFST
ADDRESS 07H; :TBAL
ADDRESS 08H; : RFRP_FREQ : RFRP_TH : DFT_TH
ADDRESS 09H; : SBAD_ATT : RFRP_ATT1
ADDRESS 0AH; : LD_ON
ADDRESS 0BH; : RFRP_SEL
ADDRESS 0FH; : MODE_SEL :PDmode
6
CD-ROM 48X RF AMP S1L9251X
Serial Interface
Address: 01H
DATA D7 D6 D5 D4 D3 D2 D1 D0
Function RFEQ_SEL RSV ABCD_ATT
Initial Value 1 0 0 1 0 0 1 0
RFEQ_SEL (D7 - D4): EQ Mode
D7 D6 D5 D4 RF EQ SELECT
0 0 0 0 32X 0 0 0 1 26X 0 0 1 0 21X 0 0 1 1 19X 0 1 0 0 16X 0 1 0 1 13X 0 1 1 0 11X 0 1 1 1 8X(CAV) 1 0 0 0 8X(CLV) 1 0 0 1 4X 1 0 1 0 1X
ABCD_ATT (D2 - D0): ABCD attenuate gain select
D2 D1 D0 MODE
0 0 0 6dB 0 0 1 2.5dB 0 1 0 0dB 0 1 1 2dB 1 0 0 3.5dB 1 0 1 5dB 1 1 0 6dB
7
S1L9251X CD-ROM 48X RF AMP
Address : 02H
DATA D7 D6 D5 D4 D3 D2 D1 D0
Function RSV EQG_CEN C48_SEL CAV_SEL AGC_LVL
Initial Value 0 0 1 0 0 0 0 1
EQG_CEN (D6 - D4): Center gain fine control of EQ boost gain select
D6 D5 D4 CENTER BOOST GAIN
0 0 0 3.5dB 0 0 1 4.5dB 0 1 0 5.5dB 0 1 1 6.5dB 1 0 0 7dB 1 0 1 7.5dB
C48_SEL (D3) : 4X, 8X select
0 : 4X 1 : 8X
CAV_SEL (D2) : CAV, CLV select
0 : CAV mode 1 : CLV mode
AGC_LVL (D1 - D0): Output level select of AGC Amp
D1 D0 LEVEL
0 0.75V 0 1 1.0V 1 1.25V 1 1 1.5V
8
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