DEFLECTION PROCESSOR FOR MULTISYNC MONITORSS1D2147A01
DEFLECTION PROCESSOR
42-SDIP-600
The S1D2147A01is a monolithic integrated circuit assembled
in a 42 pins shrunk dual in line plastic package.
The goal of this IC is to control all the functions related to the
horizontal and vertical deflection in multimodes or multisync
monitors.
FUNCTIONS
• Positive or Negative sync polarities
• Auto-sync horizontal processing
• H-PLL lock/unlock identification
• Auto-sync Vertical processing
• East/West signal processing block
• B+ controller
• Safety blanking output
ORDERING INFORMATION
DevicePackageOperation Temperature
FEATURES
(HORIZONTAL)
• Dual Pll concept
• Self-adaptative (30 to 70kHz)
• X-ray protection input
• DC adjustable duty-cycle
• Internal 1stPLL lock/unlock information
• Wide range DC controlled H-position
• ON/OFF switch (for PWR management)
• Two H-drive polarities
(VERTICAL)
• Vertical ramp generator
• 50 to 120Hz AGC Loop
• DC controlled V-amp, V-pos, S-amp & S-centring
• ON/OFF Switch
(B+ REGULATOR)
S1D2147A01-A0B042-SDIP0 °C — 70 °C
(GENERAL)
• Accept Positive or Negative Horizontal &
Vertical sync polarities
• Separate H & V TTL input
• Safety blanking output
(E
WPCC
)
• Internal PWM generator for B+ current mode
step-up conveter
• DC adjustable B+ voltage
• Output pulse synchronised on horizontal frequency
• Internal MAX current limitation
• Vertical parabola generator with DC
• controlled keystone & amplitude
0
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
BLOCK DIAGRAM
R0
PLL1NHIB
3515
H-POS
PLL1F
1211
10
C0
FH-MIN
14
HLOCK-CAP
133
HFLY
PLL2C
H-DUTY
H-OUTEM
122021
H-OUTCOL
HSYNC
XRAY-IN
HREF
HGND
VREF
VGND
VSYNC
16
26
24
34
17
INPUT
INTERFACE
5
H-VREF
4
V-VREF
INPUT
INTERFACE
19
GND
18
VCC
1st PHASE
COMP
BANDGAP
OSCILLATOR
VERTICAL
VCAP
VAGCCAP
VCO
CORRECTION
VS-CENT
S
2nd PHASE
COMP
LOCK
DETECT
+
SAFETY
PROCESSOR
VCC
OUTPUT
INHIBITION
28292725
333130323837
V-POS
VS-AMP
V-AMP
EA
-
VOUT
PHASE
SHAPER
DCOUT
V
V
REF
+
PARABOLA
GENERATOR
KEYST
-
OUTPUT
BUTTER
EW-AMP
23
SBLKOUT
39
B+ADJ
42
R
22
S
41
40
36
I
SENSE
B+OUT
COMP
REGIN
E/WOUT
1
DEFLECTION PROCESSOR FOR MULTISYNC MONITORSS1D2147A01
PIN CONFIGURATIONS
1
2
4
5
6
7
8
9
10
11
12
3
PLL2C
H-DUTY
HFLY
HGND
HREF
NC
NC
NC
NC
C0
R0
PLL1F
I-SENSE
COMP
REGIN
B+ ADJ
KEYST
E/W-AMP
E/WOUT
PLL1-INHIB
VSYNC
V-POS
V-DCOUT
S1D2147
V-AMP
42
41
40
39
38
37
36
35
34
33
32
31
13
HLOCK-CAP
14
FH-MIN
15
H-POS
16
XRAY-IN
17
HSYNC
18
VCC
19
GND
20
H-OUTEM
21
H-OUTCOL
VOUT
VS-CENT
VS-AMP
VCAP
VREF
VAGCCAP
VGND
SBLK-OUT
B+ OUT
30
29
28
27
26
25
24
23
22
2
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PIN DESCRIPTION
Table 1. Pin Description
Pin NoPin NameDescription
1PLL2C Second PLL Loop Filter
2H-DUTY DC Control of Horizontal Drive Output Pulse Duty-cycle.
If this pin grounded, the horizontal and vertical outputs are inhibited. By connecting a
capacitor on the this pin a soft-start function may be realized on h-drive output.
3 H-FLY Horizontal Flyback Input (Positive Polarity)
4H-GND Horizontal section ground. Must be connected only to components related to H
blocks.
5H-REF Horizontal section reference voltage. Must be filtered by capacitor to pin 4.
6NC
7NC
8NC
9NC
10C0 Horizontal Oscillator Capacitor. To be connected to pin 4.
11R0 Horizontal Oscillator Resistor. To be connected to pin 4.
12PLL1F First PLL Loop filter. To be connected to pin 4.
13HLOCK-CAP First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the freqency
change detected on pin 13. When frequency is changing, a blanking pulse is
generated on pin 23, the duration of this pulse is proportionnal to the capacitor on
pin 13. To be connected to pin 4.
14FH-MIN DC Control for free running frequency setting. Comming from DAC output or DC
voltage generated by a resistor bridge connected between pin 5 and 4.
15H-POS DC Control for Horizontal Centering
16XRAY-IN X-RAY Protection input (with Internal latch function)
17H-SYNC TTL Horizontal Sync Input
18Vcc Supply Voltage (12V Typical)
19GND Ground
20H-OUTEM Horizontal Drive Output (emiter of internal transistor)
21H-OUTCOL Horizontal Drive Output (open collector of internal transistor)
22B+OUT B+ PWM Regulator output
23SBLK
OUT
Safety Blanking output. Activated during frequency changes, when X-RAY input is
triggered or when VS is too low.
24VGND Vertical Section Signal Ground
25VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26V
REF
Vertical Section Reference Voltage
3
DEFLECTION PROCESSOR FOR MULTISYNC MONITORSS1D2147A01
Table 1. Pin Description (Continued)
Pin NoPin NameDescription
27VCAP Vertical Sawtooth Generator Capacitor
28 VS-AMPDC Control of Vertical S-Shape Amplitude
29 VS-CENTDC Control of Vertical S-Centering
30 V-OUTVertical Ramp Output (with frequency independant amplitude and S-Correction)
31 V-AMPDC Control of Vertical Amplitude Adjustment
32 VDCOUTVertical Position Reference Voltage Output Temperature matched with V-AMP
output
33 V-POSDC Control of Vertical Position Adjustment
34 V-SYNCVertical TTL Sync Input
35PLL1INHIBTTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input
signal)
36E/WOUTEast/West Pincushion Correction Parabola Output
37 E/W-AMPDC Control East/West Pincushion Correction Amplitude
38 KEYSTDC Control of Keystone Correction
39 B+ADJDC Control of B+ Adjustment
40 REGINRegulation Input of B+ Control Loop
41 COMPB+ Error Amplifier Output for Frequency Compensation and Gain Setting
42 I
SENSE
Sensing of External B+ Switching Transistor Emitter Current
4
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
ABSOLUTE MAXIMUM RATINGS
NOItemSymbol Spec Unit
1Supply Voltage (Pin 18)V
2Maximum Voltage on Pins 2, 14,15, 28, 29, 31, 33, 37, 38, 39
Pin 3
Pins 17, 34
Pin 40
Pin 42
Pin 16
3ESD Succeptibility
Human Body Model, 100pF Discharge through 1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
Oscillator Resistor Min Value (Pin 11)R0min 6kΩ
Oscillator Capacitor Min Value (Pin 10)C0min390pF
Maximum Oscillator FrequencyFmax70kHz
Horizontal Sync Input Voltage (Pin 17)HsVR0 5.5V
INPUT SECTION
Minimum Input Pulses Duration (Pin 17)MinD1 µS
Maximum Input Signal Duty Cycle (Pin 17)Mduty25%
OUTPUT SECTION
Maximum Input Peak Current (Pin 3)I3m 2 mA
Horizontal Drive Output Max Current
Pin 20
Pin 21
DC CONTROL VOLTAGE
HOI1
HOI2
Sourced current
Sink current
20
20
mA
mA
5
DEFLECTION PROCESSOR FOR MULTISYNC MONITORSS1D2147A01
ParameterSymbol Conditions Min Typ Max Unit
DC Voltage Range on DC Controls (Pins 2-14-15)DCadj V
= 8V 26 V
REF-H
6
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Vertical sync input bias current
(Current sourced by PNP base)
Voltage at ramp bottom pointVRB On Pin 272/8VREF-V
Voltage at ramp top point (with sync)VRT On Pin 275/8VREF-V
Voltage at ramp top point (without sync)VRTF On Pin 27VRT-0.1V
IBIASP For V23-28-29 = 2V2°C
IBIASN For V31 = 6V0.5°C
2
Low -level
VSBI V34 = 0.8V1 µA
0.8
V
V
8
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Keystone adjustment capability
B/A ratio
A/B ratio
Parabola amplitude adjustment capability
Maximum amplitude on pin 36
Maximum ratio between max and min
NOTES:
1. These parameters are not tested on each unit. They are measured during our internal qualification procedure
which includes characterization on batches comming from comers of our processes and also temperature
characterization.
2 . When 2V are applied on pin 28 (Vertical S-Correction control ), then the S-Correction is inhibited, consequently the
sawtooth have a linear shape.
3.It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchorize, using a single
capacitor value on Pin 27 and with a constant ramp amplitude.
4.Typically 3.5V for vertical reference voltage typical value (8V).
Kadj See figure 2; V37 = 4V
V38 = 2V
V38 = 6V
Paramp V38 = 4.3V, V28 = 2V
V37 = 2V
2V < V37 < 6V
3.3
2.4
2.3
2.0
V
3.834.3
11
DEFLECTION PROCESSOR FOR MULTISYNC MONITORSS1D2147A01
APPLICATION CIRCUIT
AFC
10nF
H-POSI
27k
6W
H-ref
1/
12V
1
22nF
24k 1/6W
1nF 50v
4.7uF
1.2k
1/6W
4.7k
1/6W
+
470uF
16V
+
H-SYNC1
1k 1/6W
103
+
100uF 16V
680pF MONO
1.5k
1/6W
100nF
1N4148
1N4148
1k 1/6w
18k 1/
6W
+
10uF
1K 1/6W
100pF 50V
1/6W
100V
5.6k 1/4W MF
1.8k
30k 1/8W
2.20nF
220nF MP
22nF MP
100V
20k
1/4W
MF
5.6k 1/6W
1N4148
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PLL2C
H-DUTY
HFLY
HGND
HREF
S4
S3
S2
S1
C0
R0
PLL1F
HLOCK-CAP
FH-MIN
H-POS
XRAY-IN
HSYNC
VCC
GND
H-OUTEM
H-OUTCOL
PLL1-INHIB
S1D2147A01
VAGCCAP
SBLK-OUT
I-SENSE
COMP
REGIN
B+ ADJ
KEYST
E/W-AMP
E/WOUT
VSYNC
V-POS
V-DCOUT
V-AMP
VOUT
VS-CENT
VS-AMP
VCAP
VREF
VGND
B+ OUT
42
D
KEY-STONE
E/W OUT
1uF
+
47k 15k
1/6W
100uF
I-SENSE
H-REF
AFC
H-SIZE
S-PIN
5V
6.8k
To vertical Amp(+)
V-SIZE
To vertical Amp
V-LIN
Vref
+
16V
B+ DRIVE
41
1M
40
39
38
37
36
35
36K 1/6W
34
33
32
31
30
29
28
27
26
25
24
23
22
22k 1/6W
+
3.3k
1/6W
20k
0.47uF
R
R
56K 1/6W
22K 1/6W
1K 1/6W
12k 1/6W
33k 1/6W
10k 1/6W
47K 1/6W
220 nF 64V
1N4148
1uF
V-sync
V-posi
47k
1/6W
+
82k 1/6W
C
100nF
10nF
12V
H-DRIVE
Figure 1. Application Circuit
12
S1D2147A01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
V
36
AB
V
27
3.8
3.5
3.2
Figure 2. Keystone Adjusment
V
27
V38 = 2V
V38 = 4V
V38 = 6V
4.0V
3.5V
3.0V
Figure 3. Amplitude Adjusment
V
30
0T/4T/23T/2T
¡âV increase when V28 increase.
¡âV = 0 when V28 = 0.
T0
¡âV
V30pp
Figure 4. Correction Adjusment
13
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