Samsung q20 Schematics

5-1 System Main Board Schematic Diagrams

5-1Sens Q 20

5 System Schematic Diagrams and PCB Silkscreen

15.

3.

13.

Model Name :

1.

31.

12.

T.R. Date :

27.

WS JUNG

BANIAS LV

4.

BA41-00377A

18.

855GM

PCB Code :

CPU :

11.

29.

Remarks :

20.

10.

HJ KIM

Chip Set :

16.

25.

28.

2003. 4. 24

1.0

Kevin

30.

19.

22.

Dev. Step :

CHECK

26.

21.

6.

5.

APPROVAL

2.

8.

MP

14.

7.

24.

9.

17.

CETUS Main

23.

CETUS

Revision :

DRAW

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-2

5-1-1(a) System Main Board Schematic Sheet 2 of 40(BLOCK DIAGRAM)

PCI BUS

1394 (port 0)

EEPROM

p24

p23

p23

p22

IDE0

256MB/128MB

SODIMM

Max 1GB

CPU

BaniasLV

USB (port 1)

LAN switch

Clock generator

82801 DBM 1.5V

400MHZ

Docking

SPDIF

RJ-45(10/100)

1394 (port 1)

p28

p30

p18

(FACTORY OPTION)

Clocking

PIO

82562EZ

FIR(Option)

#0

#1

266DDR

On Board

Internal KBD

Touch Pad

87391

p11,p13,p14

p12

USB

BLUETOOTH

p29

p15,p16,p17

p30

p20,p21

p21 p21

port3

LPC

FWH

82802A

MICOM

AC LINK

HDD

RJ-11

MDC

SPKR

HI 1.5

RJ-45(10/100)

EEPROM

p20

GMCH-M

855GM

ICH4 - M

CONN

WLAN/Bluetooth

Docking

CRT

2 USB (port4,5)

CardBus +

1394 Lynx+PHY

R5C591

CARD BUS

Mini PCI

THERMISTER

ADM1032

LCD

CRT

(1.2V)

(100MHZ, 4*)

HP JACK

PS/2

AMP

p4

p25

p29

p28

p19

Hitachi 2160

p24

p24

p24

p24

/2ND HDD

p19

(AC97 2.2)

CS4202

MIC JACK

LOM

KINNERITH+

p20

p22

p5

p5,p6

p7,p8,p9,p10

SIO

p29

p29

SD(MMC) + MS

FDD/ODD

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 20

5-1-1(b) System Main Board Schematic Sheet 3 of 40(BOARD INFORMATION)

Devices

ICH4M

SODIMM0

0100 110x

Hex

4Ch

PCI Devices

Devices IDSEL#

Cardbus

USB

Hub to PCI

SYSTEM PORT RIGHT

LPC bridge/IDE/AC97/SMBUS

1

AGP5Internal MAC

3

AD19

AD20

AD29(internal)

E,F

AD30(internal)

AD31(internal)

AD17(internal)

AD24(internal)

REQ/GNT#

0

Interrupts

A,B,C

#0 : A

B

A,B

#1 : D

#2 : C

-

-

E

---

-

I2 C / SMB Address

P1.25V

Address

P2.5V

ADM1032

LAN

Master11010 001x

5.0V power rail ( off in S4-S5)

-

USB2.0 : H

A2h

Bus

SMBUS Master

Thermal Sensor ( CPU )

-

Clock, Unused Clock Output DisableD2hCK-408 (Clock Generator) 1101 001x

Voltage Rails

Primary DC system power supply (9 to 12V)

1.5V switched power rail (off in S3-S5)

1.8V switched power rail (off in S3-S5)

VDC

VCC_CORE

P1.5V

P1.8V

USB PORT Assign

PORT NUMBER ASSIGNED TO

SYSTEM PORT LEFT

0

004

1

Docking

02021

AC Link - B-

MiniPCI SLOT1 BANIAS/MGM Processor System Bus(PSB) Termination (1.05V)VCCP

MCH-M Core Voltage (1.2V)VCC_MCH

Core voltage for BANIAS CPU (1.356 - 0.844V)

3.3V always on power rail for MICOM

3.3V power rail (off in S4-S5)

3.3V switched power rail (off in S3-S5)

5.0V switched power rail (off in S3-S5)

2.5V power rail (off in S4-S5)

P3.3V_AUX

P3.3V

P5V

P2.5V_AUX

MICOM_P3V

1.25V power rail (off in S4-S5)

0

2.5V switched power rail (off in S3-S5)

0

BLUETOOTH

0

AD21

1D1

P5V_AUX

1

Photo snesor72hTSL2550 0111 001x

MICOM Master - SMBUS Master

Battery 0001 011x 16h System Battery

CPU Core Voltage Table

VID4 VoltageVID3 VID2 VID1 VID0

00111001111

1

00111

00010100011

1

111

0

1.612 V

0

VID4

1

VID3

0

VID11011

1

000

1

00000000000

0

000

-

00101

1101000

1

01011

1.708 V

1.692 V

1.676 V

1.516 V

1.660 V

1.596 V

1.580 V

1.564 V

1.548 V

1.500 V

1.484 V

1.468 V

1.644 V

1.628 V01.532 V

0

Voltage

0

VID2

0

VID0

0

0

1.196 V

0

1100101

1

00111

00010100001

010

100

-

0

010011111

1

000

1

01001

1111101

111

1

0

1.180 V

1.164 V

1.004 V

1.148 V

1.084 V

1.068 V

1.052 V

1.036 V

0.988 V

0.972 V

0.956 V

1.132 V

1.116 V

1.100 V

1.020 V

VID500

000001000

10101

0

VID511

111111111

1

11111

0

0

1.452 V01.420 V11.404 V01.324 V01.292 V11.228 V

011

1

00010100011

1

111

0

01000111101

1

000

1

01001101010

1

01011

0

1.436 V

1

1.260 V

1

1.340 V11.308 V11.244 V11.212 V

1.388 V

1.372 V

1.356 V

1.276 V

00101100101

1

001

1

1

010

0.924 V

0

0.748 V

0

0.828 V00.796 V

1

1

11110

00010011111

1

0

00

1

-

1

1111111

111

11111

01001101010

1

010

1

0.940 V10.908 V00.892 V00.812 V00.780 V

0.732 V

0.716 V

0.700 V

0.876 V

0.860 V

0.844 V

0.764 V

00000000000

0

0

VCC (LFM = 600MHz)

0

- 100MHz Geyserville III steps supported

0

- 700MHz point not supported

1

Ultra Low Voltage CPU

1

- GV III points for LV Banias 1.1GHz = 600MHz, 800MHz, 900MHz

1

- TDP = 7W, Iccmax = 9A

11111

11111

11111111111

ICH4

1

MICOM

1

STAC9750

1

CPU

0

P3.3V_AUX0MDC

0000000

000-0

Highest Freq.

Deeper Sleep

Low Voltage Banias

VCC (HFM = 1.1/1.2GHz)

Low Voltage Banias

VCC (LFM = 600MHz)

Ultra Low Voltage Banias

VCC (HFM = 900MHz)

Ultra Low Voltage Banias

5C591

Low Voltage CPU

Docking

- GV III points for LV Banias 1.1/1.2GHz = 600MHz, 800MHz, 900MHz, 1GHz, 1.1/1.2GHz

- TDP = 12W, Iccmax = 12A

- 100MHz Geyserville III steps supported

- 700MHz point not supported

- Vcc (HFM = 1.1/1.2GHz) = 1.180V

- Vcc (LFM = 600MHz) = 0.956V

- Vcc (HFM = 900MHz) = 1.004V

- Vcc (LFM = 600MHz) = 0.844V

MICOM_P3V

POWER

P3.3V P5VP1.8V

MICOM ICH4

P1.5V VCCP

CLOCK

5C591

MINI-PCI

SODIMM

MICOM

S/IO

FWH

HDD HDD

MDC

MINI-PCI

CPUICH4

MINI-PCI

FIR

MGM

THERMISTER

MGM

P5V_AUX

ICH4

P2.5V_AUX

MGM

SODIMM

BLUETOOTH

ICH4

VCC_CORE

CPU

VCC_MCH

CPU

MGM

P1.5V_AUX

ICH4

5C591

5C591

Docking

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

5-3

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-4

5-1-1(c) System Main Board Schematic Sheet 4 of 40(CLOCK GENERATOR)

Close to chip

HCB3216K-601T20

Be sure to follow A/W guide line!

682088

48Mhz

CLK3_SIO14

CLK3_MCH66

CLK3_PCLKICH

CLK3_PCLKFWH

CLK3_PCLKCB

CLK3_PCLKMICOM

CLK3_DREFSSCLK

CLK_CPU*

CLK_CPUITP

CLK_CPUITP*

CLK3_DREF

CLK3_ICH66

CLK3_ICH14

CLK3_ICH48

CLK3_PCLKSIO

CLK3_PCLKMIN

SMB3_DATA

CLK_MCH

CLK_CPU

CHP3_SLPS1*

IMVP4_PWRGD

CHP3_CPUSTP*

CHP3_PCISTP*

SMB3_CLK

CLK_MCH*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-5Sens Q 20

5-1-1(d) System Main Board Schematic Sheet 5 of 40(BANIAS CPU)

CPU2_THERMDCSMB3_ALERT*

CHP3_OVERT*

KBC3_THERM_SMDATA

KBC3_THERM_SMCLK CPU2_THERMDA

CPU1_A20M*

CPU1_ADSTB1*

CPU1_ADSTB0*

CPU1_ADS*

CPU1_IGNNE*

CPU1_HITM*

CPU1_HIT*

CPU1_FERR*

CPU1_DRDY*

CPU1_DEFER*

CPU1_DBSY*

CPU1_BREQ*

CPU1_BPRI*

CPU1_BNR*

CPU1_RS0*

CPU1_LOCK*

CPU1_NMI

CPU1_INTR

CPU1_INIT* CPU1_DSTBP0*

CPU1_DSTBN0*

CPU1_D*(31:16)

CPU1_D*(15:0)

CPU1_DSTBN3*

CPU1_D*(63:48)

CPU1_D*(47:32)

CPU1_TRDY*

CPU1_STPCLK*

CPU1_SMI*

CPU1_RS2*

CPU1_RS1*

CPU1_A*(16:3)

CPU1_REQ*(4:0)

CPU1_CPURST*

CPU1_DSTBN1*

CPU1_DBI3*

CPU1_DSTBN2*

CPU1_DSTBP2*

CPU1_DSTBP3*

CPU1_DBI2*CPU1_DBI0*

CPU1_DSTBP1*

CPU1_DBI1*

CPU1_A*(31:17)

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-6

5-1-1(e) System Main Board Schematic Sheet 6 of 40(BANIAS CPU)

Placed as close as possible to

COMP 0 , 2 <(COMP 1,3) should be connected

of the First GTLREF0 with Z0= 55 ohm trace

Minimize coupling of any switching signals to this net

Z0=27.4 ohm (55 ohm) trace shorter than

PREQ,PRDY,BPM(0:3),TCK,TDI,TDO,TMS,TRST

PSI*

each of the four VCCA pins.

220uF * 4, 10uF *35

"Mobile Platform Design Checklist rev. 0.94 page19"

STUFFING OPTION

"ALL ITP I/F signals"

220uF = 12mohm(Max/4) 3.5nH/4

must have T.P.

GTLREF : Keep the Voltage divider within 0.5"

1/2 " to their respective Banias Pins

10uF = 5mohm(typ/35) 0.6nH/4

TEST3

CPU1_GTLREF0

VOS-

CPU1_PROCHOT*

CPU1_PSI*

CPU1_DPSLP*

CPU1_PWRGDCPU

CLK_CPU*

CPU3_VID(5:0)

CPU2_THERMDA

CPU2_THERMDC

CPU1_THRMTRIP*

CLK_CPU

CPU1_SLP*

CPU1_DPWR*

CLK_CPUITP

CLK_CPUITP*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-7Sens Q 20

5-1-1(f) System Main Board Schematic Sheet 7 of 40(GMCH-M)

HLZCOMP

Trace should be 10 mil,20mil spacing.

near component

CPURST* Length

near divider

GMCH-CPU : 1.0" ~ 6.0"

800mV +/- 8%

RCOMP reference voltage

GMCH-R-ITP : 12.0" max

Routing : 10 mil trace, 20 mil space

Checklist rev0.94

350mV +/- 8%

Trace should be 10 mil,20mil spacing.

near divider

near component

HUB1_REF_GMCH

GMCH1_PSWING

GMCH1_HDVREF

GMCH1_HCCVREF

GMCH1_HAVREF

GMCH1_HCCVREF

HUB1_REF_GMCH

GMCH1_PSWING

GMCH1_HAVREF

HUB1_STB*

HUB1_STB

CPU1_HITM*

CPU1_LOCK*

CLK_MCH*

CLK_MCH

CPU1_A*(31:3)

CPU1_TRDY*

CPU1_RS0*

CPU1_RS1*

CPU1_RS2*

CPU1_REQ*(4:0)

CPU1_D*(63:0)

GMCH1_HXSWING

GMCH1_HXSWING

CPU1_DSTBP0*

CPU1_DSTBN0*

CPU1_DBI0*

GMCH1_HYSWING

HUB1_HL(0:10)

CPU1_BREQ*

CPU1_DBI1*

CPU1_DBI2*

CPU1_DBI3*

CPU1_ADSTB0*

CPU1_ADSTB1*

CPU1_DSTBN1*

CPU1_DSTBN2*

CPU1_DSTBN3*

CPU1_DSTBP1*

CPU1_DSTBP2*

CPU1_DSTBP3*

GMCH1_HYSWING

GMCH1_HDVREF

CPU1_ADS*

CPU1_BNR*

CPU1_CPURST*

CPU1_BPRI*

CPU1_DBSY*

CPU1_DEFER*

CPU1_DRDY*

CPU1_HIT*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-8

5-1-1(g) System Main Board Schematic Sheet 8 of 40(GMCH-M)

SODIMM 0

On Board : 256MB

On Board : 256MB

Used to measure timing for the read data

SCK2/2*, SCK5/5*, these signal are NC.

SDQ[71:64], SDM8, SDQS8

SODIMM 0

SODIMM0

Both signals should have vias located adjacent to the package

ON BOARD

SODIMM 0

SODIMM 0

If ECC support is not implemented,

GMCH1_SMRCOMP

GMCH1_SMVSWINGH

GMCH1_SMVSWINGL

MEM2_SRASA*

MEM2_SWEA*

CLK2_MCLK1*

CLK2_MCLK3

CLK2_MCLK3*

CLK2_MCLK4

CLK2_MCLK4*

MEM2_CSA0*

MEM2_CSA1*

MEM2_CSA2*

MEM2_SCASA*

MEM2_CKE0

MEM2_CKE1

MEM2_CKE2

CLK2_MCLK0

CLK2_MCLK0*

CLK2_MCLK1

MEM2_MAA(12:0)

MEM2_MD(63:0)

GMCH1_SMRCOMP

MEM2_DQS(7:0)

GMCH1_SMVSWINGH

GMCH1_SMVSWINGL

MEM2_MAB(2:1)

MEM2_MAB(5:4)

MEM2_DM(7:0)

MEM2_BS0

MEM2_BS1

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-9Sens Q 20

5-1-1(h) System Main Board Schematic Sheet 9 of 40(GMCH-M)

T-topology

-10mil wide

-20mil spacing

As short as possible

Place near GMCH

GST2

CLK3_DREFSSCLK

CLK3_MCH66

DCK_VGA3_BLUE

DCK_VGA3_GREEN

DCK_VGA3_RED

VGA3_BLUE

VGA3_GREEN

VGA3_RED

CHP3_DCKIN*

VGA3_DDCC

VGA3_DDCD

CPU1_DPSLP*

CPU1_DPWR*

AGP3_BUSY*

DVO1_DPMS

CHP3_SUSCLK

DVO1_DPMS

VGA3_BKLTON

CLK3_DREF

VGA3_CLK-

VGA3_A1-

VGA3_CLK+

VGA3_A1+

VGA3_A0-

VGA3_A2-

VGA3_HSYNC

VGA3_VSYNC

PCI3_RST*

VGA3_A0+

VGA3_A2+

VGA3_LCDVDDON

IMVP4_PWRGD

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-10

5-1-1(i) System Main Board Schematic Sheet 10 of 40(GMCH-M)

Place two caps near MGM ACAP

VCCADPLLA

VCCADPLLB

VCCQSM

VCCASM

VCCQSM

VCCASM

VCCADPLLA VCCADPLLB

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-11Sens Q 20

5-1-1(j) System Main Board Schematic Sheet 11 of 40(DDR-ON BOARD)

D3

D2

D1

Close to memory as you can!

Close to memory as you can!

Close to memory as you can!

Close to memory as you can!

D0

MEM2_RMD(63:48)

CLK2_MCLK4*

CLK2_MCLK3

CLK2_MCLK4

MEM2_RDM(7)

MEM2_RDQS(7)

MEM2_RSRASA*

MEM2_RDM(6)

MEM2_RDQS(6)

MEM2_RSWEA*

MEM2_RMAA(12:6)

MEM2_MAB(5:4)

MEM2_MAB(2:1)

MEM2_RBS0

MEM2_RBS1

MEM2_RSCASA*

MEM2_CKE2

MEM2_CSA2*

MEM2_RSRASA*

MEM2_RDM(4)

MEM2_RDQS(4)

MEM2_RSWEA*

MEM2_RMAA(12:6)

MEM2_MAB(5:4)

MEM2_MAB(2:1)

MEM2_RMD(47:32)

MEM2_RMAA(0)

MEM2_RMAA(3)

MEM2_RDM(5)

MEM2_RDQS(5)

MEM2_RSWEA*

MEM2_RMAA(12:6)

MEM2_MAB(5:4)

MEM2_MAB(2:1)

MEM2_RDM(3)

MEM2_RDM(2)

MEM2_RDQS(3)

MEM2_RDQS(2)

MEM2_CSA2*

MEM2_CKE2

MEM2_RMD(31:16)

MEM2_RMAA(0)

MEM2_RMAA(3)

MEM2_RBS0

MEM2_RBS1

MEM2_RSCASA*

MEM2_CKE2

MEM2_CSA2*

MEM2_RSRASA*MEM2_RSRASA*

MEM2_RSWEA*

MEM2_RMAA(12:6)

MEM2_MAB(5:4)

MEM2_MAB(2:1)

MEM2_RDM(1)

MEM2_RDM(0)

MEM2_RDQS(1)

MEM2_RDQS(0)

MEM2_CSA2*

CLK2_MCLK3*

MEM2_CKE2

MEM2_RMD(15:0)

MEM2_RMAA(0)

MEM2_RMAA(3)

MEM2_RBS0

MEM2_RBS1

MEM2_RSCASA*

MEM2_RMAA(0)

MEM2_RMAA(3)

MEM2_RBS0

MEM2_RBS1

MEM2_RSCASA*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-12

5-1-1(k) System Main Board Schematic Sheet 12 of 40(DDR-SODIMM)

P/N : 3709-001193

SMBUS Addr : 1010000X

MEM2_CSA0*

MEM2_CSA1*

MEM2_BS0

MEM2_BS1

MEM2_SWEA*

MEM2_SCASA*

MEM2_SRASA*

SMB3_CLK

SMB3_DATA

MEM2_MAA(0)

CLK2_MCLK0

CLK2_MCLK0*

CLK2_MCLK1

CLK2_MCLK1*

MEM2_CKE0

MEM2_CKE1

MEM2_MD(63:0)

MEM2_DM(7:0)

MEM2_DQS(7:0)

MEM2_MAA(2:1)

MEM2_MAA(3)

MEM2_MAA(5:4)

MEM2_MAA(12:6)

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-13Sens Q 20

5-1-1(l) System Main Board Schematic Sheet 13 of 40(SERIES & TERMINATION)

SODIMM Pad

Rs

Vtt

L2

: CHECK BITS FOR ECC

SDQS[8:0]

L4 Rt

On Board

GMCH

L3L1

: DATA BUS

SDQ[71:64]

: DATA STROBE

SDM[8:0] : DATA MASK

DATA Signal Routing Topology

SDQ[63:0]

MEM2_RMD(63:0)

MEM2_RDQS(7:0)

MEM2_MD(63:0)

MEM2_RMD(63:0)

MEM2_DQS(7:0) MEM2_RDQS(7:0)

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-14

5-1-1(m) System Main Board Schematic Sheet 14 of 40(SERISE & TERMINATION)

SODIMM 0 Pad / On Board

Control Signal Routing Topology

SMA[12:6,3,0], SBS[1:0], RAS*, CAS*,WE*

L2

CPC signals

Place one 0.1uF cap and one 0.01uF colse to every 4 pull-up resistors terminated to Vcc1_25.

L3 L4

Rt

On Board

L2

Rt

SODIMM 0 Pad

L1

Rs

GMCH

Place 1 Cap close to every 2 pullup resisters terminated to +V1.25

Vtt

GMCH

Command Signals

L1

Command Signal can not be placed within the R-packs as data, strobe or control signals

SCKE[3:0], SCS#[3:0]

SMB[5,4],[2,1]

Vtt

SMA[5,4],[2,1]

MEM2_MAA(1)

MEM2_MAA(2)

MEM2_MAA(4)

MEM2_MAA(5)

MEM2_RMAA(12:0)

MEM2_CSA0*

MEM2_CSA2*

MEM2_CSA1*

MEM2_CKE0

MEM2_CKE1

MEM2_CKE2

MEM2_RBS0

MEM2_RSCASA*

MEM2_RSRASA*

MEM2_RBS1

MEM2_RSWEA*

MEM2_MAA(12:0) MEM2_RMAA(12:0)

MEM2_RBS0

MEM2_RBS1

MEM2_RSWEA*

MEM2_RSCASA*

MEM2_RSRASA*

MEM2_BS0

MEM2_BS1

MEM2_SWEA*

MEM2_SCASA*

MEM2_SRASA*

MEM2_RDM(7:0)MEM2_DM(7:0)

MEM2_MAB(4)

MEM2_MAB(5)

MEM2_MAB(1)

MEM2_MAB(2)

MEM2_RDM(7:0)

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-15Sens Q 20

5-1-1(n) System Main Board Schematic Sheet 15 of 40(ICH4-M)

RESUME POWER WELL : GPIO25, GPIO27, GPIO28

350mV +/- 8%

Hub I/F : Route Signal with 5/20 trace/space routing.

PLACE RCOMP Resistor within 0.5" of ICH pad using thick trace

Signals must match +/- 0.1" of Strobe signals.

Place resistor near ICH4-m

near component

Checklist rev 0.91

RESUME POWER WELL : GPI8, GPI12, GPI13

Checklist rev0.94

MAIN POWER WELL : GPO16,GPO17

RCOMP R should be 2/3 board impedance

800mV +/- 8%

SET ALL UNUSED GPIO PINS TO GPO

near divider

near divider

near component

LAN3_TXD1

LAN3_TXD2

LAN3_PHYRST

KBC3_LAN_PWROK

CHP3_SMLINK0

CHP3_SMLINK1

CHP3_PME*

CHP3_DCKIN*

CHP3_IRQH*

PCI3_INTE*

PCI3_INTF*

CHP3_INTRUDER*

AGP3_BUSY*

KBC3_A20G

LCD3_LAMPSTAT

CHP3_DBAY_MODPRES*

HUB1_HVSWING

HUB1_REF_ICH

CLK3_PCLKICH

CHP3_DBAY_MODPRES*

LAN3_PHYCLK

LAN3_RXD0

LAN3_RXD1

LAN3_RXD2

LAN3_TXD0

PCI3_INTF*

PCI3_INTE*

CHP3_IRQH*

PCI3_CLKRUN*

AGP3_BUSY*

PCI3_GNT0*

PCI3_GNT1*

PCI3_GNT2*

HUB1_HVSWING

HUB1_REF_ICH

CHP3_SMLINK0

CHP3_SMLINK1

KBC3_IMVP4_PWRGD

CHP3_BATLOW*

CHP3_INTRUDER*

PCI3_GNT1*

PCI3_GNT2*

PCI3_RSTF*

PCI3_RST*

ISA3_IRQ(14)

ISA3_IRQ(15)

PCI3_PAR

PCI3_CLKRUN*

PCI3_IRDY*

PCI3_TRDY*

PCI3_INTB*

PCI3_INTC*

PCI3_INTD*

PCI3_PERR*

PCI3_PLOCK*

PCI3_REQ0*

PCI3_REQ1*

PCI3_REQ2*

PCI3_REQ3*

PCI3_INTA*

PCI3_FRAME*

PCI3_REQ4*

CHP3_SERIRQ

PCI3_DEVSEL*

KBC3_EXTSMI*

KBC3_RUNSCI*

KBC3_WAKESCI*

CPU1_SMI*

CPU1_STPCLK*

CPU1_DPSLP*

CPU1_PWRGDCPU

HUB1_HL(0:10)

HUB1_STB

HUB1_STB*

PCI3_INTA*

PCI3_INTB*

PCI3_INTC*

PCI3_INTD*

ISA3_IRQ(14)

ISA3_IRQ(15)

CHP3_SERIRQ

PCI3_GNT0*

PCI3_REQ0*

PCI3_REQ1*

PCI3_REQ2*

PCI3_REQ3*

PCI3_REQ4*

CHP3_BATLOW*

CHP3_CPUSTP*

CHP3_PCISTP*

PCI3_STOP*

PCI3_SERR*

PCI3_AD(31:0)

PCI3_CBE0*

PCI3_CBE1*

PCI3_CBE2*

PCI3_CBE3*

PCI3_DEVSEL*

PCI3_FRAME*

PCI3_IRDY*

PCI3_PAR

PCI3_PLOCK*

PCI3_SERR*

PCI3_STOP*

PCI3_TRDY*

GPIO16

PCI3_RSTF*

PCI3_PERR*

CHP3_PME*

KBC3_A20G

CPU1_A20M*

CPU1_FERR*

CPU1_IGNNE*

CPU1_INIT*

CPU1_INTR

CPU1_NMI

KBC3_CPURST*

CPU1_SLP*

CHP3_DCKSTS

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-16

5-1-1(o) System Main Board Schematic Sheet 16 of 40(ICH4-M)

Function

EEP_DOUT

256MB

No Stuff

128MB

On Board Memory Size

ICH4-m Strapping Options

PC/PCI GNTA*

ICH_SPKR

AC97_SDOUT

Default

No Stuff

No Stuff

A16 swap override

Safe Mode

No Stuff

No Reboot

Reserved

SMB3_ALERT*

CLK3_ICH14

USB3_P5+

GPIO16

LCD3_LAMPSTAT

KBC3_SUSPEND

USB_OC0*

SMB3_DATA CHP3_SMLINK1

SMB3_CLK

USB_OC1*

USB_OC0*

USB_OC1*

CLK3_ICH66

CHP3_SMLINK0

CHP3_OVERT*

CHP3_CRISIS*

CHP3_CRISIS*

USB3_P3+

HDD5_D(0:15)

LPC3_LAD(0:3)

CHP3_SPKR

CHP3_AC97_SDO

CHP3_BIOSWP*

CHP3_BIOSTBL*

CHP3_IVTPWRON

CHP3_1394_ROMW*

CHP3_BKLTON

USB3_P4-

USB3_P4+

USB3_P5-

CHP3_SLPS1*

CPU1_THRMTRIP*

CHP3_SLPS3*

SMB3_DATA

CHP3_SUSCLK

SMB3_CLK

CHP3_SUSSTAT*

CHP3_SPKR

KBC3_RSMRST*

USB3_P0-

USB3_P0+

USB3_P1-

USB3_P1+

USB3_P2-

USB3_P2+

USB3_P3-

HDD5_DACK*

HDD5_DREQ

HDD5_IOR*

HDD5_IOW*

HDD5_IORDY

CHP3_SLPS5*

KBC3_PWRGD

CHP3_RTCRST*

CHP3_VBIAS

CHP3_RTCX1

CHP3_RTCX2

CHP3_AC97_SDO

CHP3_AC97_BCLK

CHP3_AC97_SYNC

CHP3_AC97_RST*

CHP3_AC97_SDI1

CHP3_AC97_SDI0

CLK3_ICH48

CHP3_SLPS4*

CHP3_DPRSLPVR

LPC3_LDRQ0*

LPC3_LFRAME*

HDD5_A0

HDD5_A1

HDD5_A2

HDD5_CS1*

HDD5_CS3*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-17Sens Q 20

5-1-1(p) System Main Board Schematic Sheet 17 of 40(ICH4-M)

100nF *4

Vcc 1.5*8, VccPLL, Vcc H1

P1.5V

100nF *5, 4.7uF *1P3.3V_AUX VccSUS 3.3, VccLAN 3.3

100nF *5 10nF*1

VccSus 1.5, VccLAN 1.5

P3.3V

PRTC_BAT:Can drop to 2.0V(min)

RTC_Battery

Vcc 3.3

P1.5V

Mobile Platform Design Checklist rev 0.91

100nF *6

Pins

CHP3_RTCX1CHP3_VBIAS

CHP3_RTCX2

CHP3_RTCRST*

CHP3_VBIAS

CHP3_RTCRST*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-18

5-1-1(q) System Main Board Schematic Sheet 18 of 40(FWH)

CHP3_BIOSTBL*

CHP3_BIOSWP*

CLK3_PCLKFWH

PCI3_RST*

CPU1_INIT*

LPC3_LAD(0:3)

LPC3_LFRAME*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-19Sens Q 20

5-1-1(r) System Main Board Schematic Sheet 19 of 40(LCD INTERFACE)

LCD CONNECTOR

CRT CONNECTOR

PHOTO_SMB3_CLK

PHOTO_SMB3_DATA

PCI3_RST*

VGA3_LCDVDDON

LCD5_BRIT

KBC3_BRIT

VGA3_DDCD

VGA3_DDCC

VGA3_HSYNC

VGA3_VSYNC

PHOTO_SMB3_DATA

PHOTO_SMB3_CLK SMB3_CLK

SMB3_DATA

KBC3_THERM_SMCLK

KBC3_THERM_SMDATA

VGA3_A0+

VGA3_A0-

VGA3_CLK+

VGA3_CLK-

VGA3_A2+

VGA3_A2-

VGA3_A1-

VGA3_A1+

CHP3_BKLTON

LID3_SWITCH*

VGA5_DDCD

VGA5_VSYNC

VGA5_HSYNC

VGA5_DDCC

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-20

5-1-1(s) System Main Board Schematic Sheet 20 of 40(CARDBUS & 1394)

-----------GND-----------

-----------GND-----------

---------TPAP0-----------

- It is better no divergence, no-via hole and short wire about IEEE1394 signals.

---------TPAN0-----------

---------TPBN0-----------

- IEEE1394 signals should be designed on outside layers of PCB

---------TPBP0-----------

1.86V

-----------GND-----------

- Place these coil near the connector ACAP.

Implement these ACAP to 5C591

PCI3_INTC*

CLK3_PCLKCB

PCI3_AD(19)

VBUSPWR

VBUSPWR

1394_TPB+

1394_TPA+

CHP3_1394_ROMW*

CB3_SPKR

PCI3_INTA*

CHP3_SERIRQ

PCI3_CBE1*

PCI3_CBE3*

PCI3_INTB*

PCI3_AD(0:31)

1394_TPB-

1394_TPA-

PCI3_CBE0*

KBC3_PWRGD

CHP3_PME*

PCI3_CLKRUN*

PCI3_CBE2*

PCI3_RST*

PCI3_DEVSEL*

PCI3_FRAME*

PCI3_GNT0*

PCI3_IRDY*

PCI3_PAR

PCI3_PERR*

PCI3_REQ0*

PCI3_SERR*

PCI3_STOP*

PCI3_TRDY*

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-21Sens Q 20

5-1-1(t) System Main Board Schematic Sheet 21 of 40(CARDBUS & 1394)

1

MemoryStick

1

1

10

0

Memory Card Detect Logic Table

MS_CD*

0

1

0

0

0

1

1

SmartMedia

Socket Frame

Inhibit

Inhibit

SD/MMC

0

0

SM_CD*

1

1

1

Inhibit

SD_CD*

Not Detected

0

1

0

0

Inhibit

1

0

CB3_VCC5EN*

CB3_VPPEN0

CB3_VPPEN1

SD_CD*

MS_INS*

MS_RSVR1

MS_RSVR2

MS_RSVR2

MS_RSVR1

CB3_FUNC1*

CB3_VCC3EN*

CB3_VCC5EN*

CB3_MDVCCEN*

CB3_CCBE1*

CB3_CCBE2*

CB3_CCBE3*

CB3_D14

CB3_D2

CB3_CDEVSEL*

CB3_CFRAME*

CB3_CGNT*

CB3_CINT*

CB3_CIRDY*

CB3_CPAR

CB3_CPERR*

CB3_CREQ*

CB3_CRST*

CB3_CSERR*

CB3_CSTOP*

CB3_CSTSCHG

CB3_CTRDY*

CB3_CVS1

CB3_CVS2

CB3_VCC3EN*

MCCCD*

CB3_FUNC0*

CB3_FUNC1*

CB3_FUNC0*

SD_CD*

CB3_VPPEN1

MCCCD*

CB3_A18

CB3_A19

CB3_CAUDIO

CB3_CCD1*

CB3_CCD2*

CB3_CCLKRUN*

CB3_CCBE0*

CB3_CRST*

CB3_CCD1*

CB3_CCD2*

CB3_VPPEN0

CB3_MDVCCEN*

CB3_CAD(0:31)

MS_INS*

CB3_CSTOP*

CB3_CDEVSEL*

CB3_CTRDY*

CB3_CFRAME*

CB3_CVS2

CB3_CRST*

CB3_CSERR*

CB3_CREQ*

CB3_CCBE3*

CB3_CAUDIO

CB3_CSTSCHG

CB3_CCD2*

CB3_CCLK

CB3_CCBE1*

CB3_CPAR

CB3_CPERR*

CB3_CGNT*

CB3_CINT*

CB3_CCLK

CB3_CIRDY*

CB3_CCBE2*

CB3_D2

CB3_CCLKRUN*

CB3_CCD1*

CB3_CCBE0*

CB3_D14

CB3_CVS1

CB3_A18

CB3_A19

This Document can not be used without Samsung’s authorization.

5-1-1(u) System Main Board Schematic Sheet 22 of 40(LOW [BCM5705M])

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-22

Note : All LAN signals should be 5~6mils.

Gemini Name

Aquila Name

LAN3_PHYRST

LAN3_RXD0

LAN3_RXD2

LAN3_PHYCLK

LAN3_RXD1

LAN3_ACT*

LAN3_RDN

LAN3_RDP

100M_LED*

LAN3_TDN

LAN3_TDP

KBC3_LAN_PWROK

LAN3_DCK_TX-

LAN3_DCK_TX+

LAN3_DCK_RX-

LAN3_DCK_RX+

KBC3_DCKIN*

LAN3_TDN

LAN3_TDP

LAN3_RDN

LAN3_RDP

10M_LED*

KBC3_LAN_PWROK

LAN3_TXD0

LAN3_TXD1

LAN3_TXD2

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

5-23Sens Q 20

5-1-1(v) System Main Board Schematic Sheet 23 of 40(LOW [BCM5705M])

CS4202

1~12, 44~48: Digital GND

Place near HP & MIC conn audio ground partition

13~43 Analog GND

MDC connector

MIC In

CD5_L

CD5_R

CD5_COM

AUD5_CDL

AUD5_CDR

AUD5_CDCOM

AUD5_VREFOUT

LINE_OUT_R

LINE_OUT_L

AUD3_SPDIF

CHP3_AC97_BCLK

CHP3_AC97_SDI0

AUD3_MONO_OUT

AUD3_SPKR

AUD_MIC_CODEC

AUD5_PHONE

AUD5_CDCOM

AUD5_CDL

AUD5_CDR

CHP3_SPKR

CB3_SPKR

AUD3_SPKR

AUD3_PHONE

AUD_MIC_CODEC

AUD3_PHONE AUD5_PHONE

CHP3_AC97_RST*

CHP3_AC97_SDO

CHP3_AC97_SYNC

This Document can not be used without Samsung’s authorization.

5 System Schematic Diagrams and PCB Silkscreen

Sens Q 205-24

5-1-1(w) System Main Board Schematic Sheet 24 of 40(AUDIO)

Min 15mil

HEADPHONE

HP_IN

AUD5_SHUTDOWN

HP_IN

DCK5_LINE_OUT_R

DCK5_LINE_OUT_L

DCK5_SPKR_MUTE

KBC3_SPKMUTE

CHP3_DCKIN*

AUD5_VREFOUT

AUD5_LINE_OUT_R

LINE_OUT_R

AUD5_LINE_OUT_L

LINE_OUT_L

AUD5_SHUTDOWN

HP_IN

AUD5_LINE_OUT_R

AUD5_LINE_OUT_L

AUD5_LINE_OUT_L

AUD5_LINE_OUT_R

This Document can not be used without Samsung’s authorization.