Samsung PL42C91 Diagram

Schematic Diagram

Samsung Electronics 7-1

7. Schematic Diagram

7-1 Circuit Description

■ SMPS Board The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VAoutputs, a LLC converter has been used. For the other outputs, a Flyback converter has been used.

■ LOGIC Board The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC.

- LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip.

- Outputs the address Drive IC control and data signals to the Buffer Board.

- Outputs the control signal for the X and Y Drive Boards.

- Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects the Drive Circuit.

- Temperature Adaptive Operating Mode (Low Temperature/Room Temperature/High Temperature); Discharge optimization for each temperature level.

■ X-MAIN Board Connects to the X terminal block, 1) provides maintaining voltage waveform (including ERC), and 2) maintains the Ve bias in the Scan section.

■ Y-MAIN Board Connects to the Y terminal block, 1) provides maintaining voltage waveform (including ERC), 2) provides YRising, Falling Ramp waveforms, and 3) maintains the Vscan bias.

■ Address Buffer Board It delivers the data signal and control signal to the TCP.

LVDS

Recever

Input Data

Processor

LVDS Trans

Image Scaler

TMDS

Logic Board

Data

Controller

Main Board

Image

Enhancer

CPU

Decoder

A/D

Converter

DRAM

Driver

Timing

Controller

Deinterlacer

Video

Decoder

Video

S/W

Display

Data

Display

Timing

Scan

Timing

Audio

Processor

Speaker

Out

Micom

Y Main Board

Y-Pulse

Generator

Tune r

Row

Driver

RF

Splitter

PDP Panel

42” - 1024x768 Pixels 1024x768x3 Cells (R,G,B) 50” - 1360x768 Pixels 1360x768x3 Cells (R,G,B)

Address Buffer

SMPS Board

Main SMPS

X Main Board

X-Pulse

Generator

AC Power

Source

7-2 Samsung Electronics

MEMO

Samsung Electronics

Schematic Diagram

7-3

A

This Document can not be used without Samsung’s authorization.

7-2 Schematic Diagram

Power

Vidoe Audio

7-2-1 POWER_ETC

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Schematic Diagram

7-4 Samsung Electronics

This Document can not be used without Samsung’s authorization.

7-2-2 INPUT_JACK1

Power

Vidoe Audio

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52R

CDS3C30GTH

P

O_362R

mho0

PO_

k7.4 : U

4

5

1 3

GND

2 7

6

1

402AJ

NI

GA

_DN

mhoK74

W01/1

NI_DNGA

8

2C

22C

D223

D224

CDS3C30GTH

A

NI_DNG

UE_522D

11-ET-B6.5ZLR

12

462R

mho57

2(m

ho

1VA_TN

EDI

92

Fp001

UE_062R

332C

Fp74

NI_DNGA

)070000-7002(mho0 : TN

4

80000-700

)

TUPNI_1VA

TUPNI_1PMOC

D202

D201

502C

CDS3C30GTH

p00

F

1

2R

A

I_DNG

312PT

1

T

P

412

1

112U

03

2C

01

mho0

12D

3SDC

NI_DNGAN

mhoK1

352R

mhoK1

552R

132C

Fp00

1

Fp0

NI_DNGA

9

52R

262R

mhoK1

702R

902R

602C

Fp001

NI_DNGA

412R

2R

81

1

mho00

12

W01/1

5

22R

mho001

82

W01/1

5

32R

mho001

8

32R

W

1

01/

142

R

N

NA_

ecivreS

5

42

R

2R

64

8

D

HTG03C

I

_DNGA

2R

mho001

25

7

mho001

42R

S

602Q

K

Y-3261CS

mho001

4

mho7

UE_232C

001

Fp

NI_DNGA

OC

mhoK1

mho00

1

W4/1

mho74

05

902C

W

4/1

mho74

01

512C

W4/1

mho74

2C

12

mho74

C

NI_RS_1PM

NI

_L

C

S_1PMO

1

V

05

Fn01

702C

V

Fn01

V05

Fn

01

2C

31

V05

Fn

V05

Fn01

12C

9

V05

O

C

Fn01

Fn7.4

522

V0

5

PMOC_TNEDI

r

MOC_VTD

P_1P

D

NG_BP_1PMOC

bP

_1PMOC_VTD

DNG_RP_1PMOC

MOC

Y_1

_

P

VTD

Y

DNG

_1PM

_

GOS_

C

1PMO

Y

mho001

912

03C3SDC

HTG

NI_RS_1VA_2CS

Q

502

NI_LS_1VA_2C

C

R

652

B

1

mhoK

E

C

E

7

52R

B

mhoK1

NI

_DNGA

4D_2C

S

_

A_2CS

SBVC_V

SBVC_1VA_2CS

A

_ECIV

XR_YN

RES

E

I

R

XT_YNA_EC

S

V

A

TUO_LS_2CS_YN

TUO_RS_2CS_YNA

-3261CSK

Y

DI_3TNOC_

TUO

RP_2CS

O