Samsung MZ-7GE960EW User Manual
DATA SHEET
Ver. 1.1, June, 2014
SAMSUNG SSD 845DC EVO
Data Sheet, Ver. 1.1
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DATA SHEET
Ver. 1.1, June, 2014
Revision History
Revision No.
History
Date
Ver.1.0
Initial Release
May 2014
Ver.1.1
Content reorganized
June 2014
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DATA SHEET
Ver. 1.1, June, 2014
Table of Contents
Product Overview
Revision history
1. General Description .......................................................................................................................................................................... 5
2. Mechanical Specification ................................................................................................................................................................ 6
2.1 Physical dimensions and Weight........................................................................................................................................... 6
3. Product Specifications ..................................................................................................................................................................... 7
3.1 Interface and Configuration .................................................................................................................................. 7
3.2 Capacity ................................................................................................................................................................ 7
3.3 Performance .............................................................................................................................................................................. 7
3.3.1 Sequential Read/Write Bandwidth ................................................................................................................................ 7
3.3.2 Random Read/Write Input/Output Operations Per Second (IOPS)................................................................ 7
3.3.3 IOPS Consistency ................................................................................................................................................................ 7
3.3.4 Latency ........................................................................................................................................... ..................... 8
3.3.5 Quality of Service (QoS)...................................................................................................................................................... 8
3.4 Electrical Characteristics.......................................................................................................................................................... 9
3.4.1 Supply Voltage ................................................................................................................................................................. 9
3.4.2 Power Consumption ................................. ..................................... ............... ................................................................ 9
3.4.3 Power Loss Protection ............................................................................ ................................................... 9
3.5 Reliability .............................................................................................................. .............................. 10
3.6 Environmental Specifications ............................................................................................................................................. 10
4. Electrical Interface Specification ……………………………………………………………………………………………………………………………………… 11
4.1 Serial ATA Interface connector............................................................................................................................................... 11
4.2 Pin Assignments............................................................................................................................................................................ 11
5. Shadow Register Block registers Description ...........................................................................................................................12
5.1 Command Register........................................................................................................................................................................12
5.2 Device Control Register.............................................................................................................................................................. 12
5.2.1 Field / bit description .........................................................................................................................................................12
5.3 Device / Head Register............................................................................................................................................................... 12
5.3.1 Field / bit description .................................................................................................................................................………12
5.4 Error Register ..........................…………………………………………………………………………………………………………………………………………..12
5.4.1 Field / bit description …………………………………………………………..……………………………………….............................................12
5.5 Features Register ......................................................................................................................................................................... 12
5.6 Cylinder High (LBA High) Register ......................................................................................................................................... 13
5.7 Cylinder Low (LBA Mid) Register ............................................................................................................................................ 13
5.8 Sector Number (LBA low) Register ....................................................................................................................................... 13
5.9 Sector Count Register ................................................................................................................................................................ 13
5.10 Status Register ........................................................................................................................................................................... 13
5.10.1 Field / bit description .......................................................................................................................................................13
6. Command Descriptions......................................................................................................................................................................14
6.1 Supported ATA Commands……………………………………………………………………………………………………………………………………….….14
6.2 SECURITY FEATURE Set ............................................................................................................................................................ 15
6.2.1 SECURITY mode default setting.................................................................................................................................... 15
6.2.2 Initial setting of the user password............................................................................................................................... 15
6.2.3 SECURITY mode operation from power-on.............................................................................................................. 15
6.2.4 Password lost......................................................................................................................................................................... 15
6.3 SMART FEATURE Set (B0h) …………………………………………………………………………………………………………………………………………. 15
6.3.1 Sub Command ..................................................................................................................................................................... 15
6.3.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h)............................................................................... 15
6.3.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h) ..................................................................... 15
6.3.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (subcommand D2h) ................................................... 15
6.3.1.4 S.M.A.R.T. Save Attribute Values (subcommand D3h) .............................................................................. 16
6.3.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h) ...........................................................……..16
6.3.1.6 S.M.A.R.T. Selective self-test routine ................................................................................................................ 16
6.3.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h)...........................................................................................18
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6.3.1.8 S.M.A.R.T. Write Log Sector (subcommand D6h)..........................................................................................18
6.3.1.9 S.M.A.R.T. Enable Operations (subcommand D8h) ……………………………………………………………………………..18
6.3.1.10 S.M.A.R.T. Disable Operations (subcommand D9h) .................................................................………………18
6.3.1.11 S.M.A.R.T. Return Status (subcommand DAh) ........................................................................................….18
6.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh) ................................................. 19
6.3.2 Device Attribute Data Structure.......................................................................................................................................... 19
6.3.2.1 Data Structure Revision Number ...................................................................................................................... 19
6.3.2.2 Individual Attribute Data Structure .................................................................................................................. 19
6.3.2.3 Off-Line Data Collection Status .......................................................................................................................... 21
6.3.2.4 Self-test execution status...................................................................................................................................... 21
6.3.2.5 Total time in seconds to complete off-line data collection activity .................................................... 21
6.3.2.6 Current segment pointer ...................................................................................................................................... 21
6.3.2.7 Off-line data collection capability ………………………………………………………………………………………………………….. 21
6.3.2.8 S.M.A.R.T. Capability ................................................................................................................................................ 22
6.3.2.9 Error logging capability ......................................................................................................................................... 22
6.3.2.10 Self-test failure check point.............................................................................................................................. 22
6.3.2.11 Self-test completion time ................................................................................................................................. 22
6.3.2.12 Data Structure Checksum.................................................................................................................................. 22
6.3.3 Device Attribute Thresholds data structure .................................................................................................................. 22
6.3.3.1 Data Structure Revision Number ……………………………………………………………………………………………………………. 22
6.3.3.2 Individual Thresholds Data Structure............................................................................................................... 22
6.3.3.3 Attribute ID Numbers ............................................................................................................................................. 22
6.3.3.4 Attribute Threshold ................................................................................................................................................. 23
6.3.3.5 Data Structure Checksum..................................................................................................................................... 23
6.3.4 S.M.A.R.T. Log Directory …………………………………………………………………………………………………………………………………………… 23
6.3.5 S.M.A.R.T. error log sector ……………………………………………………………………………………………………………………………………….. 23
6.3.5.1 S.M.A.R.T. error log version ………………………………………………………………………………………………………………………. 23
6.3.5.2 Error log pointer ....................................................................................................................................................... 23
6.3.5.3 Device error count .................................................................................................................................................. 23
6.3.5.4 Error log data structure ......................................................................................................................................... 23
6.3.5.5 Command data structure ..................................................................................................................................... 23
6.3.5.6 Error data structure.................................................................................................................................................. 25
6.3.6 Self-test log structure ................................................................................................................................................ 25
6.3.7 Selective self-test log data structure ………………………………………………………………………………………………………… 25
6.3.8 Error reporting .............................................................................................................................................................. 26
7. OOB signaling and Phy Power State ............................................................................................................................................ 27
7.1 OOB signaling ................................................................................................................................................................................ 27
7.1.1 OOB signal spacing ............................................................................................................................................................. 27
7.2 Phy Power State............................................................................................................................................................................ 27
7.2.1 COMRESET sequence state diagram .......................................................................................................................... 27
8. SPOR Specification(Sudden Power Off and Recovery) ........................................................................................................ 28
8.1. Data Recovery in Sudden Power Off..................................................................................................................................... 28
8.2 Time to Ready Sequence........................................................................................................................................................... 28
9. SATA II Optional Feature.................................................................................................................................................................... 29
9.1 Asynchronous Signal Recovery............................................................................................................................................... 29
9.2 Power Segment Pin P11 ........................................................................................................................................................... 29
9.3 Activity LED indication ............................................................................................................................................................... 29
10. Product Compliance......................................................................................................................................................................... 30
10.1 Product Regulatory compliance and Certifications .................................................................................................... 30
11. Identify Device Data ........................................................................................................................................................................ 31
12. Product Line up ................................................................................................................................................................................. 33
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Ver. 1.1, June, 2014
1. General Description
845DC EVO
Capacity
240GB, 480GB, 960GB
Application
Mixed and Read-centric applications are recommended
Dimensions (LxWxH)
(100.20±0.25) x (69.85±0.25) x (6.80±0.20) mm
Weight
Max. 63g (960GB)
Interface
Serial ATA 6Gb/s (compatible with SATA 3Gb/s and SATA 1.5Gb/s)
Fully complies with ATA/ATAPI-7 Standard(Partially Complies with ATA/ATAPI-8)
Support NCQ : Up to 32 depth
Form Factor
2.5” type
Controller
Samsung 3-core MEX controller
NAND Flash Memory
Samsung 19nm Toggle 3bit MLC NAND
DRAM Cache memory
256MB (240GB), 512MB (480GB), 1GB (960GB)
Performance*
Sequential Read:
Up to. 530 MB/s
Sequential Write:
Up to. 410 MB/s (480GB, 960GB)
Up to. 270 MB/s (240GB)
Random Read (4KB, QD32):
Max. 87,000 IOPS
Random Write (4KB, QD32):
Max. 14,000 IOPS(480GB, 960GB)
Max. 12,000 IOPS(240GB)
Quality of Service
(4KB, QD32)
99.99%
Read: 0.6ms
Write: 7ms
Max.
Read: 3ms
Write: 8ms
Latency
(4KB, QD1)
Sequential
Read :55 us Write : 45us
Random
Read :115us Write : 55us
Reliability
- Mean Time Between Failures (MTBF) : 2,000,000 hours
- Uncorrectable Bit Error Rate (UBER) : 1 sector per 10
17
bits read
- End-to-end data protection
TBW
240GB : 150TBW
480GB : 300TBW
960GB : 600TBW
Power Consumption
Active Read/Write : 3.1 Watt/4.2Watt
Idle : 1.5 Watt
Temperature
Operating:
Non-Operating:
0°C to 70°C
-40°C to 85°C
Humidity
5% to 95%, non-condensing
Vibration
Non-Operating:
20~2000Hz, 20G
Shock
Non-Operating:
1500G , duration 0.5m sec, 3 axis
Certification
CE, BSMI, KCC, VCCI, C-tick, FCC, IC, UL, TUV, CB
RoHS compliance
ROHS2
Warranty
5 years limited
Samsung SSD 845DC EVO is designed for server and data centers delivering an exceptionally high
performance, consistent low latency and outstanding reliability. With the addition of Tantalum capacitors,
crucial data is protected from corruption due to power loss more than ever before. The 845DC EVO provides
a state-of-the-art yet cost-effective solution for today’s increasing data traffic.
* Actual performance may vary depending on use conditions and environment
1. Performance measured using FIO with queue depth 32
2. Measurements are performed on whole LBA range
3. Write cache enabled
4. 1MB/sec = 1,048,576 bytes/sec was used in sequential performance
5. Uncorrectable Bit Error Rate (UBER) and Endurance (TBW) is based on JEDEC standard.
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Ver. 1.1, June, 2014
2. Mechanical Specification
Model Name
Height
Width
Length
Weight
MZ-7GE240
MZ-7GE480
MZ-7GE960
6.80±0.20
69.85±0.25
100.20±0.25
Max. 63g
2.1 Physical dimensions and Weight
※ For the thickness size(height), drive label thickness was included
[Figure 2-1] Physical dimension
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Ver. 1.1, June, 2014
3. Product Specifications
MZ-7GE240
MZ-7GE480
MZ-7GE960
Unformatted Capacity
240 GB
480 GB
960 GB
User-addressable Capacity
(Number of sectors)
468,862,128
937,703,088
1,875,385,008
Byte per Sector
512 Bytes
Sequential (128KB, MB/s)
Model Name
MZ-7GE240
MZ-7GE480
MZ-7GE960
Read
530
530
530
Write
270
410
410
4KB Random (IOPS)
MZ-7GE240
MZ-7GE480
MZ-7GE960
QD 32
Read IOPS
87,000
87,000
87,000
Write IOPS
12,000
14,000
14,000
QD 1
Read IOPS
8,000
8,000
8,000
Write IOPS
12,000
14,000
14,000
8KB Random (IOPS)
MZ-7GE240
MZ-7GE480
MZ-7GE960
QD 32
Read IOPS
55,000
55,000
55,000
Write IOPS
6,000
7,000
7,000
QD 1
Read IOPS
7,000
7,000
7,000
Write IOPS
3,000
5,000
5,000
3.1 Interface and Configuration
Burst read/write rate is 600 MB/sec (6Gb/s).
Fully compatible with ATA-7 Standard
(Partially Complies with ATA/ATAPI-8)
3.2 Capacity
※ 1 Megabyte (MB) = 1 Million bytes; 1 Gigabyte (GB) = 1 Billion bytes
Actual usable capacity may be less due to formatting, partitioning, operating system, application and otherwise.
3.3 Performance
3.3.1 Sequential Read/Write Bandwidth
3.3.2 Random Read/Write Input/Output Operations Per Second (IOPS)
※ Actual performance may vary depending on usage conditions and system environment.
1. Performance measured FIO with queue depth 32
2. Measurements are performed on whole LBA range
3. Write cache enabled
4. 1MB/sec = 1,048,576 bytes/sec was used in sequential performance
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3.3.3 IOPS Consistency
4KB
MZ-7GE240
MZ-7GE480
MZ-7GE960
Random Read (%)
QD1
95
95
95
QD32
99
99
99
Random Write (%)
QD1
85
85
85
QD32
90
90
90 8KB
MZ-7GE240
MZ-7GE480
MZ-7GE960
Random Read (%)
QD1
95
95
95
QD32
99
99
99
Random Write (%)
QD1
90
90
90
QD32
90
90
90
MZ-7GE240
MZ-7GE480
MZ-7GE960
Read (us)
Typical 4KB Random
110
115
115
Typical Sequential
55
55
55
Write (us)
Typical 4KB Random
50
55
55
Typical Sequential
45
45
45
QD1
MZ-7GE240
MZ-7GE480
MZ-7GE960
Read
Write
Read
Write
Read
Write
99.9%
(ms)
4KB
0.2
0.4
0.2
0.4
0.2
0.4
8KB
0.2
0.6
0.2
0.6
0.2
0.6
Max (99.9999%)
(ms)
4KB
1 1 1 1 1 1 8KB
1
1.5 1 1.5 1 1.5
QD32
MZ-7GE240
MZ-7GE480
MZ-7GE960
Read
Write
Read
Write
Read
Write
99.9%
(ms)
4KB
0.6 7 0.6 7 0.6 7 8KB
1
10 1 10 1 10
Max (99.9999%)
(ms)
4KB
3 8 3 8 3
8
8KB
5
15 5 15 5 15
※ IOPS Consistency [%] = (99.9% IOPS)/(Average IOPS) x 100
3.3.4 Latency
※ Latency is measured using 4KB transfer size with Queue Depth 1.
3.3.5 Quality of Service (QoS)
Quality of Service (QoS) is the level of quality that provides steady and consistent performance given as a
maximum response time under the certain confidence level of 99.9% or 99.9999%.
※ Actual performance may vary depending on usage conditions and system environment.
Test condition: Intel® i3-3240 3.40GHz, 4GB DDR3-1600, Intel C216 Family Chipset
RedHat Enterprise Linux 6.4 with AHCI (ver.9.3.0.1011)
Test program: FIO 2.1.3
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3.4 Electrical Characteristics
Characteristics
Requirements
Allowable voltage
5V ± 5%
Allowable noise/ripple
100mV p-p or less
Rise time (Max./Min.)
1s / 1ms
Fall time
500ms
Inrush current (Typical Peak)
1.5A, <1s
MZ-7GE240
MZ-7GE480
MZ-7GE960
Active Read
(Watt)
Average
3.1
3.1
3.1
Burst
3.1
3.1
3.1
Active Write
(Watt)
Average
3.1
4.1
4.2
Burst
3.4
4.4
4.8
Idle (Watt)
1.0
1.5
1.5
MZ-7GE240
MZ-7GE480
MZ-7GE960
Number of Capacitors
14
21
23
Capacitance
1.4mF
2.1mF
2.3mF
Discharging time
Min 35ms
3.4.1 Supply Voltage
※ The 845DC EVO needs only 5V power rail, and the 12V power pin of a SATA connector is not connected to any
net and components in the 845DC EVO.
If both 12V and 5V power rails are provided to the SSD, the SSD would work well.
If only 5V power rail is provided to the SSD, the SSD would work well.
If only 12V power rail is provided to the SSD, the SSD would not work, but this won’t bring any problems to host
system.
3.4.2 Power Consumption
3.4.3 Power Loss Protection (PLP)
Samsung 845DC EVO SSD is built with tantalum capacitors to protect all data in the write cache in case
of a power failure. On detection of the external power loss, the SSD uses the electricity from a tantalum
capacitor to transfer the cached data in DRAM to the flash memory.
This enterprise-grade PLP provides an added level of security to ensure that valuable write information is
well protected against data corruption caused by sudden power loss.
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3.5 Reliability
MZ-7GE240
MZ-7GE480
MZ-7GE960
Mean Time Between Failures (MTBF)
2,000,0000 Hours
Uncorrectable Bit Error Rate (UBER)
1 sector per 10^17 bits read
Endurance(TBW)
150TBW
300TBW
600TBW
Data Retention
3 months (@40℃)
Power on/off cycle
24 per Day
Insertion cycle
500 cycles
Features
Operating
Non-Operating
Temperature
0℃ to 70℃
-40℃ to 85℃
Humidity
5% to 95%, non-condensing
Vibration
1~2KHz, 20Grms, 20min/3-axis
Shock
1500G with 0.5ms duration
※ Refer to JESD218 standard table 1 for requirements of enterprise SSD reliability.
3.6 Environmental Specifications
※ Notes :
1. Temperature specification is following JEDEC standard; Expressed temperature must be measured right on
the case.
2. Humidity is measured in non-condensing.
3. Shock test condition: 0.5ms duration with half sine wave.
4. Vibration test condition: 10Hz to 2,000Hz, 15mins/axis on 3axis(X,Y,Z)
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