SAMSUNG Max945 Special Circuit Descriptions

Page 1

Circuit Descriptions

4. Circuit Descriptions

4-1 RF

4-1-1 RIC1 (KS1461)

KS1461 is combined with KS1452 and KS1453 as bipolar IC developed for DVD SERVO system. Main features include DVD waveform equalizing, CD waveform equalizing, focus error signal generation, 3-beam tracking error signal generation, DPD 1-beam tracking error, defect, envelope, MIRR output, etc. after receiving the pick-up output converted into I/V.

4-2-1 (a) Basic Potentiometer

KS1461 uses a single power method and each circuit is based on V of 2.5V. V (Pin 12, 20, 24, 67) terminal is needed for IC, which uses the peripheral V.

4-2-1(b) RF signal

Fig. 4-1shows the flow of signal generated by the pick-up. A, B, C, D signals detected from pick-up are converted in to RF signal(A+B+C+D) via RF summing AMP.

104

PICK-UP

RFAGCO EQIN

104

B C

EFLDPD

104

5 6 7 8

13 14

15 16 17 18

RE SUM

& AGC

DPD

ABCD

SUM

474

TESEL

Mhx

ENV

FOK

DEFECT

MIRRI

RF EG

MIRR

39 43

46 55 54 33

MIRR

RFEQO

ABCDI

103

ABCD

ENV FOKB

DFCT2 DFCT1

28 29

ALPC

Fig. 4-1

Fig. 4-2 shows the waveform-equalizing block diagram for the RF signal. It outputs to EQout (Pin 86) terminal by initially changing switching AMPgain of DVD and CD, and then adjusting the level in RF SUM & AGC. It controls RF SUM & AGC gain by means of Pin 89-95 and interfaces with PWM signal, (output from PWM terminal of KS1453, via low-pass filter to adjust boost gain and peak frequency. EQout terminal is connected with EQin (Pin 86).

Samsung Electronics 4-1

Page 2

Circuit Descriptions

474

REAGCO 8

The control parameters of DVD EQ and CD EQ are as follows.

9 RFEQO

EQIN

RF EQ

EQG

Fig. 4-2

EQF

PWM1

PLLGF

PWM2

VZOCTL

VREFEQ

RFDVCC

1) DVD CD EQ control parameter

˛EQG (Pin 97) : Changes the gain of peak frequency with EQ frequency characteristic. Convert PWM signal,

output from KS1453, into DC via low-pass filter.

«EQF (Pin 98) : Changes the peak frequency with EQ frequency characteristic. Convert PWM signal, output

from KS1453, into DVD via low-pass filter.

4-2 Samsung Electronics

Page 3

Circuit Descriptions

Samsung Electronics 4-3

4-2 System Control

4-2-1 Outline

The main micom peripheral circuit is composed of 16bit Micom (MIC1 ; TMP93CM41F), 8M EPROM (MIC8 ; AM27C080) for Microcode and data save, 512 byte EE-PROM (MIC5 ; KS24C020) for permanent storage of data needed at power off, MIC4 (74AC573) to latch only address in the bus where address and data are mixed, address decoder (MIC7 ; 74HC00) for selection of ex-ternal device chip and 20MHz clock oscillator for micom operation. The Micom (MIC1 ; TMP93CM41F) mounted in main board analizes the key commands of front panel or instructions of remote control through communication with Micom (FIC1 ; LC86P6232) of front and controls the devices on board to execute the corresponding commands after initializing the devices connected with micom on board at power on.

4-2-2 Block Diagram

RIC1

RF AMP

KS1461

SIC1

DIGITAL SERVO

KS1452

VIC1

A/V DECODER

ZIVA-3

VIC50

VIDEO ENCODER

SAA7128/7120

AIC1,2,3,4

D/A CONVERTER

AK4324

DIC1

DATA PROCESSOR

KS1453

MIC2

ADDR LATCH

74AC573

MIC1 MAIN MICOM TMP93CM41F

MIC8

EPROM

AT27C080

MIC5

EEPROM

KS24C020

MICOM

BLOCK

HIGH ADDRESS

LOW ADDRESS

DATA BUS

UIC1

FRONT MICOM

LC86P6548

MIC7

ADDR DECODER

74HC00

Fig. 4-3

Page 4

Circuit Descriptions

4-4 Samsung Electronics

4-2-3 Waveform Description

When micom accesses each device sharing bus, it falls the chip select signal of corresponding chip to (CS2:MIC8-22, /DSPCS:DIC1-2, /DVDCS:VIC1-206/SRVCS:SIC1-10) 0 (Low) before trial. So to speak, the bus is used by time-division as shown in Fig 4-4, 4-5, 4-6. Two and more devices can't be accessed simultaneously.

• CH1 : CS2 (MIC8-22, EPROM CHIP SELECT)

• CH2 : DSPCS (DIC1-2, DATA PROCESSOR CHIP SELECT)

• CH3 : DVDCS (VIC1-206, A/V DECODER CHIP SELECT)

• CH4 : SRVCS (SIC1-10, DIGITAL SERVO CHIP SELECT)

• CH5 : WR (MIC1-73, MICOM OUTPUT WRITE SIGNAL)

• CH6 : RD (MIC1-72, MICOM OUTPUT READ SIGNAL)

/CS2

/DSPCS

/DVDCS

/SRVCS

/RD

/WR

Fig. 4-4

• CH1 : CS2 (MIC8-22, EPROM CHIP SELECT)

• CH2 : DSPCS (DIC1-2, DATA PROCESSOR CHIP SELECT)

• CH3 : DVDCS (VIC1-206, A/V DECODER CHIP SELECT)

• CH4 : SRVCS (SIC1-10, DIGITAL SERVO CHIP SELECT)

• CH5 : WR (MIC1-73, MICOM OUTPUT WRITE SIGNAL)

• CH6 : RD (MIC1-72, MICOM OUTPUT READ SIGNAL)

/CS2

/DSPCS

/DVDCS

/SRVCS

/RD

/WR

Fig. 4-5

Page 5

Circuit Descriptions

Samsung Electronics 4-5

• CH1 : CS2 (MIC8-22, EPROM CHIP SELECT)

• CH2 : DSPCS (DIC1-2, DATA PROCESSOR CHIP SELECT)

• CH3 : DVDCS (VIC1-206, A/V DECODER CHIP SELECT)

• CH4 : SRVCS (SIC1-10, DIGITAL SERVO CHIP SELECT)

• CH5 : WR (MIC1-73, MICOM OUTPUT WRITE SIGNAL)

• CH6 : RD (MIC1-72, MICOM OUTPUT READ SIGNAL)

/CS2

/DSPCS

/DVDCS

/SRVCS

/RD

/WR

Fig. 4-6

Page 6

Circuit Descriptions

4-3 Servo

4-3-1 Outline

SERVO system of DVD is divided into Focusing SERVO, Tracking SERVO, SLED Linked SERVO and CLV SERVO (DISC Motor Control SERVO).

1) Focusing SERVO Focuses the optical spot output from object lens onto the disc surface. Maintains a uniform distance between object lens of Pick-up and disc (for surface vibration of disc).

2) Tracking SERVO Make the object lens follow the disc track in use of tracking error signal (created from Pick-up).

3) SLED Linked SERVO When the tracking actuator inclines outwardly as the object lens follows the track during play, the SLED motor moves slightly (and counteracts the incline).

4) CLV SERVO (DISC Motor Control SERVO) Controls the disc motor to maintain a constant linear velocity (necessary for RF signal).

4-3-2 Block Diagram

SLED M/T

HALL

PCB

FOCUSING

TRACKING

DISC

SPINDLE M/T

CN1 HA1+ HA1– HA2– HA2+

SLED+ SLED–

AO DO CO BO

FO EO PD

F–

T+

T–

F+

SPINDLE

SIC8

NJM2903

5 6

11 12 18 17

1 2

KA3011D

DRIC2

KA3010D

DRIC1

MIC1

TMP 93CS41F

RIC1

KS1461

SIC1

KS1452

1 94

Fig. 4-7

4-6 Samsung Electronics

Page 7

Circuit Descriptions

Samsung Electronics 4-7

4-3-3 Operation

1) FOCUSING SERVO

(1) FOCUS INPUT

The focus loop is changed from open loop to closed loop, and the triangular waveform moves the object lens up and down (at pin 75 of SIC1 during Focus SERVO ON.) At that time, S curve is input to pin 65 of SIC1.

ABAD (pin 39 of RIC1) signal, summing signal of PD A, B, C, D, is generated, and zero cross(2.5V) point occurs when S curve is focused and ABAD signal exceeds a preset,constant value. The focus loop is changed to closed loop, and the object lens follows the disc movement, maintaining a constant distance from the disc. (these operations are same in CD and DVD).

Fig. 4-8

Vref

1.5V

Pin75 of SIC1 (FOD)

Pin65 of SIC1 (FEI)

Pin39 of RIC1 (ABCD)

(2) PLAY

When focus loop closes the loop during focus servo on, both pin 65 and pin 75 of SIC1 are controlled by VREF voltage (approx. 2.5V), and pin 1, 2 of DRIC2 are approximately 4.5V.

2) TRACKING SERVO

(1) NORMAL PLAY MODE

˛ For DVD

Composite : The signal output from PD A, B, C, D of Pick-up, the tracking error signal (pin36 of RIC1) uses the phase difference of A+C and B+D in RIC1, and inputs to terminal 64 of SIC1. Then, it is output to SIC1 pin 76 via

digital equalizer, and applied to the tracking actuator through DRIC2. Pins 17, 18 of SIC1 are controlled by VREF(approx. 2.5V) during normal play. Meanwhile, DVD repeats the track jump from 1 to 4 in inner direction at normal play (because data- read speed from disc is faster than data output speed on screen).

« For CD, VCD

Receive the signal output through E, F of Pick-up, from RIC1. The tracking error signal is similar to DVD.

Page 8

Circuit Descriptions

4-8 Samsung Electronics

(2) SEARCH Mode :

Search mode : Fine seek,(Moving the tracking actuator slightly little below 255 track) and coarse search, moving much in use of sled motor. The coarse search will be described in sled linked servo and now, the fine seek is explained shortly. If the object lens is located near target, cut off the tracking loop and give the control signal as many as desired count to move the tracking actuator via SIC1 pin 76 terminal(TRD).

3) SLED LINKED SERVO

¥ Normal play mode

Move SLED motor slightly by means of PWM signal in SIC1 pin 73, as the tracking actuator moves along with track during play. Control to move the entire Pick-up as the tracking actuator moves.

¥ Coarse serach mode

In case of long-distance search (such as chapter serach), SIC1 uses sled FG (SIC8 pin 1, 7, which is generated) by rotation of sled motor via hall PCB. Then, read ID and compute the existing track count after input of next track. If the existing track count is within fine seek range, tracking begins using fine seek.

4) CLV SERVO(DISC MOTOR CONTROL SERVO)

Input RF signal (from Pick-up) to SIC1 pin59. Detect SYNC signal from RF in SIC1, and output PWM signal to SIC1 pin 55 for constant linear velocity.

Page 9

Circuit Descriptions

Samsung Electronics 4-9

4-4 DVD Data Processor

4-4-1 Outline

DIC1(KS1453) performs Sync detection, EFM/EFM demodulation and error correction and Spindle motor control (CLV control) after inputting sliced EFM signal of RF signal at disc playback and EFM read clock (PLCK) signal generated from PLL. Outputs data which converted to the last audio and video from A/V decoder(VIC1). KS1453 uses external memory(4M DRAM) as buffer as well as for error correction and carries out Variable Bit Rate transfer function. VBR function uses the external buffer as buffer to absorb the difference of transfer rate occurring because the transfer rate of disc playback is faster than data transfer rate demanded by A/V decoder(Video/Audio Signal Process Chip). In case of general disc refresh, the memory is almost filled up periodically. It is because Write rate to memory after disc playback and signal process is faster than Read of A/V decoder. When the memory is filled, this status is reported by interrupt to main micom, which controls the servo to kick back the pick-up to the previous track after memorizing the last data read from disc until now. It takes some times to jump to the previous track and return to the original(jump location) again. The memory will have an empty space because A/V decoder reads out data of memory. When the memory has an empty space, where data can be processed and written and the pick-up correctly gets to the original location(before kick back location) again, it reads data again avoids the interrupt of data read previously. The basic operation repeats to perform as described above.

4-4-2 Block Diagram

Fig. 4-9

AD[7..0] HA[23..8] *WR(73)

INTO(ZIRQZD) INT4(/INT) *RD(72)

MIC1 TMP93CM41F

HDATA[7..0]

HADDR[3..0]

/CS

/RD /WR /INT

DVD-D[7..0] VSTROBE REQUEST DACK

*ERR

VIC1

(ZiVA-3)

192 191 196 200

177, 178

CLOCK 27MHz CLOCK 33.8688MHz CLOCK 27MHz

69 70

58 71 57

SDATA[7..0]

CSTROBE

DATREQ DATACK

DTER

TOS

OEW

C A S

R A S

[

D 1 5

. .

[

A 8

. .

[

D D 1 5

. .

[

D A D R 8

. .

Z R A S

Z C A S

MDAT[7:0]

MRZA(3)

ZCS(2)

MWR(128)

MRD(127)

ZIRQZD(126)

EFMI PLCK

116 104

109 110

MDP MDS

EFM PLCK

DIC1

(KS1453)

DIC2

(KM416C254)

Page 10

Circuit Descriptions

4-10 Samsung Electronics

4-4-3 Waveform Description

It measures the timing that data processed in DIC1 at DVD playback.

STROBE

REQ

DACK

SDATA all

220 1 0

Fig. 4-10

• CH1 : STROBE (DIC1-69, CLOCK)

• CH2 : REQ (DIC1-70, DATA REQUEST)

• CH3 : DACK (DIC1-58, DATA ACKNOWLEDGE)

• CH4 : SDATA (DIC1-60~67, DATA)

Page 11

Circuit Descriptions

Samsung Electronics 4-11

4-5 Video

4-5-1 Outline

VIC50 sends VSYNC and HSYNC from VIC1(A/V decoder) and receives 8bit video data. VIC50 does RGB encoding, copy guard processing and D/A conversion of 8bit video data inputted from VIC1(A/V decoder) by control of MIC1(Micom). Video signal converted into analog signal is outputted via amplifier of analog part.

(Main Board) (Output Board)

VIC1

A/V Decoder

ZiVA-3

MIC1

Main Micom

TMP93CM41F

Video

data

VIC50

SAA7128

Video

encoder

VIC52

Amplifier

BA7660

CVBS-1

Fig. 4-11 Video Output Block Diagram

Page 12

Circuit Descriptions

4-12 Samsung Electronics

4-5-2 NTSC/PAL Digital Encoder (VIC50 : SAA7128)

VIC50 inputted from pin4 with 27MHz generates HSYNC and VSYNC which are based on video signal. Each HSYNC and VSYNC outputted from Pin8 and Pin7 are inputted to Pin157 and Pin158 of A/V decoder VIC1(ZIVA-

3). VIC1 is the synchronous signals with the video signal and control the output timing of 8bit video signal of ITUR601 format. (Pin180, 182, 184 ~ 189 (MSP)) 8bit data is inputted to Pin9(MSB) and Pin16 of VIC50 and the inputted data is demuxed with each 8bit of Y/R-Y/BY. The separate signal is encoded to NTSC or PAL by control of MIC1. The above signals, that is CVBS (Composite Video Burst Synchronized)(Pin30), S-Video (Y:Pin27, C:Pin24), Y/Pb/Pr(Pin27/Pin29/Pin23) and GB(Pin26/Pin29/Pin23). In course of encoding, 8bit data can extend to 10bit or more. To convert the extended data to quantization noise as possible, VIC50 adopts 10bit D/A converter. VIC50 perform video en-coding as well as copy protection.

VDATA

[7:0]

VSYNC HSYNC 27M

MRST SDA SCL

9~16

7 8 4

40 42 41

Demultiplexer

CR-CB

RGB encoding

Luminace

processing

MACROVISION

7.0.1/6.1

Cloed captions

CGMS

Chrominance

processor

CTRL+CFG

Trap

10-bit DAC

CVBS

Cr/R

Cb/B

VIC1 (SSA7128)

Fig. 4-12

4-5-3 Amplifier (VIC51, VIC52 : BA7660)

VIC51 and VIC52 are 6dB amplifier. Based on CVBS signal, the final output level must be 2Vpp without 75ohm terminal resistance. Because the level of video encoder output is only 1.1Vpp, the level is adjusted with the special amplifier. When mute of pin1 is high active, if the pin is floating and connected to power, the output signal is never outputted. CVBS, Y, C, Cr and Cb outputted from video encoder are inputted to VIC52 (Pin7, Pin2 and Pin4) and VIC51 (Pin7 and Pin4) respectively and outputted from VIC52 (Pin10, Pin15 and Pin13) and VIC51 (Pin10 and Pin

13). Pin9, Pin12 and Pin14 of VIC51 and VIC52 are feedback pin to SAG compensation(DC characteristic compensation of signal). Resistance(VR3-VR14) which is inserted to input terminal is bias resistance for input offset. The signal to which gain is adjusted by amplifier is outputted from jack via 75ohm.

Page 13

Circuit Descriptions

Samsung Electronics 4-13

4-6 Audio

4-6-1 Outline

The four data (Data 0~3) outputted from A/V decoder (VIC1 ; ZiVA-3) are supplied to DATA 0 for 2-channel mixed audio output and to DATA 1~3 for Analog audio output (5.1-channel). The audio data (0~3) transmitted from A/V decoder (VIC1 ; ZiVA-3) are converted into analog signal via audio D/A converter and outputted via post filter and amplifier. CD and VCD are outputted with only 2 channels audio data and transmit them to Data 0 and Data 1. Front L/R channel is outputted in mixed audio output (L/R output) and analog audio output and surround L/R, center and subwoofer arenÕt outputted. If DVD of 2 channels source disc is used, it is outputted by the same way with CD and VCD.

AIC1

AK4324

D/A CONVERTER

POST

FILTER

POST

FILTER

AMP

VIC1

(ZiVA-3)

A/V Decoder

DATA0 LRCK

BCK

Mixed Audio Output (2-Channel)

Fig. 4-13 Audio Output Block Diagram

Page 14

Circuit Descriptions

4-14 Samsung Electronics

4-6-2 DVD Audio Output

1) Compressed Data

The audio data inputted to VIC1 (ZiVA-3) A/V decoder is divided into compressed data and uncompressed data. It is compressed data that is compressed with multi-channel audio data such as Dolby digital, MPEG, DTS, etc. The compressed data inputted to VIC1 (ZiVA-3) is converted into the uncompressed data of 2, 4, and 6 channels through ZiVA-3 built-in audio decoder and is outputted to Data 0, 1, 2, and 3 through digital audio interface. The compressed data is transmitted to external AC-3 amplifier or MPEG/DTS amplifier as IEC-958/1937 transmission data format compressed by ZiVA-3 built-in IEC-958 output process.

2) Uncompressed Data

The uncompressed data is that data isnÕt compressed, so it is called CD-DA, LPCM data. The 2 channels data is converted through audio decoder 2-channel data and Data 0 and Data 1 are outputted in digital audio interface.Via IEC-958 output process, they is transmitted to digital amplifier or AC-3/MPEG/DTS amplifier built in the external digital input source with IEC-958/1937 transmission format.

AUDIO INPUT

BUFFER

AUDIO OUTPUT

BUFFER

RECEIVER

DECODER

(IEC-958/1937)

AUDIO

DAC

HOST or DVD/CD

INTERFACE

IEC-958/1937

OUTPUT PROCESS

IEC-958/1937

INTERFACE

AUDIO DECODER

(MPEG, DOLBY DIGITAL,

CD-DA, LPCM

DIGITAL AUDIO

INTERFACE

2-, 4, or 6-

CHANNEL OUTPUT

PROCESS

Uncompressed 16- or 24-bit

LPCM camples at fs=44.1,48,96KHz

2-Channel LPCM, Decoder Dolby Digital, Decoded MPEG

Compressed Data (MPEG, Dolby Digital), CD-DA, LPCM

VIC4, 10 (LOCAL DRAM)

VIC1 (ZiVA-3 ; A/V DECODER)

Source Data Types :

MPEG-1,-2, Dolby Digital,

CD-DA, LPCM

Fig. 4-14 Audio Decoder and Output Interface Datapath