Samsung MAX85~10 Datasheet

9. Block Diagrams

9-1 Main

Samsung Electronics

9-1

Samsung Electronics9-2

Block Diagrams

9-2 CD

SLED

MOTOR

SPINDLE

MOTOR

PICK - UP

TRACKING

ACTUATOR

FOCUSING

ACTUATOR

A.B.C.D.E.F

LD.PD

DISC

SP+

SP-

TRK+ TRK-

FCS-

17

18

11 12 26 27 1

2

+5V

19

10

25 3

43

46

50

48

71P/U IN

LIMIT S/W

OPEN/CLOSE MOTOR

2

10

DM- DM+

MOTOR DRIVER

OPEN/CLOSE S/W

41

69.70

65.66.

67.68

33.30

29.25

22.24.23

31

35.36.37

38

40

MOTOR CONTROL

S/W SENSOR

FOK

MAIN PCB MAIN PCB

MICOM CTRL LINE

POWER / AUDIO LINE

10

1

11

219

19

R

G

L

21

20

36.37.38

68

25.26.30

29

10.70.72

73.75.76

27

MCK. MDATA. MLT

ISTAT

SQDT. LKFS. SOS1

SQCK

A. GND

R-CH

L-CH

GND

B+

RESET

LOCK.SMEF.WDCH.SMON.SMSD

SL IN

SP IN

TE IN

EF IN

VREF

SL-

SL+

MOTOR/ACTUATOR DRIVER

6

ASSP

KB9223

NIC 9223

SCW1

SCW4

SIC1,SIC2,SIC3

DIGITAL SIGNAL PROCESSOR

16.9344MHz

66.69

8

EFM.TRCNT

LB1641/BA6209

UP/DOWM S/W

ROULETTE SENSOR

UP/DOWN

ROULETTE

MOTOR

SIC1,2,3

KA9258

NIC 9258

KS9286

NIC9286

NIC9223

KB9223

SUB PCB

9

9-3Samsung Electronics

Block Diagrams

DATA

CLK

STB CLK

P1 P2 P3 P4 P5

P15 P16

SO

Controller Circuit

Shift Register

Latch Circuit

NJU3716M : JIC5

BA4560 : DIC4

9-3-1 Main

9-3 IC & TR Internal Diagrams

Samsung Electronics9-4

Block Diagrams

1

22

XIN

XOUT

16

FMIN

15

AMIN

3

CE

4

DI

5

CL

6

DO

17

VDD

21

Vss

C2B

1/F

P0WER

ON

RESET

7 8 9 10

BO1 BO2 BO3 BO4

11

IO1

13

IO2

18

PD

19

AIN

20

ADUT

12

IFIN

REFERENCE DIVIDER

PHASE DETECTOR CHARGE PUMP

UNLOCK

DETECTOR

UNIVERSAL

COUNTER

DATA SHIFT REGISTER

LATCH

12bita PROGRAMMABLE

DIVIDER

SWALLOW COUNTER

1/16, 1/17 4D1ts

1/2

L-N1

L-N2

L-N3

L-N4

R-N1

R-N2

R-N3

R-N4

11

12

13

14

10

9

8

7

100K

G

0/30dB

2dB STEP

INPUT MULTIPLEXER

GAIN

MUXOUTL

15 16

27

26 25 23 24

TREBLE(L)

MOUT(L)

BN(L)

BOUT(L)

UN(L)

RR

MUXOUTR

TREBLE(R)

MOUT(R)

BN(R)

BOUT(R)

CREF

UN(R)

RR

17 18 20 19 20 21

22

2

4

3

5

30

1

29

6

AGND

R OUT

L OUT

DIGGND

SDA

SCL

SPKR ATT

LEFT

I CBUS DECDER + LATCHES

2

VOLUME TREBLE MIDDLE BASS

SPKR ATT

RIGHT

Verf

V3

VOLUME TREBLE MIDDLE BASS

LC72131 : TIC2

TDA7439: FIC2

9-5Samsung Electronics

Block Diagrams

DATA

CLK

STB CLK

P1 P2 P3 P4 P5

P19 P20

SO

Controller Circuit

Shift Register

Latch Circuit

BIASC 1

VREFC 2

RREF 3

N.C. 4

N.C. 5

DIFOUT 6

CIN 7

AIN 8

VCC 9

PEAK

HOLD

PEAK

HOLD

PEAK

HOLD

PEAK

HOLD

PEAK

HOLD

PEAK

HOLD

PEAK

HOLD

RES

G4Hz

BPF

160Hz

BPF

400Hz

BPF

1KHz

BPF

2.5KHz

BPF

6.3KHz

BPF

15.6KHz

BPF

DIF

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

GND

AOUT

TEST

N.C.

SEL

C

B

A

BIAS

VREF

REFFERENCE CURRENT

MPX

A

A-C

C

DES

BA3834S : UIC3

NJU3718 : UIC2

Samsung Electronics9-6

Block Diagrams

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

29 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALC

DUFF

AM

OSC

AM

MIX

AM

RF AMF

AGC

AM

DET

AM

IF

SMFT

LEVEL

DET

FM

IF

FM

DET

REG GND

TUNING

DRIVE

S-CURVE

AM/FM

IF

BUFF

COMP

VCC

AM/FM

SW

VCC

PHASE DET

PILOT

DET

FF FF FF

STEREO

DRIVE

TRIG MUTE

STERO

SW

DECODER

PM

AM

SW A SW B SW C SW D

14 13 12 10 9 811

123 5674

LA1836: TIC1

LC4966: DIC2

9-7Samsung Electronics

Block Diagrams

OUTPUT

V+

-INPUT +INPUT

V-

32131230329428527626725824923102211211220131914181517

16

C L K

L P F A / D

L O G I C

SFB SW

MODE SEL

SU EC

MODE SEL

PHASE SEL

V O L

16kSRAM

L P F

D / A

6

1/2Vcc

MICMIX SW

DMIX SW

ON OFF

1 2

Vcc

VOL SEL

PHASE SEL

NJM074 : DIC3

M65846FP : DIC1

Samsung Electronics9-8

Block Diagrams

TR1 TR2

R2

TR3 TR4

TR5

R3

O1 R8

R10 R20

R18

R17

R13

TR19

TR17

R7

R6

R5

R4

R9

R14

R12

R19

TR9

TR11

TR21

TR14 TR13

TR51

TR42

SUB

TR51

R51

Comparator

R51

R42

R45

R44

R43

D53

D51 D52

R58

R58 R59

R59

D53

TR18

TR20

TR16 TR15

O5

R15

R16

O3O2

TR22TR10

TR12 TR24

C4

C3

TR23

TR8

O4

C2

TR7

R31

C1

18

19

20

12 13 16 10 14 15 11 9

6

7

4

5

2

3

1

212217

8

S. W. Cont.

21

MSOUT

201918171615141312

PB A/B

111098765

BIAS 1

DET(R)

RECOUT(R)

EQOUT(R)

EQIN(R)

PBOUT(R)

RIN(R)

33k

0.1µ

+

43

ABO(R)

0.0047µ

2

AIN(R)

1

222324252627282930313233343536373839404142

V

EE

V

CC

V

CC

V

EE

BIAS

V

CC

V

EE

BIN(R)

DET(L)

RIN(L)

BIN(L)

ABO(L)

AIN(L)

GND

BIAS 2

0.1µ

0.0047µ

22k

+

++

+

A 120/70

NORM/HIGH

BIAS ON/OFF

NR ON/OFF

RM ON/OFF

B NORM/CROM/METAL

REC/PB/PASS

BIAS(M)

BIAS(C)

BIAS(N)

MSDET

MSIN

MAOUT

MAI

100k

15k

12k

LPF

DOLBY

B-NR

EQ

8.2k

GPCAL

RECCAL

EQOUT(L)

EQIN(L)

RECOUT(L)

PBOUT(L)

0.33µ

1000 p

BIAS

SW

MS

DET

300k

LM ON/OFF

15k

12k

EQ

DOLBY

B-NR

+

HA12203/HA12204 : JIC3

STK417-090: AIC1

9-9Samsung Electronics

Block Diagrams

DATA

CLK

STB CLK

P1 P2 P3 P4 P5

P15 P16

SO

Controller Circuit

Shift Register

Latch Circuit

CK

C

SI SO

(OP-10)

I/O-10

I/O-9

(OP-9)

I/O-8

(OP-8)

I/O-7

(OP-7)

I/O-6

(OP-6)

I/O-5

(OP-5)

I/O-4

(OP-4)

I/O-3

(OP-3)

I/O-2

(OP-2)

I/O-1

(OP-1)

GND

VDD

STB

Serial

Latch

Driver

Y

NJU3716M : JIC5

TC9173P : JIC6

Samsung Electronics9-10

Block Diagrams

32

OUT1 OUT2

VCC2

810 9 7

P1 P2 VCC1

4

V2

6

IN2IN1

GND

5 1

LB1641

Input logic circuit

Predriver

LB1641/BA6209

28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 6 7 8 9 10 11 12 13 14

LEVEL SHIFT

BUY

10K

REGULATOR

10K

MUTE

50K

10K

LEVEL SHIFT

10K

BUY

T S D

10K

BUY

5

KA9258 : NIC9258

LB1641/BA6209(MOTOR DRIVER) : SIC1,SIC2,SIC3,NIC1641

9-3-2 CD

TR

1

E

* NOTE : KSB564 = ‘EBC’ TYPE

C

B

2

3

KSR1003 A928

9-11Samsung Electronics

Block Diagrams

26

32

33

30

11 12 14

77 67 80 24

17 22

37 38 36

69 68

8

9

72 73 75 76 70

4 2

5 3

66

19

20

7

29

65

63

62

61

EFMI

CNTVOL

DPFIN

DPFOUT

DPDO

SMEF

SMON

SMDP SMSD

LOCK XOUT

XIN

MDAT

MCK

MLT

TRCNT

/ISTAT

LRCHO ADATAO BCKO

BCKI ADATAI LRCHI EMPH

VREFL1 VREFH1

XTALSEL

TESTO

CDROM

TEST1

DATX

RCHOUT

LCHOUT

S0S1

SBCK

SDAT

SUBCODE

SYNC

DETECTOR

SUBCODE

OUTPUT

SUBCODE-Q

REGISTER

EFM

PHASE

DETECTOR

FRAME SYNC

DETECTOR

PROTECTOR

INSERTOR

EFM

DEMODULATOR

SQDT SQCK

DIGITAL

PLL

DIGITAL

CLV

SERVO

23BIT

SHIFT

REGISTER

X-TAL

TIMING

GENERATOR

CPU

INTERFACE

TRACK

COUNTER

MODE

SELECTOR

DIGITAL OUTPUT

ADDRESS

GENERATOR

16K

SRAM

ECC

INTERPOLATOR

DIGITAL

FILTER

& DE-EMPH

D/A

CONVERTER

8BIT DATA BUS

KS9286 : NIC9286

Samsung Electronics9-12

Block Diagrams

KB9223 : NIC9223

RF–

FEI

RF Amp

FDFCT

59 54 22 30 29 31 38 37 36 35 51 52 58 26 28 27 3

60 47 48

57

49 50 53 55 62 61

43 44 42

46 45 23 24

25

6

39

1

40

15 16 13 14 19 17 12 11 9 105

32 33 77

2

4

78 76 75

69

70

71

68 79

66 63 67

65

73

74

TE1

WDCH

TRCNT

LOCH

ISTAT

RESET

MLT

MDATA

MCK

ATSC

TZC

FE2

FLB

FGD

FS3

FEFEO

TDFCT

TETEO TE2 LPFT TG2 TGU

SLO SL– SL+

SPDLO SPDLSMDP SMON SMEF FSET MIRROR MCP

FOK

GC10

GC11

CH10

CH11

MUTEI

RRC

CH20

CH21

GC21

GC20

DCC1

RFO

PD1 PD2

F

E

EI

PD

LD

VR

ARF

IRF

ASY

EFM

RFI

DCB

Focus Error Amp

FE-BIAS Adjustment

Tracking Error Amp E/F Balance & Gain

Control

APC Amp

Center Voltage Amp.

RF Level AGC

&

Equalizer

EFM

Comparator

Defect Dectection

Circuit

Micom Data

Interface Logic

MICOM TO SERVO CONTROL

AUTO SEQUENCER

ADJUSTMENT-FREE CONTROL

FS1 to

FS4

TM to

TM6

BAL1 to

BAL5

PS1 to

PS4

GA1 to

GAS

Focus Phase

Compensation

& Offset cancel circuit

Tracking Phase

Compensation Block

& Jump Pulse GEN.

Sled Servo Amplifier

& Sled Kick GEN.

Spindle Servo LPF

(Double Speed)

MIRROR DETECTION

CIRCUIT

FOK DETECTION

CIRCUIT

Built-in Post Filter Amp (L&R)

RF Amp

9-13Samsung Electronics

9-4 µ-COM : UIC1

No.

Port

Name I/O

Function

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P 16

17 30 31 32 33 34 35 36 37 70

RESET

P 74

75 VSS1 CF 1

2

VDD1

P 80

81 82 83 84 85 86 87

P 71

72

73 S 0

1 2 3 4 5 6 7 8 9

S 10

11 12 13 14 15

VDD3

S 16

17

18

19

D12

JOG

POWER

TUNED

A/MUTE

CE11

DI1

DO1 CLK1 CE31

PSNS

MO/ST

CF2

GND

XT1

XT2

THS

AMPS

EQ IN

KEY1 KEY2

JOG

KEY3

MIC

T/SENS

SCOR REMO

G1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

S1

2 3 4

I I

O

I/O

O O

I O O O

I

O

I

I O O O O O O O O O O O O O O O O

O O

TC9173 INPUT MULTI JOG IN POWER ON/OFF TUNED/DSP MUTE AUDIO MUTE LC72131(PLL) CE LC72131 DATA INPUT LC72131 /TDA7439 LC72131 /TDA7439 M65846 CE POWER SENSE

FM MONO/STEREO SUB OSC(CLOCK) MAIN GND MAIN OSC MAIN OSC MAIN 5V POWER AMP PROTECT/HPS AMPS SIGNAL EQUALIZER INPUT A/D KEY INPUT 1 A/D KEY INPUT 2 MULTI JOG IN A/D KEY INPUT 3 MIC ON SNS CD TRAY SENSE SCOR INT REMOCON INPUT VFD GRID 1 VFD GRID 2 VFD GRID 3 VFD GRID 4 VFD GRID 5 VFD GRID 6 VFD GRID 7 VFD GRID 8 VFD GRID 9 VFD GRID 10 VFD GRID 11 VFD GRID 12 VFD GRID 13 VFD GRID 14 VFD GRID 15 VFD GRID 16

VFD SEG 1 VFD SEG 2 VFD SEG3 VFD SEG4

Block Diagrams

Samsung Electronics9-14

No.

Port

Name

I/O

Function

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

VP

S 20

21

22 23 24 25 26 27 28 29 30 31 32

PE 1

2 3 4 5 6 7

VDD 4

PF 0

1 2 3 4 5 6 7

PG 0

1 2 3

P 00

01

02

03

VSS2

VDD2

P 04

05 06 07

10 11 12 13 14 15

S5 S6 S7 S8

S9 S10 S11 S12 S13 S14 S15 S16 S17

OPT

LKFS

FOK

SENSE

SENSE1

SW2 SW1

RL+

LAT1

OPEN

CLOSE

XRST C-LAT EMPH

EVR

VCLK

VR

V-LAT

V-DATA

MCK C-DATA MDATA

1 SOL

CE32

MLT CE34 SOL2

TRCNT

SQDT SQRT

CLK3

DO3 CE33

O O O O O O O O O O O O O

I I I I I I I

O O O O O O O O O

I I

I/O

O O O O

O O O O O

I O O O O

VFD SEG 5 VFD SEG 6 VFD SEG 7 VFD SEG 8 VFD SEG 9 VFD SEG 10 VFD SEG 11 VFD SEG 12 VFD SEG 13 VFD SEG 14 VFD SEG 15 VFD SEG 16 VFD SEG 17 TUNER/TIME/PRO-LOGIC

FOCUS OK SENSE & LIMIT SWITCH SENSE1

ROULETTE+ LATCH OPEN MOTOR CLOSE MOTOR RESET C-LATCH/REM DO/PRO DO EMPHASI/REM CE/PRO LED P ERE VR SW VCD-CLOCK/REM MUTE/PRO-L ELE VR SW VCD LAT/REM NAR/PRO CE2 VCD DATA/REM CH/PRO CE1 DSP/SSP CONTROL CLOCK C-DATA/REM CLK/PRO CLK DSP/SSP CONTROL DATA 1 DECK SOLENOID

TC9173 CE DSP/SSP CONTROL LATCH NJU3718 CHIP ENABLE 2 DECK SOLENOID LD ON SUBQ DATA INPUT SUBQ DATA INPUT CLOCK NJU3716/18/TC9173/M65846 NJU3716/18/TC9173/M65846 NJU3716 CE

Block Diagrams

9-15Samsung Electronics

Block Diagrams

Name

No.

NJU3718 : UIC2

TC9173 : JIC6

NJU3716 : JIC5

Function

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

P 9

10 11 12 13 14

GND

P 15

16 17 18 19 20

S 0

DO3 CLK3 CE34

CLR

P1 P2

VSS

P3 P4 P5 P6 P7 P8

VDD

DISC2 LED DISC3 LED EQ A EQ B EQ C REC/PAUSE

TUNER FUNCTION LED CD FUNCTION LED TAPE FUNCTION LED AUX FUNCTION LED ECHO LED / PRO LED SCORE LED

MICOM 99 MICOM 98 MICOM 93 VDD STOP LED COMM` 1 LED GND COMM` 2 LED COMM` 3 LED DISC 1 LED JOG LED CD MUTE VCD / REMAKE RESET

Name

No.

Function

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

P 7

8

9 10 11

GND

P 12

13 14 15 16

S 0

DO3 CLK3 CE32

CLR P 1

GND

P 2

3 4 5 6

VDD

STS 1 R/P P/B 1 MOTOR HI / SP

REC 1 A/B NOR/HI REC MUTE DOLBY NR

TUNER MODE

SRS

STS LINE MUTE P/B

Name

No.

Function

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

GND

P 1

2 3 4 5 6 7 8 9

10

DO 3

DI 2 CLK

CE 33

CLR

GND REC / R MODE / B HALF / B HALL / B REC / F MODE / A HALF / A NC NC HALL / A

Samsung Electronics9-16

Block Diagrams

9-5 RF AMP & Servo Processor(KB9223) : NIC9223

No.

Port

Description

1 2 3 4 5 6

7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27

28 29 30 31 32 33 34 35 36 37 38 39 40

MCP

DCB FRSH DCC2 DCC1 FSET

VDDA

VCCP GC21 GC20

CH2I GC2O CH1O

CH1I GC1O

GC1I

RRC

VSSP

MUTEI

ISET

VREG

WDCK

SMDP

SMON

SMEF

FLB FS3

FGD

LOCK

TRCNT

ISTAT

ASY EFM

VSSA

MCK

MDATA

MLT

RESET

MIRROR

FOK

Capacitor connection pin for mirror hold Capacitor connection pin for defect Bottom hold Capacitor connection pin for time constant to generate focus search waveform The input pin through capacitor of defect bottom hold output The output pin of defect bottom hold The peak frequency setting pin for focus, tracking servo and cut of frequency of CLV LPF Analog VCC for servo part Vcc for post filter Amplifier negative input pin for gain and low pass filtering of DAC output CH2 Amplifier output pin for gain and low pass filtering of DAC output CH2 The input pin for post filter channel2 The output pin for post filter channel2 The output pin for post filter channel1 The input pin for post filter channel1 Amplifier output pin for gain and low pass filtering of DAC output CH1 Amplifier negative input pin for gain and low pass filtering of DAC output CH1 The pin for noise reduction of post filter bias VSS for post filter The input pin for post filter muting control The input pin for current setting of focus search, track jump and sled kick voltage The output pin of regulator The clock input pin for auto sequence The input pin of CLV control output pin SMDP of DSP The input pin for spindle servo ON through SMON of DSP The input pin of provide for an external LPF time constant Capacitor connection pin to perform rising low bandwidth of focus loop The pin for high frequency gain change of focus loop with internal FS3 pin switch Reducing high frequency gain with capacitor between FS3 pin Sled runaway prevention pin Track count output pin Internal status output pin The input pin for asymmetry control EFM comparator output pin Analog VSS for servo part Micom clock input pin Micom data input pin Micom data latch input pin Reset input pin The mirror output for test The output pin of focus OK comparator

9-17Samsung Electronics

Block Diagrams

No.

Port

Description

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

SSTOP

SL+

SLO

SL-

SPDL-

SPDLO

FE-

FEO

TE-

TEO

ATSC

TZC

TE2 TE1

LPFT

DVDD

TDFCT

FE2 FE1

FDFCT

TGU

TG2

FEBIAS

DVEE

PD1 PD2

F

E PD LD VR

VCC

RF-

RFO

IRF

ARF

RFI

CAGC

EI

GND

The pin for detection whether pick_up position is innermost or not The noninverting input pin of sled servo amplifier The output pin of sled servo amplifier The inverting input pin of sled servo amplifier The noninverting input pin of spindle servo amplifier The output pin of spindle servo amplifier The inverting input pin of focus servo amplifier The output pin of focus servo amplifier The inverting input pin of tracking servo amplifier The output pin of tracking servo amplifier The input pin for Anti-shock detection The comparator input pin for tracking zero crossing detection Tracking servo input pin Tracking error amplifier output pin The input pin of tracking error low pass filtering signal The power supply pin for logic circuit The capacitor connectiong pin for tracking defect compensation Focus servo input pin Focus error amplifier output pin The capacitor connection pin for focus defect compensation The capacitor connection pin for high frequency tracking gain switch The pin for high frequency gain change of tracking servo loop with internal TG2 switch Focus error bias voltage control pin The DVEE pin for logic circuit The negative input pin of RF I/V amplifier1(A+C signal) The negative input pin of RF I/V amplifier2(B+D signal) The negative input pin of F I/V amplifier(F signal) The negative input pin of E I/V amplifier(E signal) The input pin for APC The output pin for APC The output pin of (AVEE+AVCC)/2 voltage VCC for RF part RF summing amplifier inverting input pin RF summing amplifier output pin The input pin for AGC The output pin for AGC The input pin for EFM comparating The capacitor connection pin for AGC Feedback input pin of E I/V amplifier for EF Balance control GND for RF part

Samsung Electronics9-18

Block Diagrams

No.

Port

Description

1 2 3 4 5 6 7 8

9 10 11 12

13 14

15 16 17 18 19 20 21 22 23 24 25 26 27 28

29 30 31

32 33 34 35 36 37 38 39 40

-

O

I

O

I

-

O

I O O O O

-

O

I

O O

-

I

I O O O

I

I O O

I O

-

I

I/O I/O

AVDD1

DPDO

DPFIN DPFOUT CNTVOL

AVSS1

DATX

XIN

XOUT

WDCHO

LRCHO

ADATAO

DVSS1

BCKO

C2PO VREFL2 VREFL1

AVDD2

RCHOUT

LCHOUT

AVSS2 VREFH1 VREFH2

EMPH

LKFS S0S1

RESET

/ESP

SQCK SQDT SQOK

SBCK SDAT

DVDD1

MUTE

MLT

MDAT

MCK

DB8 DB7

Analog VCC1 Charge pump output for Digital PLL Filter input for Digital PLL Filter output for Digital PLL VCO control voltage for Digital PLL Analog Ground1 Digital Audio output data X’tal oscillator input X’tal oscillator output Word clock output of 48 bit/Slot (88.2KHz) Channel clock output of 48 bit/Slot (44.1KHz), 88.2KHz when ESP ON Serial audio data output of 48 bit/Slot (MSB first), double speed output when ESP ON Digital Ground1 Audio data bit clock output of 48 bit/Slot(2.1168MHz), 4.2336MHz when ESP ON C2 Pointer for output audio data Input terminal2 of reference voltage “L”(Floating) Input terminal2 of reference voltage “L”(GND connection Analog VCC2 Right-Channel audio output through D/A converter Left-Channel audio output through D/A converter Analog ground2 Input terminal1 of reference voltage “H” (VDD connection) Input terminal2 of reference voltage “H” (Floating) Emphasis/Non-Emphasis output, H: Emphasis ON, L: Emphasis OFF The Lock Status output of frame sync Output of subcode sync signal(S0+S1) System reset at “L” ESP function ON/OFF control(“L”: ESP function ON, “H”: ESP function OFF) Clock for output Subcode-Q data Serial output of Subcode-Q data The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q) Clock for output subcode data Subcode serial data output Digital VDD1 Mute control input (“H”: Mute ON) Latch Signal input from Micom (Schmit Trigger) Latch Signal input from Micom (Schmit Trigger) Latch Signal input from Micom (Schmit Trigger) SRAM data I/O port8 (MSB) SRAM data I/O port7

9-6 Digital Signal Processor(KS9286) : NIC9286

9-19Samsung Electronics

Block Diagrams

No.

Port

Description

41 42 43 44 45 46 47 48 49 50 51

52 53 54 55 56

57 58 59 60 61 62 63 64 65 66 67 68 69 70

71 72 73 74 75

76 77 78 79 80

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O

I/O I/O I/O I/O

I I I I I I I

O

I

O

O O O

-

O

I I I I

DB6 DB5 DB4 DB3 DB2

DB1 C1F1 C1F2 C2F1 C2F2 C2FL

/PBCK

DVSS2

FSDW

ULKFS

/JIT

C4M

C16M

/WE

/CS

XTALSEL

TEST0

CDROM

SRAM TEST1

EFMI

ADATAI

/ISTAT

TRCNT

LOCK

PBFR

SMEF

SMON

DVDD2

SMDP

SMSD

BCKI

TESTV

DSPEED

LRCHI

SARM data I/O port 6 SARM data I/O port 5 SARM data I/O port 4 SARM data I/O port 3 SARM data I/O port 2 SARM data I/O port 1 (LSB) Monitoring output for C1 error correction (RA1) Monitoring output for C1 error correction (RA2) Monitoring output for C2 error correction (RA3) Monitoring output for C21 error correction (RA4) C2 decoder flag (RA5, “H” : When the processing C2 code is impossible correction status.) Output of VCO/2 (4.3218MHz) (RA6) Digital ground2 Window or unprotected frame sync (RA7) Frame sync protection state (RA8) Display of either RAM overflow or underflow for ±4 frame jitter margin (RA9) Only monitoring signal (4.2336MHz) (RA10)

16.9344MHz signal output (RA11) Terminal for test Terminal for test Mode Selection1 (H: 33.8688MHz, L:16.9344MHz) TEST input terminal (GND connection) Mode Selection2 (H: CD-ROM, L: CDP) TEST input terminal (GND connection) TEST input terminal (GND connection) EFM signal input Serial audio data input of 48 bit/Slot (MSB first) The internal status output Tracking counter input signal Output signal of LKFS condition sampled PBFR/16 (if LKFS is “H”, LOCK

is “H”, if LKFS is sampled “L” at least 8 times by PBFR/16, LOCK is “L”) Write frame clock (Lock: 7.35KHz) LPF time constant control of the spindle servo error signal ON/OFF control signal for spindle servo Digital VDD2 Spindle Motor drive (Rough control in the SPEED mode, Phase control in the PHASE mode) Spindle Motor drive (Velocity control in the PHASE mode) Audio data bit clock input of 48 bit/Slot (2.1168MHz) TEST input terminal (GND connection) TEST input terminal (VDD connection) Channel clock input of 48 bit/Slot (44.1KHz)