Datasheet M392B2873FH0 Datasheet (SAMSUNG)

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Rev. 1.0, Jan. 2010

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M392B2873FH0 M392B5673FH0 M392B5670FH0 M392B5170FM0

240pin VLP Registered DIMM

1.35V

based on 1Gb F-die

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

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VLP Registered DIMM

datasheet DDR3L SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First Release Jan. 2010 - S.H.Kim

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VLP Registered DIMM

datasheet DDR3L SDRAM

Table Of Contents

240pin VLP Registered DIMM based on 1Gb F-die

1. DDR3L VLP Registered DIMM Ordering Information ...................................................................................................5

2. Key Features................................................................................................................................................................. 5

3. Address Configuration ..................................................................................................................................................5

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................6

5. Pin Description .............................................................................................................................................................7

6. ON DIMM Thermal Sensor ........................................................................................................................................... 7

7. Input/Output Functional Description..............................................................................................................................8

8. Pinout Comparison Based On Module Type.................................................................................................................9

9. Registering Clock Driver Specification..........................................................................................................................10

9.1 Timing & Capacitance values ..................................................................................................................................10

9.2 Clock driver Characteristics..................................................................................................................................... 10

10. Function Block Diagram:.............................................................................................................................................11

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 12

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13

10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ................................................................. 14

11. Absolute Maximum Ratings ........................................................................................................................................ 15

11.1 Absolute Maximum DC Ratings............................................................................................................................. 15

11.2 DRAM Component Operating Temperature Range .............................................................................................. 15

12. AC & DC Operating Conditions...................................................................................................................................15

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................15

13. AC & DC Input Measurement Levels..........................................................................................................................16

13.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 16

13.2 V

13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 18

13.3.1. Differential Signals Definition .........................................................................................................................18

13.3.2. Differential Swing Requirement for Clock (CK - CK

13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 19

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 20

13.4 Slew Rate Definition for Single Ended Input Signals .............................................................................................20

13.5 Slew rate definition for Differential Input Signals ...................................................................................................20

14. AC & DC Output Measurement Levels .......................................................................................................................21

14.1 Single Ended AC and DC Output Levels............................................................................................................... 21

14.2 Differential AC and DC Output Levels ................................................................................................................... 21

14.3 Single-ended Output Slew Rate ............................................................................................................................ 21

14.4 Differential Output Slew Rate ................................................................................................................................ 22

15. IDD specification definition..........................................................................................................................................23

16. IDD SPEC Table .........................................................................................................................................................25

17. Input/Output Capacitance ...........................................................................................................................................27

18. Electrical Characteristics and AC timing .....................................................................................................................28

18.1 Refresh Parameters by Device Density................................................................................................................. 28

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 28

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 28

18.3.1. Speed Bin Table Notes ..................................................................................................................................31

19. Timing Parameters by Speed Grade ..........................................................................................................................32

19.1 Jitter Notes ............................................................................................................................................................35

19.2 Timing Parameter Notes........................................................................................................................................ 36

20. Physical Dimensions................................................................................................................................................... 37

20.1 128Mbx8 based 128Mx72 Module (1 Rank) - M392B2873FH0 ............................................................................ 37

20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................ 37

20.2 128Mbx8 based 256Mx72 Module (2 Ranks) - M392B5673FH0 .......................................................................... 38

Tolerances.................................................................................................................................................... 17

REF

) and Strobe (DQS - DQS) .............................................18

0.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs38

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20.3 256Mbx4 based 256Mx72 Module (1 Rank) - M392B5670FH0 ............................................................................ 39

20.3.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs................................................................ 39

20.4 512Mbx4(DDP) based 512Mx72 Module (2 Ranks) - M392B5170FM0 ................................................................ 40

20.4.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs .............................................................. 40

20.4.2. Heat Spreader Design Guide ......................................................................................................................... 41

datasheet DDR3L SDRAM

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VLP Registered DIMM

datasheet DDR3L SDRAM

1. DDR3L VLP Registered DIMM Ordering Information

Part Number Density Organization Component Composition

M392B2873FH0-YF8/H9 1GB 128Mx72 128Mx8(K4B1G0846F-HY##)*9 1 18.75mm

M392B5673FH0-YF8/H9 2GB 256Mx72 128Mx8(K4B1G0846F-HY##)*18 2 18.75mm

M392B5670FH0-YF8/H9 2GB 256Mx72 256Mx4(K4B1G0446F-HY##)*18 1 18.75mm

M392B5170FM0-YF8/H9 4GB 512Mx72 DDP 512Mx4(K4B2G0446F-MY##)*18 2 18.75mm

NOTE :

- "##" - F8/H9/K0

- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11

Number of

Rank

Height

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 ns

CAS Latency 6 7 9nCK

tRCD(min) 15 13.125 13.5 ns

tRP(min) 15 13.125 13.5 ns

tRAS(min) 37.5 37.5 36 ns

tRC(min) 52.5 50.625 49.5 ns

DDR3-800 DDR3-1066 DDR3-1333

6-6-6 7-7-7 9-9-9

Unit

• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply

•V

= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

DDQ

• 400MHz f

• 8 independent internal bank

• Programmable

• Programmable Additive Latency(Posted

• Programmable

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with st write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin

CAS Latency: 6,7,8,9

CAS) : 0, CL - 2, or CL - 1 clock

CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)

arting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

85°C, 3.9us at 85°C < T

CASE

≤ 95°C

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

256Mx4(1Gb) based Module A0-A13 A0-A9, A11 BA0-BA2 A10/AP

128Mx8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10/AP

512Mx4(2Gb DDP) based Module A0-A13 A0-A9, A11 BA0-BA2 A10/AP

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VLP Registered DIMM

datasheet DDR3L SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

REFDQ

121

122 DQ4 43 DQS8 163

3 DQ0 123 DQ5 44

4DQ1124

6DQS

125

0126

7DQS0127

128 DQ6

9 DQ2 129 DQ7 49

10 DQ3 130

131 DQ12 51

12 DQ8 132 DQ13 52 BA2 172 A14 93 DQS

13 DQ9 133

15 DQS

134

1135

16 DQS1 136

137 DQ14 57

18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53

19 DQ11 139

140 DQ20 60

21 DQ16 141 DQ21 61 A2 181 A1 102 DQS

22 DQ17 142

24 DQS

143

2144

25 DQS2 145

146 DQ22 66

27 DQ18 147 DQ23 67

28 DQ19 148

149 DQ28 69

30 DQ24 150 DQ29 70 A10/AP 190 BA1

31 DQ25 151

33 DQS

152

3153

34 DQS3 154

155 DQ30 75

36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1

37 DQ27 157

158 CB4,NC 78

39 CB0,NC 159 CB5,NC 79 S2,NC 199

40 CB1,NC 160

161

NOTE : NC = No internal Connection

DM0,DQS9

,TDQS9

NC,DQS

,TDQS

DM1,DQS10

,TDQS10

NC,DQS

,TDQS

DM2,DQS11

,TDQS11

NC,DQS

,TDQS

DM3,DQS12

,TDQS12

NC,DQS

,TDQS

DM8,DQS17 TDQS17,NC

42 DQS8162

164 CB6,NC 84 DQS4 204

45 CB2,NC 165 CB7,NC 85 DQS4 205

46 CB3,NC 166

, NC

167 NC(TEST) 87 DQ34 207 DQ39

168 RESET

KEY

169 CKE1, NC 90 DQ40 210 DQ45

50 CKE0 170

171 A15 92

53 Err_Out/NC 173

174 A12/BC 95

55 A11 175 A9 96 DQ42 216 DQ47

56 A7 176

177 A8 98

59 A4 179

180 A3 101

182

63 NC, CK1 183

64 NC, CK

1 184 CK0 105 DQ50 225 DQ55

REFCA

185 CK0 106 DQ51 226

186

187 EVENT,NC 108 DQ56 228 DQ61

68 NC/Par_In 188 A0 109 DQ57 229

189

71 BA0 191

73 WE

192 RAS 113

193 S0 114 DQ58 234 DQ63

74 CAS 194

195 ODT0 116

77 ODT1,NC 197

198 S3,NC 119 SA2 239

200 DQ36

81 DQ32 201 DQ37

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

NC,DQS

,TDQS

82 DQ33 202

203

206 DQ38

DM4,DQS13

88 DQ35 208

209 DQ44

91 DQ41 211

212

DM5,DQS14

5 213

94 DQS5 214

215 DQ46

97 DQ43 217

218 DQ52

100 DQ49 220

221

DM6,DQS15

6 222

103 DQS6 223

104

107

110

111

DQS7

224 DQ54

227 DQ60

230

231

112 DQS7 232

233 DQ62

115 DQ59 235

236

118 SCL 238 SDA

120

240

,TDQS13

NC,DQS

,TDQS

,TDQS14

NC,DQS

,TDQS

,TDQS15

NC,DQS

,TDQS

DM7/DQS16

TDQS16

DM7,DQS

,TDQS

DDSPD

- 6 -

Rev. 1.0

SCL

SDA

WP/EVENT

SA0 SA1 SA2

EVENT

R1 0 Ω

R2 0 Ω

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VLP Registered DIMM

datasheet DDR3L SDRAM

5. Pin Description

Pin Name Description Number Pin Name Description Number

CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2

CK0

CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8

RAS

CAS

[3:0] Chip Selects 4

A[9:0],A11,

A[15:13]

A10/AP Address Input/Autoprecharge 1 EVENT

A12/BC

BA[2:0] SDRAM Bank Addresses 3 RESET

SCL Serial Presence Detect (SPD) Clock Input 1

SDA SPD Data Input/Output 1

SA[2:0] SPD Address Inputs 3

Par_In Parity bit for the Address and Control bus 1

Err_Out

NOTE : *The V

and V

Clock Input, negative line 1 DQ[63:0] Data Input/Output 64

Row Address Strobe 1 DQS[8:0] Data strobes 9

Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9

DM[8:0]/

Write Enable 1

Address Inputs 2\14 RFU Reserved for Future Use 2

Address Input/Burst chop 1 TEST

Parity error found on the Address and Control bus

pins are tied common to a single power-plane on these designs.

DDQ

DQS[17:9]

TDQS[17:9]

[17:9]

DQS

TDQS

REFDQ

REFCA

DDSPD

Data Masks/ Data strobes, Termination data strobes

Data strobes, negative line, Termination data

[17:9]

strobes

Reserved for optional hardware temperature sensing

Memory bus test toll (Not Connected and Not Usable on DIMMs)

Power Supply 22

Ground 59

Reference Voltage for DQ 1

Reference Voltage for CA 1

Termination Voltage 4

SPD Power 1

Total 240

6. ON DIMM Thermal Sensor

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

Resolution 0.25 °C /LSB -

Temperature Sensor Accuracy

Min. Typ . Max.

75 < Ta < 95 - +/- 0.5 +/- 1.0

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

- 7 -

Units NOTE

°C

Rev. 1.0

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VLP Registered DIMM

datasheet DDR3L SDRAM

7. Input/Output Functional Description

Symbol Typ e Polarity Function

CK0 Input

CK0

CKE[1:0] Input Active High

[3:0] Input Active Low

ODT[1:0] Input Active High On-Die Termination control signals

AS, CAS, WE Input Active Low

REFDQ

REFCA

BA[2:0] Input

A[15:13,

12/BC,11, 10/AP,9:0]

DQ[63:0],

CB[7:0]

DM[8:0]

DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.

DQS

[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.

TDQS[17:9],

[17:9] OUT

TDQS

SA[2:0] IN

SDA I/O

SCL IN

EVENT

DDSPD

RESET

Par_In IN Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)

Err_Out

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Input

Supply Reference voltage for DQ0-DQ63 and CB0-CB7

Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.

Input

I/O Data and Check Bit Input/Output pins

OUT (open drain)

Supply

OUT (open drain)

Positive

Edge

Negative

Edge

Active Low

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.

When sampled at the positive rising edge of the clock, CAS cuted by the SDRAM.

Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/ Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during Mode Register Set commands.

Active High Masks write data when high, issued concurrently with input data.

, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.

Supply Termination Voltage for Address/Command/Control/Clock nets.

TDQS/TDQS enable the same termination resistance function on TDQS/TDQS abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

These signals are tied at the system planar to either V address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V

This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the EVENT

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

The RESET low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock)

Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up.

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will

on the system planar to act as a pull-up.

DDSPD

on the system planar to act as a pull-up.

DDSPD

pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When

, RAS, and WE define the operation to be exe-

that is applied to DQS/DQS. When dis-

or V

to configure the serial SPD EEPROM

DDSPD

pin on TS/SPD part.

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datasheet DDR3L SDRAM

8. Pinout Comparison Based On Module Type

48, 49

120, 240

53 Err_Out

63 NC

64 NC CK1

68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs

76 S

77 ODT1, NC

79 S

167 NC TEST input used only on bus analysis probes NC

169 CKE1

171 A15

172 A14 A14

196 A13 A13

198 S

39, 40, 45, 46, 158, 159, 164,

165

125, 134, 143, 152, 161, 203, 212, 221, 230

126, 135, 144, 153, 162, 204, 213, 222, 231

187

NOTE : NC = No internal Connection

Signal NOTE Signal NOTE

1 Connected to the register on all RDIMMs S1

2, NC

3, NC

CBn Used on all RDIMMs; (n = 0...7) NC, CBn

DQSn,

TDQSn

DQS

TDQS

EVENT

Additional connection for Termination Voltage for Address/Command/Control/Clock nets.

Termination Voltage for Address/Command/Control/Clock nets.

Connected to the register on all RDIMMs NC Not used on UDIMMs

Not used on RDIMMs

Connected to the register on dual- and quadrank RDIMMs; NC on single-rank RDIMMs

Connected to the register on quad-rank RDIMMs, not connected on single or dual rank RDIMMs

Connected to the register on dual- and quadrank RDIMMs; NC on single-rank RDIMMs

Connected to the register on all RDIMMs

Connected to the register on quad-rank RDIMMs, not connected on single-or dual-rank RDIMMs

Connected to DQS on x4 SDRAMs, TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

Connected to DQS SDRAMs on RDIMMs; (n=9...17)

Connected to optional thermal sensing component. NC on Modules without a thermal sensing component.

RDIMM UDIMM

NC Not used on UDIMMs

Termination Voltage for Address/Command/Control/Clock nets.

Used for 2 rank UDIMMs, not used on single-rank UDIMMs, but terminated

Used for dual-rank UDIMMs, not connected on single-rank UDIMMs

TEST input used only on bus analysis probes

Used for dual-rank UDIMMs, not connected on single-rank UDIMMs

connected to SDRAMs on UDIMMs. However, these signals are terminated on UDIMMs. A15 not routed on some RCs

Used on x72 UDIMMs, (n = 0...7); not used on x64 UDIMMs

Connected to DM on x8 DRAMs, UDM or LDM on x16 DRAMs on UDIMMs; (n = 0...8)

on x4 DRAMs, TDQS on x8

NC NC Not used on UDIMMs

CK1

ODT1,NC

NC Not used on UDIMMs

CKE1,

A15, NC Depending on device density, may not be

NC Not used on UDIMMs

DMn

NC Not used on UDIMMs

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VLP Registered DIMM

datasheet DDR3L SDRAM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

TC = TBD

= 1.35V(1.28V~1.45V)

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 300 670 MHz

CH/tCL

ACT

PDM

DIS

(DATA)

(CLOCK)

(RST)

Pulse duration, CK, CK HIGH or LOW 0.4 -

Inputs active time4 before RESET is taken HIGH

Setup time Input valid before CK/CK 100 - ps

Hold time

Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns

output disable time(1/2-Clock pre-launch)

output disable time(3/4-Clock pre-launch) 0.25 -

output enable time(1/2-Clock pre-launch)

output enable time(3/4-Clock pre-launch) - 0.25

Data Input Capacitance 1.5 2.5

Data Input Capacitance 2 3

Reset Input Capacitance - 3

DCKE0/1 = LOW and DCS0/1

= HIGH

Input to remain Valid after CK/ CK

CK/CK

to output float

CK/CK

to output driving

& 1.5V(1.425~1.575V)

Min Max

175 -

0.5 -

-0.5

Units Notes

9.2 Clock driver Characteristics

Symbol Parameter Conditions

(cc)

jit

STAB

fdyn

CKsk

(per)

(hper)

Qsk1

dynoff

Cycle-to-cycle period jitter 0 40 ps

Stabilization time -6us

Dynamic phase offset -50 50 ps

Clock Output skew 50 ps

Yn Clock Period jitter -40 40 ps

Half period jitter -50 50 ps

Qn Output to clock tolerance (Standard 1/2 -Clock Pre-Launch)

Output clock tolerance (3/4 Clock Pre-Launch)

Maximum re-driven dynamic clock off-set -80 80 ps

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

TC = TBD

= 1.35V(1.28V~1.45V)

& 1.5V(1.425~1.575V)

Min Max

Units Notes

- 10 -

Rev. 1.0

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

DQS8 DQS8

DM8/DQS17

DQS

CB[7:0]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCLE0A

RODT0A

A[N:0]A

/BA[N:0]A

DQS3 DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS2 DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS1 DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS0 DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

Vtt

DQS4 DQS4

DM4/DQS13

DQS

DQ[39:32]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCLE0B

RODT0B

A[N:0]B

/BA[N:0]B

DQS5 DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS6 DQS6

DM6/DQS15

DQS15

DQ[55:48]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS7 DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

Vtt

D0 - D8

REFCA

DDSPD

Serial PD

1:2

R E G

I S T E R

S1* BA[N:0]

A[N:0]

RAS

CAS

CKE0

CK0

RESET

PST

** : SDRAMs D[8:0]

RS0B-> CS0 : SDRAMs D[7:4] RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8

RRASA

-> RAS : SDRAMs D[3:0], D8

RCASA

-> CAS : SDRAMs D[3:0], D8

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

ODT0

PAR_IN

RODT0A -> ODT0 : SDRAMs D[3:0], D8

S0* RS0A-> CS0 : SDRAMs D[3:0], D8

EVENT EVENT

REFDQ

D0 - D8

NOTE :

1. DQ-to-I/O wiring may be changed within a byte.

2. ZQ resistors are 240 1% For all other resistor values refer to the appropriate wiring diagram.

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4]

RRASB

-> RAS : SDRAMs D[7:4]

RCASB

-> CAS : SDRAMs D[7:4]

RWEA

-> WE : SDRAMs D[3:0], D8

RWEB

-> WE : SDRAMs D[7:4]

RCKE0B -> CKE0 : SDRAMs D[7:4]

RODT0B -> ODT0 : SDRAMs D[7:4] PCK0A -> CK : SDRAMs D[3:0], D8 PCK0A -> CK : SDRAMs D[7:4] PCK

0A -> CK : SDRAMs D[3:0], D8

PCK

0A -> CK : SDRAMs D[7:4]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

10. Function Block Diagram:

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

- 11 -

Rev. 1.0

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

DQS8 DQS8

DM8/DQS17

DQS17

CB[7:0]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

Vtt

D0 - D17

REFCA

DDSPD

Serial PD

EVENT EVENT

REFDQ

D0 - D17

NOTE :

1. DQ-to-I/O wiring may be changed within a byte.

2. Unless otherwise noted, resistor values are 15Ω ± 5%.

3. RS0 and RS1 alternate between the back and front sides of the DIMM.

4. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram.

5. See the wiring diagrams for all resistors associated with the command, address and control bus.

DQS DQS TDQS TDQS DQ[7:0]

D17

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS1A

PCK1A

RCKE1A

RODT1A

DQS3 DQS3

DM3/DQS12

DQS12

DQ[31:24]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D12

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS2 DQS2

DM2/DQS11

DQS11

DQ[23:16]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D11

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS1 DQS1

DM1/DQS10

DQS10

DQ[15:8]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D10

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS0 DQS0

DM0/DQS9

DQS9

DQ[7:0]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS4 DQS4

DM4/DQS13

DQS13

DQ[39:32]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCKE0B

RODT0B

A[N:0]B

/BA[N:0]B

Vtt

DQS DQS TDQS TDQS DQ[7:0]

D13

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS1B

PCK1B

RCKE1B

RODT1B

DQS5 DQS5

DM5/DQS14

DQS14

DQ[47:40]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D14

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS6 DQS6

DM6/DQS15

DQS15

DQ[55:48]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D15

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS7 DQS7

DM7/DQS16

DQS16

DQ[63:56]

DQS DQS TDQS TDQS DQ[7:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS DQS TDQS TDQS DQ[7:0]

D16

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

1:2

R E G

I S T E R

S1*

BA[N:0]

A[N:0]

RAS

CAS

CKE0

RESET

PST

** : SDRAMs D[8:0]

RS1B-> CS1 : SDRAMs D[16:13] RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RRASA

-> RAS : SDRAMs D[3:0], D[12:8], D17

RCASA

-> CAS : SDRAMs D[3:0], D[12:8], D17

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

PAR_IN

S0* RS0A-> CS0 : SDRAMs D[3:0], D8

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]

RRASB

-> RAS : SDRAMs D[7:4], D[16:13]

RCASB

-> CAS : SDRAMs D[7:4], D[16:13]

RWEA

-> WE : SDRAMs D[3:0], D[12:8], D17

RWEB

-> WE : SDRAMs D[7:4], D[16:13]

RCKE0B -> CKE0 : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17 PCK1B -> CK : SDRAMs D[16:13]

PCK

0A -> CK : SDRAMs D[3:0], D8

PCK

0B -> CK : SDRAMs D[7:4]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

CKE1

RCKE1A -> CKE1 : SDRAMs D[12:9], D17 RCKE1B -> CKE1 : SDRAMs D[16:13]

ODT0

RODT0A -> ODT0 : SDRAMs D[3:0], D8 RODT0B -> ODT0 : SDRAMs D[7:4]

ODT1

RODT1A -> ODT1 : SDRAMs D[12:9], D17 RODT1A -> ODT1 : SDRAMs D[16:13]

CK0

PCK0A -> CK : SDRAMs D[3:0], D8 PCK0B -> CK : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17 PCK

1B -> CK : SDRAMs D[16:13]

0B-> CS0 : SDRAMs D[7:4]

1A-> CS1 : SDRAMs D[12:9], D17

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

- 12 -

Rev. 1.0

DQ[27:24]

DQ[19:16]

DQS8 DQS8

CB[3:0]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

VSS

DQS17 DQS17

CB[7:4]

DQS DQS

D17

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS3 DQS

DQ[27:24]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS

DQ[31:28]

DQS DQS

D12

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS8

DQ[19:16]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS17

DQ[23:20]

DQS DQS

D11

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS8

DQ[11:8]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS17

DQ[15:12]

DQS DQS

D10

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS

DQ[3:0]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS

DQ[7:4]

DQS DQS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS8

DQ[35:32]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB

PCK0B

RCKE0B

RODT0B

A[N:0]B

/BA[N:0]B

VSS

DQS17 DQS17

DQ[39:36]

DQS DQS

D13

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS

DQ[43:40]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS

DQ[47:44]

DQS DQS

D14

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS8

DQ[51:48]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS17

DQ[55:52]

DQS DQS

D15

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

DQS8 DQS8

DQ[59:56]

DQS DQS

DQ[3:0]

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQS17 DQS17

DQ[63:60]

DQS DQS

D16

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

VSS

DQ[3:0]

Vtt

D0 - D17

REFCA

DDSPD

Serial PD

REFDQ

D0 - D17

NOTE :

1. DQ-to-I/O wiring may be changed within a nibble.

2. Unless otherwise noted, resistor values are 15Ω ± 5%.

3. See the wiring diagrams for all resistors associated with the command, address and control bus.

4. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram.

1:2

R E G

I S T E R

S1*

BA[N:0]

A[N:0]

RAS

CAS

CKE0

RESET

PST

** : SDRAMs D[17:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RRASA

-> RAS : SDRAMs D[3:0], D[12:8], D17

RCASA

-> CAS : SDRAMs D[3:0], D[12:8], D17

RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17

PAR_IN

S0* RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]

RRASB

-> RAS : SDRAMs D[7:4], D[16:13]

RCASB

-> CAS : SDRAMs D[7:4], D[16:13]

RWEA

-> WE : SDRAMs D[3:0], D[12:8], D17

RWEB

-> WE : SDRAMs D[7:4], D[16:13]

RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]

PCK

0A -> CK : SDRAMs D[3:0], D[12:8], D17

PCK

0B -> CK : SDRAMs D[7:4], D[16:13]

Err_out

QERR

RST

CK0

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

ODT0

RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17 RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]

CK0

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17 PCK0B -> CK : SDRAMs D[7:4], D[16:13]

RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]

(Unused register inputs ODT1 and CKE1 have a 330

resistor to ground)

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

EVENT EVENT

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

- 13 -

Rev. 1.0

DQS0 DQS0

DQ[3:0]

DQS DQS

DQ[3:0]

ZQDM

D0 - D17

REFCA

DDSPD

Serial PD

REFDQ

D0 - D17

NOTE :

1. DQ-to-I/O wiring may be changed within a nibble.

2. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram.

3. The connection of the Serial PD to EVENT_n

(Option 1) or to ground (Option 2) is realized by resistor options.

1:2

R E G

T E R

BA[2:0]

A[15:0]

RAS

CAS

CKE0

RESET

RST : SDRAMs D[35:0]

PAR_IN

S0[1:0] RS0A-> CS0A : SDRAMs D[9:0]

Err_out

CK0

ODT0

CK0

S0[3:2] RS1A-> CS1A : SDRAMs D[27:18]

0B-> CS0B : SDRAMs D[17:10]

1B-> CS1B : SDRAMs D[35:28] RBA[2:0]A -> BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RBA[2:0]B -> BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RA[15:0]A -> A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RA[15:0]B -> A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RRAS

A -> RAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RRAS

B -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RCAS

A -> CAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RCAS

B -> CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RWE

A -> WE: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RWE

B -> WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A -> CKE0A: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RCKE0B -> CKE0B: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RODT[1:0]A -> ODT0: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RODT[1:0]B -> ODT0: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

CK0A_R0 -> CK: SDRAMs D[4:0], D[22:18] CK0B_R0 -> CK: SDRAMs D[13:10], D[31:28] CK0C_R1 -> CK: SDRAMs D[9:5], D[27:23] CK0D_R1 -> CK: SDRAMs D[17:14], D[35:32]

0A_R0 -> CK: SDRAMs D[4:0], D[22:18]

0B_R0 -> CK: SDRAMs D[13:10], D[31:28]

0C_R1 -> CK: SDRAMs D[9:5], D[27:23]

0D_R1 -> CK: SDRAMs D[17:14], D[35:32]

VSS

RS0 RS1

CS VSS

DQS DQS

DQ[3:0]

D18

ZQDM CS VSS

DQS1 DQS

DQ[11:8]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D19

ZQDM CS VSS

DQS2 DQS2

DQ[16:19]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D20

ZQDM CS VSS

DQS3 DQS3

DQ[24:27]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D21

ZQDM CS VSS

DQS4 DQS4

DQ[32:35]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D22

ZQDM CS VSS

DQS5 DQS5

DQ[40:43]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D23

ZQDM CS VSS

DQS6 DQS6

DQ[48:51]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D24

ZQDM CS VSS

DQS7 DQS7

DQ[56:59]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D25

ZQDM CS VSS

DQS8 DQS

CB[3:0]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D26

ZQDM CS VSS

DQS9 DQS9

DQ[4:7]

DQS DQS

DQ[3:0]

ZQDM CS VSS

DQS DQS

DQ[3:0]

D27

ZQDM CS VSS

DQS10 DQS

DQ[12:15]

DQS DQS

DQ[3:0]

D10

ZQDM CS VSS

DQS DQS

DQ[3:0]

D28

ZQDM CS VSS

DQS11 DQS11

DQ[20:23]

DQS DQS

DQ[3:0]

D11

ZQDM CS VSS

DQS DQS

DQ[3:0]

D29

ZQDM CS VSS

DQS12 DQS12

DQ[28:31]

DQS DQS

DQ[3:0]

D12

ZQDM CS VSS

DQS DQS

DQ[3:0]

D30

ZQDM CS VSS

DQS13 DQS13

DQ[36:39]

DQS DQS

DQ[3:0]

D13

ZQDM CS VSS

DQS DQS

DQ[3:0]

D31

ZQDM CS VSS

DQS14 DQS14

DQ[44:47]

DQS DQS

DQ[3:0]

D14

ZQDM CS VSS

DQS DQS

DQ[3:0]

D32

ZQDM CS VSS

DQS15 DQS15

DQ[52:55]

DQS DQS

DQ[3:0]

D15

ZQDM CS VSS

DQS DQS

DQ[3:0]

D33

ZQDM CS VSS

DQS16 DQS16

DQ[60:63]

DQS DQS

DQ[3:0]

D16

ZQDM CS VSS

DQS DQS

DQ[3:0]

D34

ZQDM CS VSS

DQS17 DQS

CB[7:4]

DQS DQS

DQ[3:0]

D17

ZQDM CS VSS

DQS DQS

DQ[3:0]

D35

ZQDM CS VSS

QERR

RST

Thermal sensor with SPD

A1 A2

SA0 SA1 SA2

SCL

SDA

EVENT_n EVENT_n

Serial PD w/integrated Thermal Sensor

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

- 14 -

Rev. 1.0

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11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

Voltage on V

DDQ

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the cente

3. V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

Storage Temperature -55 to +100 °C 1, 2

STG

and V

DDQ

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times;and V

r/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

cause permanent damage to the device. This is a stress rating only and functional operation of the

must be not greater than 0.6 x V

REF

11.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

OPER

NOTE :

1. Operating Temperature T JESD51-2.

2. The Normal Temperature Range specifies the temperatures where al tained between 0-85°C u

3. Some applications require operation of the Extended Temperature Range between 85°C following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing

to 7.8us) in the Extended Temperature Range.

b) If Self-Refresh operation is required in the Extended Temperat

Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b)

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

nder all operating conditions

Operating Temperature Range 0 to 95 °C 1, 2, 3

l DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI

ure Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1

, When VDD and V

DDQ

and 95°C case temperature. Full specifications are guaranteed in this range, but the

are less than 500mV; V

DDQ

REF

may be

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions (SSTL-15)

Symbol Parameter Operation Voltage

DDQ

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

3. V

& V

DDQ

Supply Voltage

Supply Voltage for Output

must be less than or equal to VDD.

DDQ

rating are determinied by operation voltage.

1.35V 1.2825 1.35 1.4500 V 1, 2, 3

1.5V 1.425 1.5 1.575 V 1, 2, 3

1.35V 1.2825 1.35 1.4500 V 1, 2, 3

1.5V 1.425 1.5 1.575 V 1, 2, 3

tied together.

DDQ

Min. Typ. Max.

Rating

Units NOTE

- 15 -

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13. AC & DC Input Measurement Levels

13.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 2 ] Single Ended AC and DC input levels for Command and Address

Symbol Parameter

(DC)

IH.CA

(DC)

IL.CA

IH.CA

(AC)

IL.CA

(AC135)

IH.CA

(AC135)

IL.CA

REFCA

IH.CA

(DC)

IL.CA

IH.CA

(AC)

IL.CA

(AC150)

IH.CA

(AC150)

IL.CA

REFCA

NOTE :

1. For input only pins except RESET

2. See "Overshoot and Undershoot specifications" section.

3. The AC peak noise on V

4. For reference : approx. V

DC input logic high

DC input logic low

(AC)

AC input logic high

AC input logic low -

AC input logic high - -

AC input logic lowM - - -

Reference Voltage for ADD,

(DC)

CMD inputs

(DC)

DC input logic high

DC input logic low

(AC)

AC input logic high

AC input logic low -

AC input logic high - -

AC input logic lowM - - -

Reference Voltage for ADD,

(DC)

CMD inputs

, V

may not allow V

REF

/2 ± 15mV

REF

= V

(DC)

REFCA

to deviate from V

REF

DDR3-800/1066 DDR3-1333/1600

Min. Max. Min. Max.

1.35V

+ 90 V

REF

+ 160

REF

0.49*V

- 90 V

REF

- 160

REF

0.51*V

1.5V

+ 100 V

REF

+ 175

REF

0.49*V

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

- 100 V

REF

- 175

REF

0.51*V

+ 90 V

REF

+ 160

REF

+135

REF

0.49*V

+ 100 V

REF

+ 175

REF

+150

REF

0.49*V

Unit NOTE

- 90

REF

mV 1

-mV1,2

REF

- 160

mV 1,2

-mV1,2

REF

0.51*V

REF

-135

- 100

mV 1,2

V3,4

mV 1

-mV1,2

REF

- 175

mV 1,2

-mV1,2

REF

0.51*V

-150

mV 1,2

V3,4

[ Table 3 ] Single Ended AC and DC input levels for DQ and DM

Symbol Parameter

(DC)

IH.DQ

IL.DQ

IH.DQ

IL.DQ

REF

IH.DQ

IL.DQ

IH.DQ

IL.DQ

REF

(AC135)

DC input logic high

(DC)

DC input logic low

(AC)

AC input logic high

(AC)

AC input logic low Note 2

AC input logic high

AC input logic low Note 2

Reference Voltage for DQ,

(DC)

DM inputs

(DC)

DC input logic high

(DC)

DC input logic low

(AC)

AC input logic high

(AC)

AC input logic low -

(DC)

I/O Reference Voltage(DQ)

DDR3-800/1066 DDR3-1333/1600

Min. Max. Min. Max.

+ 90 V

REF

+ 160

REF

+ 135

REF

0.49*V

+ 100 V

REF

+ 175

REF

0.49*V

Unit NOTE

1.35V

- 90 V

REF

Note 2

- 160

REF

+ 90 V

REF

+ 135

REF

Note 2

- 90

REF

Note 2 mV 1,2,5

- 135

REF

mV 1

mV 1,2,5

Note 2 - - mV 1,2,5

REF

0.51*V

- 135

--mV1,2,5

0.49*V

0.51*V

V3,4

1.5V

- 100 V

REF

- 175

REF

0.51*V

+ 100 V

REF

+ 150

REF

0.49*V

- 100

REF

- mV 1,2,5

- 150

REF

0.51*V

mV 1

mV 1,2,5

V3,4

- 16 -

Rev. 1.0

voltage

time

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NOTE :

1. For input only pins except RESET

2. See "Overshoot and Undershoot specifications" section.

3. The AC peak noise on V

4. For reference : approx. V

5. Single ended swing requirement for DQS - DQS

13.2 V

Tolerances

REF

, V

may not allow V

REF

/2 ± 15mV

REF

= V

(DC)

REFDQ

to deviate from V

REF

is 350mV (peak to peak). Differential swing requirement for DQS - DQS is 700mV (peak to peak).

datasheet DDR3L SDRAM

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

The dc-tolerance limits and ac-noise limits for the reference voltages V V

(t) as a function of time. (V

REF

(DC) is the linear average of V

REF

thermore V

(t) may temporarily deviate from V

REF

stands for V

REF

REFCA

and V

REFDQ

likewise).

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V

(DC) by no more than ± 1% VDD.

REF

REFCA

and V

are illustrate in Figure 1. It shows a valid reference voltage

REFDQ

REF

. Fur-

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that dc-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

Timing and voltage effects due to ac-noise on V

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

ac-noise.

REF

- 17 -

Rev. 1.0

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

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13.3 AC and DC Logic Input Levels for Differential Signals

13.3.1 Differential Signals Definition

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

Symbol Parameter

IHdiff

ILdiff

(AC)

IHdiff

(AC)

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK level is used for a signal group, then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK

[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.

use VIH/VIL(AC) of ADD/CMD and V

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

Slew Rate [V/ns]

differential input high +0.2 NOTE 3 V 1

differential input low NOTE 3 -0.2 V 1

differential input high ac

differential input low ac NOTE 3

; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and V

REFCA

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163 -

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

2 x (VIH(AC)-V

tDVAC [ps] @ |V

min max min max

DDR3-800/1066/1333/1600

min max

)

REF

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,

(AC)| = 350mV tDVAC [ps] @ |V

IH/Ldiff

NOTE 3 V 2

2 x (V

- VIL(AC))

REF

unit NOTE

; if a reduced ac-high or ac-low

REFDQ

(AC)| = 300mV

IH/Ldiff

- 18 -

Rev. 1.0

VDD or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

VSS or V

SSQ

SEL

CK or DQS

time

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13.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK

half-cycle. DQS, DQSL, DQSU, DQS

proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

signals, then these ac-levels apply also for the single-ended signals CK and CK

have to approximately reach V

, DQSL have to reach V

SEH

min / V

SEH

max (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every

SEL

min / V

max (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle

SEL

150(AC)/VIL150(AC) is used for ADD/CMD

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

with respect to V

ended components of differential signals the requirement to reach V mode characteristics of these signals.

[ Table 5 ] Single ended levels for CK, DQS, DQSL, DQSU, CK

Symbol Parameter

SEH

SEL

NOTE :

1. For CK, CK

2. V

(AC)/VIL(AC) for DQs is based on V

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes NOTE 3

Single-ended low-level for CK, CK

use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.

; VIH(AC)/VIL(AC) for ADD/CMD is based on V

REFDQ

, the single-ended components of differential signals have a requirement

REF

max, V

SEL

, DQS, DQSL or DQSU

(VDD/2)+0.175

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,

min has no bearing on timing, but adds a restriction on the common

SEH

DDR3-800/1066/1333/1600

Min Max

/2)+0.175

NOTE 3

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

NOTE 3 V 1, 2

/2)-0.175

Unit NOTE

V1, 2

- 19 -

Rev. 1.0

CK, DQS

VDD/2

CK, DQS

IHdiffmin

ILdiffmax

delta TRdiff

delta TFdiff

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13.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK

cross point of true and complement signal to the mid level between of V

[ Table 6 ] Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

NOTE :

1. Extended range for V

±250 mV, and the differential slew rate of CK-CK

and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

and VSS.

Figure 4. VIX Definition

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V

is larger than 3 V/ ns.

DDR3-800/1066/1333/1600

Min Max

-150 150 mV

-175 175 mV 1

-150 150 mV

SEL

/ V

Unit NOTE

of at least VDD/2

SEH

13.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

13.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 7 ] Differential input slew rate definition

Description

Differential input slew rate for rising edge (CK-CK

Differential input slew rate for falling edge (CK-CK

NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

and DQS-DQS)

Measured

From To

ILdiffmax

IHdiffmin

ILdiffmax

Defined by

IHdiffmin

Delta TRdiff

IHdiffmin

Delta TFdiff

- V

ILdiffmax

Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK

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14. AC & DC Output Measurement Levels

14.1 Single Ended AC and DC Output Levels

[ Table 8 ] Single Ended AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE

(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

(AC) AC output high measurement level (for output SR) VTT + 0.1 x V

(AC) AC output low measurement level (for output SR) VTT - 0.1 x V

NOTE : 1. The swing of +/-0.1 x V

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2.

DDQ

14.2 Differential AC and DC Output Levels

[ Table 9 ] Differential AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE

(AC) AC differential output high measurement level (for output SR) +0.2 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.2 x V

OLdiff

NOTE : 1. The swing of +/-0.2xV

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2 at each of the differential outputs.

DDQ

14.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)

for single ended signals as shown in below.

[ Table 10 ] Single ended Output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 11 ] Single ended output slew rate

Parameter Symbol

Single ended output slew rate SRQse

Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals, For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

Operation

Vol tag e

1.35V 1.75

1.5V 2.5 5 2.5 5 2.5 5 TBD 5 V/ns

Measured

From To

(AC) VOH(AC)

(AC) VOL(AC)

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Min Max Min Max Min Max Min Max

1.75

- - TBD TBD V/ns

Defined by

(AC)-VOL(AC)

Delta TRse

(AC)-VOL(AC)

Delta TFse

Units

- 21 -

Rev. 1.0

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

VTT

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

VTT

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Figure 6. Single-ended output slew rate definition

14.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) for differential signals as shown in below.

diff

[ Table 12 ] Differential Output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OLdiff

(AC)

OHdiff

Defined by

(AC)-V

OLdiff

Delta TRdiff

(AC)-V

OLdiff

Delta TFdiff

(AC)

(AC) and V

OLdiff

OH-

[ Table 13 ] Differential Output slew rate

Parameter Symbol

Single ended output slew rate SRQse

Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Single-ended Signals For Ron = RZQ/7 setting

Operation

Vol tag e

1.35V 3.5 10 3.5 10 - - TBD TBD V/ns

1.5V 5 10 5 10 5 10 TBD 10 V/ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Min Max Min Max Min Max Min Max

Figure 7. Differential output slew rate definition

Units

- 22 -

Rev. 1.0

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15. IDD specification definition

Symbol Description

Operating One Bank Active-Precharge Current

IDD0

IDD1

IDD2N

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

IDD6ET

IDD7

IDD8

CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers tern

Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

tern

Precharge Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

Registers

Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0

Active Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

Registers

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

Signal: stable at 0

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at HIGH

Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers

Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Self-Refresh Current: Extended Temperature Range (optional) TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK: LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

Enabled in Mode Registers

RESET Low Current RESET : Low; External clock : off; CK and CK

FLOATING

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

; Pattern Details: Refer to Component Datasheet for detail pattern

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

; Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

: LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

; AL: 0; CS: High between ACT and PRE;

; AL: 0; CS: High between ACT, RD

; AL: 0; CS: stable at 1; Command, Address, Bank

; AL: 0; CS: High between RD; Command, Address,

; ODT Signal: stable

; AL: 0; CS: High between WR; Command, Address,

; ODT Signal: stable

; AL: 0; CS: High between REF; Command,

; ODT Signal: FLOATING

; AL: CL-1; CS: High

; ODT

;

- 23 -

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NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7) IDD current measure method and detail patterns are described on DDR3 component datasheet

8) VDD and VDDQ are merged on module PCB.

9) DIMM IDD SPEC is measured with Qoff condition

(IDDQ values are not considered)

datasheet DDR3L SDRAM

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datasheet DDR3L SDRAM

16. IDD SPEC Table

M392B2873FH0 : 1GB(128Mx72) Module

DDR3-1066 DDR3-1333

Symbol

1.35V 1.5V 1.35V 1.5V

IDD0 1030 1075 1115 1160 mA 1

IDD1 1120 1165 1205 1250 mA 1

IDD2P0(slow exit) 660 660 700 700 mA

IDD2P1(fast exit) 705 750 745 790 mA

IDD2N 820 865 905 905 mA

IDD2Q 800 845 840 885 mA

IDD3P(fast exit) 795 795 835 835 mA

IDD3N 990 1035 1075 1120 mA

IDD4R 1390 1435 1520 1610 mA 1

IDD4W 1400 1490 1575 1665 mA 1

IDD5B 1620 1665 1660 1705 mA 1

IDD6 650 650 690 690 mA

IDD7 1885 1975 2195 2285 mA 1

IDD8 650 650 690 690 mA

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

Unit NOTE7-7-7 9-9-9

M392B5673FH0 : 2GB(256Mx72) Module

DDR3-1066 DDR3-1333

Symbol

1.35V 1.5V 1.35V 1.5V

IDD0 1210 1300 1340 1385 mA 1

IDD1 1345 1390 1430 1475 mA 1

IDD2P0(slow exit) 750 750 790 790 mA

IDD2P1(fast exit) 840 930 880 970 mA

IDD2N 1000 1090 1130 1130 mA

IDD2Q 980 1070 1020 1110 mA

IDD3P(fast exit) 1020 1020 1060 1060 mA

IDD3N 1350 1440 1480 1570 mA

IDD4R 1570 1660 1745 1835 mA 1

IDD4W 1580 1715 1800 1890 mA 1

IDD5B 1800 1890 1885 1930 mA 1

IDD6 740 740 780 780 mA

IDD7 2065 2200 2420 2510 mA 1

IDD8 740 740 780 780 mA

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

Unit NOTE7-7-7 9-9-9

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datasheet DDR3L SDRAM

M392B5670FH0 : 2GB(256Mx72) Module

DDR3-1066 DDR3-1333

Symbol

1.35V 1.5V 1.35V 1.5V

IDD0 1390 1480 1520 1610 mA 1

IDD1 1570 1660 1700 1790 mA 1

IDD2P0(slow exit) 750 750 790 790 mA

IDD2P1(fast exit) 840 930 880 970 mA

IDD2N 1000 1090 1130 1130 mA

IDD2Q 980 1070 1020 1110 mA

IDD3P(fast exit) 1020 1020 1060 1060 mA

IDD3N 1350 1440 1480 1570 mA

IDD4R 2020 2200 2240 2420 mA 1

IDD4W 2030 2210 2250 2430 mA 1

IDD5B 2610 2700 2650 2740 mA 1

IDD6 740 740 780 780 mA

IDD7 3010 3190 3500 3680 mA 1

IDD8 740 740 780 780 mA

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

Unit NOTE7-7-7 9-9-9

M392B5170FM0 : 4GB(512Mx72) Module

DDR3-1066 DDR3-1333

Symbol

1.35V 1.5V 1.35V 1.5V

IDD0 1750 1930 1970 2060 mA 1

IDD1 2020 2110 2150 2240 mA 1

IDD2P0(slow exit) 930 930 970 970 mA

IDD2P1(fast exit) 1110 1290 1150 1330 mA

IDD2N 1360 1540 1580 1580 mA

IDD2Q 1340 1520 1380 1560 mA

IDD3P(fast exit) 1470 1470 1510 1510 mA

IDD3N 2070 2250 2290 2470 mA

IDD4R 2380 2650 2690 2870 mA 1

IDD4W 2390 2660 2700 2880 mA 1

IDD5B 2970 3150 3100 3190 mA 1

IDD6 920 920 960 960 mA

IDD7 3370 3640 3950 4130 mA 1

IDD8 920 920 960 960 mA

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

Unit NOTE7-7-7 9-9-9

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datasheet DDR3L SDRAM

17. Input/Output Capacitance

M392B2873FH0

Parameter Symbol

Min Max Min Max

Input/output capacitance (DQ, DM, DQS, DQS

Input capacitance (CK and CK)

Input capacitance (All other input-only pins) CI - TBD - TBD pF

Input/output capacitance of ZQ pin CZQ - TBD - TBD pF

Input/output capacitance (DQ, DM, DQS, DQS

Input capacitance (CK and CK)

Input capacitance (All other input-only pins) CI - TBD - TBD pF

Input/output capacitance of ZQ pin CZQ - TBD - TBD pF

, TDQS, TDQS)

Parameter Symbol

, TDQS, TDQS)

CIO - TBD - TBD pF

CCK - TBD - TBD pF

M392B5673FH0

Min Max Min Max

CIO - TBD - TBD pF

CCK - TBD - TBD pF

Units NOTEDDR3-1066 DDR3-1333

M392B5670FH0

Parameter Symbol

Min Max Min Max

Input/output capacitance (DQ, DM, DQS, DQS

Input capacitance (CK and CK)

Input capacitance (All other input-only pins) CI - TBD - TBD pF

Input/output capacitance of ZQ pin CZQ - TBD - TBD pF

Input/output capacitance (DQ, DM, DQS, DQS

Input capacitance (CK and CK)

Input capacitance (All other input-only pins) CI - TBD - TBD pF

Input/output capacitance of ZQ pin CZQ - TBD - TBD pF

, TDQS, TDQS)

Parameter Symbol

, TDQS, TDQS)

CIO - TBD - TBD pF

CCK - TBD - TBD pF

M392B5170FM0

Min Max Min Max

CIO - TBD - TBD pF

CCK - TBD - TBD pF

Units NOTEDDR3-1066 DDR3-1333

- 27 -

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datasheet DDR3L SDRAM

18. Electrical Characteristics and AC timing

[0 °C<T

18.1 Refresh Parameters by Device Density

All Bank Refresh to active/refresh cmd time tRFC 110 160 300 350 ns

Average periodic refresh interval tREFI

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

≤95 °C, V

CASE

Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Parameter min min min min

CL 6 7911tCK

tRCD 15 13.13 13.5 13.75 ns

tRP 15 13.13 13.5 13.75 ns

tRAS 37.5 37.5 36 35 ns

tRC 52.5 50.63 49.5 48.75 ns

tRRD 10 7.5 6.0 6.0 ns

tFAW 40 37.5 30 30 ns

= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]

DDQ

0 °C ≤ T

85 °C < T

CASE

≤ 85°C

≤ 95°C

7.8 7.8 7.8 7.8 μs

3.9 3.9 3.9 3.9 μs 1

Units NOTEBin (CL - tRCD - tRP) 6-6-6 7-7-7 9-9-9 11- 11-11

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 14 ] DDR3-800 Speed Bins

Speed DDR3-800

Units NOTECL-nRCD-nRP 6 - 6 - 6

Parameter Symbol min max

Internal read command to first data tAA 15 20 ns

ACT to internal read or write delay time tRCD 15 - ns

PRE command period tRP 15 - ns

ACT to ACT or REF command period tRC 52.5 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns 8

CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3

Supported CL Settings 6 nCK

Supported CWL Settings 5 nCK

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[ Table 15 ] DDR3-1066 Speed Bins

Speed DDR3-1066

Parameter Symbol min max

Internal read command to first data tAA 13.125 20 ns

ACT to internal read or write delay time tRCD 13.125 - ns

PRE command period tRP 13.125 - ns

ACT to ACT or REF command period tRC 50.625 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns 8

CL = 6

CL = 7

CL = 8

Supported CL Settings 6,7,8 nCK

Supported CWL Settings 5,6 nCK

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3

datasheet DDR3L SDRAM

Units NOTECL-nRCD-nRP 7 - 7 - 7

[ Table 16 ] DDR3-1333 Speed Bins

Speed DDR3-1333

Units NOTECL-nRCD-nRP 9 -9 - 9

Parameter Symbol min max

Internal read command to first data tAA 13.5 (13.125)

ACT to internal read or write delay time tRCD 13.5 (13.125)

PRE command period tRP 13.5 (13.125)

ACT to ACT or REF command period tRC 49.5 (49.125)

ACT to PRE command period tRAS 36 9*tREFI ns 8

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

Supported CL Settings 6,7,8,9 nCK

Supported CWL Settings 5,6,7 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 7 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG)

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG)

5,9

1.875 <2.5

(Optional) NOTE 5,9

1.5 <1.875 ns 1,2,3

(Optional) ns 5

20 ns

- ns

ns 1,2,3,4,7

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[ Table 17 ] DDR3-1600 Speed Bins

Speed DDR3-1600

Parameter Symbol min max

Intermal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 35 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

CL = 11

Supported CL Settings 6,7,8,9,10,11 nCK

Supported CWL Settings 5,6,7,8 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 7, 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG)

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG)

CWL = 8 tCK(AVG) TBD ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG)

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,5

datasheet DDR3L SDRAM

Units NOTECL-nRCD-nRP 11-11-11

13.75

(13.125)

(48.125)

5,9

13.75

5,9

13.75

5,9

48.75

5,9

1.875 <2.5

(Optional) NOTE 5,9

1.5 <1.875

(Optional) NOTE 9,10

1.5 <1.875

(Optional) NOTE 9,10

20 ns

- ns

ns 1,2,3,4,8

ns 1,2,3,8

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datasheet DDR3L SDRAM

18.3.1 Speed Bin Table Notes

Absolute Specification [T

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/or the DIMM SPD

information if and how this setting is supported.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).

OPER

; V

= VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];

DDQ

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datasheet DDR3L SDRAM

19. Timing Parameters by Speed Grade

[ Table 18 ] Timing Parameters by Speed Bin

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period tCK(avg) See Speed Bins Table ps

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 ps

Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 ps

Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 ps

Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 ps

Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 ps

Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 ps

Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 ps

Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 ps

Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 ps

Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 ps

Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 ps

Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 ps

Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 - 100 ps 13

DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 -450 225 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 - 225 ps 13,14, f

Data setup time to DQS, DQS referenced to V

(AC)VIL(AC) levels

Data hold time from DQS, DQS referenced to VIH(AC)VIL(AC) levels

Data setup time to DQS, DQS referenced to

(AC)VIL(AC) levels

DQ and DM Input pulse width for each input tDIPW 600

Data Strobe Timing

DQS, DQS differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK 11, 13, b

DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - 0.9 - tCK

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - 0.3 - tCK

DQS, DQS rising edge output access time from rising CK, CK

DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 -450 225 ps 13,14,f

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - 0.18 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - 0.18 - tCK(avg) c, 32

tCK(DLL_OF

tDS(base) 90

tDH(base) 160

tDS(base)

AC135

tDQSCK -400 400 -300 300 -255 255 -225 225 ps 13,f

tHZ(DQS) - 400 - 300 - 250 - 225 ps 12,13,14

8 - 8 - 8 - 8 - ns 6

tCK(avg)min +

tJIT(per)min

140

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

110

490

tCK(avg)min +

tJIT(per)min

- - - - ps d, 17

- - - - ps

400

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

360

tCK(avg)max +

tJIT(per)max

Units NOTE

ps 24

ps 28

- 32 -

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VLP Registered DIMM

datasheet DDR3L SDRAM

[ Table 18 ] Timing Parameters by Speed Bin (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX

Command and Address Timing

DLL locking time tDLLK 512 - 512 - 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay

Delay from start of internal write transaction to internal read command

WRITE recovery time tWR 15 - 15 - 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - nCK

Mode Register Set command update delay tMOD

CAS# to CAS# command delay tCCD 4 - 4 - 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - 30 - ns e

Four activate window for 2KB page size tFAW 50 - 50 - 45 - 40 - ns e

Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels

Command and Address hold time from CK, CK referenced to VIH(AC) / VIL(AC) levels

Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels

Control & Address Input pulse width for each input tIPW 900

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - nCK

Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 - nCK

Normal operation short calibration time tZQCS 64 - 64 - 64 - 64 - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit

tRTP

tWTR

tIS(base) 215

tIH(base) 285

tIS(base)

AC135

tXS

tCKESR

tCKSRE

tCKSRX

max

(4nCK,7.5ns)-

max

(4nCK,7.5ns)-

max

(12nCK,15ns

)

max

(4nCK,10ns)

max

(4nCK,10ns)

365

max(5nCK,

tRFC + 10ns)

max(5nCK,t

RFC + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

max

(4nCK,7.5ns)-

max

(4nCK,7.5ns)-

max

(12nCK,15ns

)

max

(4nCK,7.5ns)-

max

(4nCK,10ns)

140

210

290

780

max(5nCK,

tRFC + 10ns)

max(5nCK,t

RFC + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

(4nCK,7.5ns)-

(12nCK,15ns

(4nCK,6ns)

(4nCK,7.5ns

max(5nCK,

tRFC + 10ns)

max(5nCK,t

RFC + 10ns)

tCKE(min) +

max(5nCK,

max

)

max

)

80 - 60 - ps b,16

150 - 130 - ps b,16

205 - 185 - ps b,16,27

620 - 560 - ps 28

1tCK

10ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns

)

max

(4nCK,6ns)

max

(4nCK,7.5ns)

max(5nCK,

tRFC + 10ns)

max(5nCK,tR

FC + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

Units NOTE

- e

- e,18

- e

- 33 -

Rev. 1.0

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

[ Table 18 ] Timing Parameters by Speed Bin (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 1 - 1 - 1 - 1 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF)

Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF)

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) -

ODT Timing

ODT high time without write command or with write command and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - nCK

Asynchronous RTT turn-on delay (Power-Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-Down with DLL frozen)

RTT turn-on tAON -400 400 -300 300 -250 250 -225 225 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Write leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing

Write leveling hold time from rising DQS, DQS crossing to rising CK, CK

Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 ns

Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns

crossing

tXP

tXPDLL

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

ODTH4 4 - 4 - 4 - 4 - nCK

tAONPD 2 8.5 2 8.5 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 2 8.5 2 8.5 ns

tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f

tWLMRD 40 - 40 - 40 - 40 - tCK 3

tWLDQSEN 25 - 25 - 25 - 25 - tCK 3

tWLH 325 - 245 - 195 - 165 - ps

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

7.5ns)

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2 +WR

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2 +WR

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2 +WR

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,5ns)

WL + 4 +(tWR/

tCK(avg))

WL + 4 +WR

WL + 2 +(tWR/

tCK(avg))

WL +2 +WR

Units NOTE

- 2

- nCK 9

- nCK 10

- nCK 9

- nCK 10

- 34 -

Rev. 1.0

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

19.1 Jitter Notes

Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b These parameters are measured from a command/address signal (CKE, CS

edge to its respective clock signal (CK/CK tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.

Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS

crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data

strobe signal (DQS(L/U), DQS

Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

(L/U)) crossing.

) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

(L/U)) crossing to its respective clock signal (CK, CK)

Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/ max usage!)

- 35 -

Rev. 1.0

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

0.5

(1.5 x 1) + (0.15 x 15)

= 0.133

128ms

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

19.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

(DC) = V

REF

See ?$paratext>? on page 48. .

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

(DC)= V

REF

See ?$paratext>? on page 54.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram

Datasheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

OPER

DQ(DC). FOr input only pins except RESET, V

REF

DQ(DC). For input only pins except RESET, V

REF

(DC)=V

REF

CA(DC).

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-

nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS

30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

(DC) and the consecutive crossing of V

REF

, as measured from one falling edge to the next consecutive rising edge.

- 36 -

REF

(DC)

Rev. 1.0

133.35 ± 0.15

Units : Millimeters

18.10

12.60

47.00

71.00

128.95

9.76 20.92 32.40 20.93 9.74

SPD/TS

1.00

0.2 ± 0.15

2.50 ± 0.20

Detail B

5.00

Detail A

1.50±0.10

0.80 ± 0.05

3.80

2.50

9.9

0.6

R 0

Detail C

18.75 ± 0.15

54.675

1.27 ± 0.10

1.0 max

Max 4.0

The used device is 128M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B1G0846F-HY**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

NOTE : DRAMs indicated with dotted outline are located on the backside of the module.

Address, Command and Control lines

VTT

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

20. Physical Dimensions

20.1 128Mbx8 based 128Mx72 Module (1 Rank) - M392B2873FH0

20.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

- 37 -

Rev. 1.0

133.35 ± 0.15

Units : Millimeters

18.10

12.60

1.27 ± 0.10

1.0 max

47.00

71.00

128.95

9.76 20.92 32.40 20.93 9.74

SPD/TS

1.00

0.2 ± 0.15

2.50 ± 0.20

Detail B

5.00

Detail A

1.50±0.10

0.80 ± 0.05

3.80

2.50

9.9

0.6

R 0

Detail C

18.75 ± 0.15

54.675

Max 4.0

The used device is 128M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B1G0846F-HY**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

VTT

SPD/TS

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

20.2 128Mbx8 based 256Mx72 Module (2 Ranks) - M392B5673FH0

20.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

- 38 -

Rev. 1.0

133.35 ± 0.15

Units : Millimeters

18.10

12.60

1.27 ± 0.10

1.0 max

47.00

71.00

128.95

9.76 20.92 32.40 20.93 9.74

SPD/TS

1.00

0.2 ± 0.15

2.50 ± 0.20

Detail B

5.00

Detail A

1.50±0.10

0.80 ± 0.05

3.80

2.50

9.9

0.6

Detail C

18.75 ± 0.15

54.675

Max 4.0

The used device is 256M x4 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B1G0446F-HY**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

VTT

SPD/TS

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

20.3 256Mbx4 based 256Mx72 Module (1 Rank) - M392B5670FH0

20.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

- 39 -

Rev. 1.0

Units : Millimeters

18.10

12.60

47.00

71.00

20.93 9.74

SPD/TS

1.00

0.2 ± 0.15

2.50 ± 0.20

Detail B

5.00

Detail A

1.50±0.10

0.80 ± 0.05

3.80

2.50

9.9

0.6

R 0.50

Detail C

18.75 ± 0.15

54.675

1.27 ± 0.10

1.0 max

Max 4.0

133.35 ± 0.15

128.95

9.76 20.92 32.40

The used device is 512M x4(DDP) DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0446F-MY**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

VTT

SPD/TS

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

20.4 512Mbx4(DDP) based 512Mx72 Module (2 Ranks) - M392B5170FM0

20.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

- 40 -

Rev. 1.0

1. FRONT PART

Outside

Inside

2. BACK PART

14.3

DRIVER IC 0.18 -0/+0.1

130.45

20.82 17.9 6.4 20.82 8.698.69

Driver IC(DP:0.18mm)

0.4

Driver IC(DP:0.18mm)

Outside

Inside

Driver IC(DP:0.18mm)

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

20.4.2 Heat Spreader Design Guide

datasheet DDR3L SDRAM

- 41 -

Rev. 1.0

3. CLIP PART

4. ASS’Y VIEW

7.55

TIM Thickness 0.25

9.16

35.82

7.2

± 0.1

9.16

± 0.12

Clip open size

3.0~4.3

SIDE-L

7.2

± 0.1

9.16

± 0.12

0.1

SIDE-RFRONT

Reference thickness total (Maximum) : 7.55 (With Clip thickness)

http://www.BDTIC.com/SAMSUNG

VLP Registered DIMM

datasheet DDR3L SDRAM

- 42 -

Datasheet M392B2873FH0 Datasheet (SAMSUNG)

Specifications and Main Features

Frequently Asked Questions

User Manual

1. DDR3L VLP Registered DIMM Ordering Information

2. Key Features

3. Address Configuration

4. Registered DIMM Pin Configurations (Front side/Back side)

5. Pin Description

6. ON DIMM Thermal Sensor

7. Input/Output Functional Description

8. Pinout Comparison Based On Module Type

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

9.2 Clock driver Characteristics

10. Function Block Diagram:

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

11.2 DRAM Component Operating Temperature Range

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions (SSTL-15)

13. AC & DC Input Measurement Levels

13.1 AC & DC Logic Input Levels for Single-ended Signals

13.3 AC and DC Logic Input Levels for Differential Signals

13.3.1 Differential Signals Definition

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

13.3.3 Single-ended Requirements for Differential Signals

13.3.4 Differential Input Cross Point Voltage

13.4 Slew Rate Definition for Single Ended Input Signals

13.5 Slew rate definition for Differential Input Signals

14. AC & DC Output Measurement Levels

14.1 Single Ended AC and DC Output Levels

14.2 Differential AC and DC Output Levels

14.3 Single-ended Output Slew Rate

14.4 Differential Output Slew Rate

15. IDD specification definition

16. IDD SPEC Table

17. Input/Output Capacitance

18. Electrical Characteristics and AC timing

18.1 Refresh Parameters by Device Density

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

18.3.1 Speed Bin Table Notes

19. Timing Parameters by Speed Grade

19.1 Jitter Notes

19.2 Timing Parameter Notes

20. Physical Dimensions

20.1 128Mbx8 based 128Mx72 Module (1 Rank) - M392B2873FH0

20.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

20.2 128Mbx8 based 256Mx72 Module (2 Ranks) - M392B5673FH0

20.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

20.3 256Mbx4 based 256Mx72 Module (1 Rank) - M392B5670FH0

20.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

20.4 512Mbx4(DDP) based 512Mx72 Module (2 Ranks) - M392B5170FM0

20.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

20.4.2 Heat Spreader Design Guide