查询M366S1723DTS供应商
M366S1723DTS
PC133/PC100 Unbuffered DIMM
M366S1723DTS SDRAM DIMM
16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
FEATUREGENERAL DESCRIPTION
The Samsung M366S1723DTS is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S1723DTS consists of eight CMOS 16M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. One 0.1uF and one 0.22 uF decoupling capacitors
are mounted on the printed circuit board in parallel for each
SDRAM.
The M366S1723DTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
• Performance range
Part No. Max Freq. (Speed)
M366S1723DTS-C/L7C 133MHz (7.5ns @ CL=2)
M366S1723DTS-C/L7A 133MHz (7.5ns @ CL=3)
M366S1723DTS-C/L1H 100MHz (10ns @ CL=2)
M366S1723DTS-C/L1L 100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), single sided component
PIN CONFIGURATIONS (Front side/back side)
CS0
DU
VSS
A0
A2
A4
A6
A8
BA1
VDD
VDD
VSS
DU
CS2
DU
VDD
NC
NC
VSS
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
*VREF
*CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
NC
**SDA
**SCL
VDD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
*CB4
*CB5
VSS
NC
NC
VDD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
*CLK1
*A12
VSS
CKE0
*CS3
DQM6
DQM7
*A13
VDD
NC
NC
*CB6
*CB7
VSS
DQ48
DQ49
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
*CB0
*CB1
VSS
NC
NC
VDD
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
A10/AP
CLK0
DQM2
DQM3
*CB2
*CB3
DQ16
DQ17
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
DQ52
NC
*VREF
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
*CLK3
NC
**SA0
**SA1
**SA2
VDD
PIN NAMES
Pin Name Function
A0 ~ A11 Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CLK0, CLK2 Clock input
CKE0 Clock enable input
CS0, CS2 Chip select input
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 7 DQM
VDD Power supply (3.3V)
VSS Ground
*VREF Power supply for reference
SDA Serial data I/O
SCL Serial clock
SA0 ~ 2 Address in EEPROM
DU Don′t use
NC No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M366S1723DTS
PC133/PC100 Unbuffered DIMM
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select
CKE Clock enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11 Address
BA0 ~ BA1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 7 Data input/output mask
DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Rev. 0.1 Sept. 2001
M366S1723DTS
FUNCTIONAL BLOCK DIAGRAM
PC133/PC100 Unbuffered DIMM
CS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS2
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM4
DQM CS
U0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQM5
DQM CS
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
•
DQM6
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
U2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQM CS
U3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
A0 ~ An, BA0 & 1
RAS
CAS
WE
CKE0
DQn
VDD
Vss
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
10Ω
Every DQpin of SDRAM
••
One 0.1uF and one 0.22 uF Cap.
per each SDRAM
•
•
To all SDRAMs
CLK0/2
CLK1/3
SCL
47K
Serial PD
WP
•
3.3pF
A1 A2A0
SA1 SA2SA0
U0/U2
•
U4/U6
U1/U3
•
•
U5/U7
Ω
10Ω
10Ω
10pF
Rev. 0.1 Sept. 2001
SDA
M366S1723DTS
PC133/PC100 Unbuffered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 8 W
Short circuit current IOS 50 mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin Symbol Min Max Unit
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
CKE (CKE0)
Clock (CLK0, CLK2)
CS (CS0, CS2)
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CADD
CIN
CCKE
CCLK
CCS
CDQM
COUT
25
25
25
15
15
8
9
45
45
45
21
25
12
12
pF
pF
pF
pF
pF
pF
pF
Rev. 0.1 Sept. 2001
M366S1723DTS
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
PC133/PC100 Unbuffered DIMM
Parameter Symbol Test Condition
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Version
- 7C -7A -1H -1L
Burst length = 1
ICC1
ICC2P CKE ≤ VIL(max), tCC = 10ns 16
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 16
ICC2N
ICC2NS
ICC3P CKE ≤ VIL(max), tCC = 10ns 40
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 40
ICC3N
ICC3NS
ICC4
tRC ≥ tRC(min)
IO = 0 mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
800 720 720 720 mA 1
160
80
240 mA
200 mA
880 880 800 800 mA 1
Unit Note
mA
mA
mA
Refresh current ICC5 tRC ≥ tRC(min) 1760 1600 1520 1520 mA 2
Self refresh current ICC6 CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
C 16
L 6.4
mA
Rev. 0.1 Sept. 2001
M366S1723DTS
PC133/PC100 Unbuffered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
Output
870Ω
3.3V
1200Ω
•• •
50pF
•
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
Vtt = 1.4V
50Ω
50pF
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Symbol
Row active to row active delay tRRD(min) 15 15 20 20 ns 1
RAS to CAS delay tRCD(min) 15 20 20 20 ns 1
Row precharge time tRP(min) 15 20 20 20 ns 1
Row active time
Row cycle time tRC(min) 60 65 70 70 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2,5
Last data in to Active delay tDAL(min) 2 CLK + tRP - 5
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid output data
CAS latency=3 2
CAS latency=2 1
tRAS(min) 45 45 50 50 ns 1
tRAS(max) 100 us
- 7C - 7A - 1H -1L
Version
Unit Note
ea 4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept. 2001
M366S1723DTS
PC133/PC100 Unbuffered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter Symbol
CLK cycle
time
CLK to valid
output delay
Output data
hold time
CLK high pulse width tCH 2.5 2.5 3 3 ns 3
CLK low pulse width tCL 2.5 2.5 3 3 ns 3
Input setup time tSS 1.5 1.5 2 2 ns 3
Input hold time tSH 0.8 0.8 1 1 ns 3
CLK to output in Low-Z tSLZ 1 1 1 1 ns 2
CLK to output
in Hi-Z
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
CAS latency=3
CAS latency=2 7.5 10 10 12
CAS latency=3
CAS latency=2 5.4 6 6 7
CAS latency=3
CAS latency=2 3 3 3 3
CAS latency=3
CAS latency=2 5.4 6 6 7
tCC
tSAC
tOH
tSHZ
- 7C - 7A - 1H - 1L
Min Max Min Max Min Max Min Max
7.5
1000
5.4 5.4 6 6
3 3 3 3
5.4 5.4 6 6
7.5
1000
10
1000
10
1000 ns 1
Unit Note
ns 1,2
ns 2
ns
Rev. 0.1 Sept. 2001
M366S1723DTS
SIMPLIFIED TRUTH TABLE
PC133/PC100 Unbuffered DIMM
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
Register Mode register set H X L L L L X OP code 1,2
Auto refresh
Refresh
Bank active & row addr. H X L L H H X V Row address
Read &
column address
Write &
column address
Burst stop H X L H H L X X 6
Precharge
Clock suspend or
active power down
Precharge power down mode
DQM H V X 7
No operation command H X
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Self
refresh
Auto precharge disable
Auto precharge enable H 4,5
Auto precharge disable
Auto precharge enable H 4,5
Bank selection
All banks X H
Entry L 3
Exit L H
Entry H L
Exit L H X X X X X
Entry H L
Exit L H
H
H X L H L H X V
H X L H L L X V
H X L L H L X
H
L L L H X X
L H H H
H X X X 3
H X X X
L V V V
H X X X
L H H H
H X X X
L V V V
X
H X X X
L H H H
X X
L
L
V L
X
X
X
X X
A11,
A9 ~ A0
Column
address
(A0 ~ A9)
Column
address
(A0 ~ A9)
X
X
Note
3
3
4
4
X
Rev. 0.1 Sept. 2001
M366S1723DTS
PACKAGE DIMENSIONS
0.118
(3.000)
1.375
(34.925)
0.118
(3.000)
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.350
(8.890)
A
.450
(11.430)
0.250
(6.350)
(36.830)
1.450
5.250
(133.350)
5.014
(127.350)
4.550
(115.57)
PC133/PC100 Unbuffered DIMM
Units : Inches (Millimeters)
0.089
(2.26)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
0.700
(17.780)
B C
0.250
(6.350)
2.150
(54.61)
0.100 Min
(2.540 Min)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
0.100 Max
(2.54 Max)
0.165 Min
(4.19 Min)
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.100 Min
(2.540 Min)
0.008 ±0.006
(0.200 ±0.150)
0.050
(1.270)
Detail C
Tolerances : ± .005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOP
SDRAM Part No. : K4S280832D
Rev. 0.1 Sept. 2001
M366S1723DTS
PC133/PC100 Unbuffered DIMM
M366S1723DTS-L7C/L7A/L1H/L1L,C7C/C7A/C1H/C1L, (Intel SPD 1.2B ver. base)
• Organization : 16Mx64
• Composition : 16Mx8 *8
• Used component part # : K4S280832D-TL7C/TL75/TL1H/TL1L,TC7C/TC75/TC1H/TC1L
• # of rows in module : 1 Row
• # of banks in component : 4 banks
• Feature : 1,375mil height & single sided component
• Refresh : 4K/64ms
• Contents ;
Byte # Function Described
0 # of bytes written into serial memory at module manufacturer 128bytes 80h
1 Total # of bytes of SPD memory device 256bytes (2K-bit) 08h
2 Fundamental memory type SDRAM 04h
3 # of row address on this assembly 12 0Ch 1
4 # of column address on this assembly 10 0Ah 1
5
# of module Rows on this assembly 1 row
6 Data width of this assembly 64 bits 40h
7 ...... Data width of this assembly - 00h
8 Voltage interface standard of this assembly LVTTL 01h
9 SDRAM cycle time @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h 2
10 SDRAM access time from clock @CAS latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2
11 DIMM configuraion type Non parity 00h
12 Refresh rate & type 15.625us, support self refresh 80h
13 Primary SDRAM width x8 08h
14 Error checking SDRAM width None 00h
15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h
16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh
17
SDRAM device attributes : # of banks on SDRAM device 4 banks
18 SDRAM device attributes : CAS latency 2 & 3 2 & 3 2 & 3 2 & 3 06h 06h 06h 06h
19 SDRAM device attributes : CS latency 0 CLK 01h
20 SDRAM device attributes : Write latency 0 CLK 01h
21 SDRAM module attributes
22 SDRAM device attributes : General
23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2
24 SDRAM access time from clock @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2
25 SDRAM cycle time @CAS latency of 1 - 00h
26 SDRAM access time from clock @CAS latency of 1 - 00h
27 Minimum row precharge time (=tRP) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h
28 Minimum row active to row active delay (tRRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h
29 Minimum RAS to CAS delay (=tRCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h
30 Minimum activate precharge time (=tRAS) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h
31
Module Row density 1 row of 128MB
32 Command and address signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h
33 Command and address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h
34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h
Function Supported Hex value
-7C -7A -1H -1L -7C -7A -1H -1L
01h
04h
Non-buffered, non-registered
& redundant addressing
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
00h
0Eh
20h
Note
Rev. 0.1 Sept. 2001
M366S1723DTS
PC133/PC100 Unbuffered DIMM
Byte # Function Described
35 Data signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h
36~61 Superset information (maybe used in future) - 00h
62 SPD data revision code Intel Rev 1.2B 12h
63 Checksum for bytes 0 ~ 62 - 6Eh AFh 16h 46h
64 Manufacturer JEDEC ID code Samsung CEh
65~71 ...... Manufacturer JEDEC ID code Samsung 00h
72 Manufacturing location Onyang Korea 01h
73 Manufacturer part # (Memory module) M 4Dh
74 Manufacturer part # (DIMM Configuration) 3 33h
75 Manufacturer part # (Data bits) Blank 20h
76 ...... Manufacturer part # (Data bits) 6 36h
77 ...... Manufacturer part # (Data bits) 6 36h
78 Manufacturer part # (Mode & operating voltage) S 53h
79 Manufacturer part # (Module depth) 1 31h
80 ...... Manufacturer part # (Module depth) 7 37h
81 Manufacturer part # (Refresh, #of banks in Comp. & Interface) 2 32h
82 Manufacturer part # (Composition component) 3 33h
83 Manufacturer part # (Component revision) D 44h
84 Manufacturer part # (Package type) T 54h
85 Manufacturer part # (PCB revision & type) S 53h
86 Manufacturer part # (Hyphen) " - " 2Dh
87 Manufacturer part # (Power) L/C 4Ch/43h
88 Manufacturer part # (Minimum cycle time) 7 7 1 1 37h 37h 31h 31h
89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch
90 Manufacturer part # (TBD) Blank 20h
91 Manufacturer revision code (For PCB) S 53h
92 ...... Manufacturer revision code (For component) D-die (5th Gen.) 44h
93 Manufacturing date (Year) - - 3
94 Manufacturing date (Week) - - 3
95~98 Assembly serial # - - 4
99~125 Manufacturer specific data (may be used in future) Undefined -
126 System frequency for 100MHz 100MHz 64h
127 PC100 specification details Detailed PC100 Information AFh AFh AFh ADh
128+ Unused storage locations Undefined -
Function Supported Hex value
-7C -7A -1H -1L -7C -7A -1H -1L
Note
Note :
1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
Rev. 0.1 Sept. 2001
Loading...