Samsung KS0759 Datasheet
KS0759
written permission of LCD Driver IC Team.
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
August. 1999.
Ver. 0.2
Prepared by Hyun-Oh,Lee
exprss@samsung.co.kr
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
KS0759 Specification Revision History
Version Content Date
0.0 Original July.1999
0.1 Remove HPMB,CS2 Pin and Change Vol, Voh value July.1999
0.2 Modify Pad Dimensions and Chip Configuration Aug.1999
2
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
CO
NTENTS
INTRODUCTION ..................................................................................................................................................1
BLOCK DIAGRAM...............................................................................................................................................2
PAD CONFIGURATION .......................................................................................................................................3
PIN DESCRIPTION ..............................................................................................................................................7
POWER SUPPLY ..........................................................................................................................................7
LCD DRIVER SUPPLY..................................................................................................................................7
SYSTEM CONTROL .....................................................................................................................................8
MICROPROCESSOR INTERFACE...............................................................................................................9
LCD DRIVER OUTPUTS.............................................................................................................................11
FUNCTIONAL DESCRIPTION............................................................................................................................ 12
MICROPROCESSOR INTERFACE.............................................................................................................12
DISPLAY DATA RAM (DDRAM)..................................................................................................................16
LCD DISPLAY CIRCUITS............................................................................................................................20
LCD DRIVER CIRCUIT ...............................................................................................................................22
POWER SUPPLY CIRCUITS ......................................................................................................................25
REFERECE CIRCUIT EXAMPLES..............................................................................................................30
RESET CIRCUIT.........................................................................................................................................32
INSTRUCTION DESCRIPTION...........................................................................................................................33
SPECIFICATIONS..............................................................................................................................................53
ABSOLUTE MAXIMUM RATINGS...............................................................................................................53
DC CHARACTERISTICS .............................................................................................................................54
AC CHARACTERISTICS.............................................................................................................................57
REFERENCE APPLICATIONS........................................................................................................................... 61
MICROPROCESSOR INTERFACE.............................................................................................................61
CONNECTIONS BETWEEN KS0759 AND LCD PANEL..............................................................................63
3
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The KS0759 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 81
common and 128 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8bit parallel display data and stores in an on-chip display data RAM of 81 x 128 bits. It provides a highly flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no externally operating clock to minimize power
consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible
to make a display system with the fewest components.
FEATURES
Driver Output Circuits
− 81 common outputs / 128 segment outputs
Applicable Duty Ratios
Programmable duty ratio Applicable LCD bias Maximum display area
1/17 to 1/81 1/4 to 1/11
− Various partial display
− Partial window moving & data scrolling
On-chip Display Data RAM
81 × 128
− Capacity: 81 x 128 = 10,368 bits
− Bit data "1": a dot of display is illuminated.
− Bit data "0": a dot of display is not illuminated.
Microprocessor Interface
− 8-bit parallel bi-directional interface with 6800-series or 8080-series.
− SPI (Serial Peripheral Interface) available. (only write operation)
On-chip Low Power Analog Circuit
− On-chip oscillator circuit
− Voltage converter (x3, x4, x5 or x6)
− Voltage regulator (temperature coefficient: -0.05%/°C or external input)
− On-chip electronic contrast control function (64 steps)
− Voltage follower (LCD bias: 1/4 to 1/11)
Operating Voltage Range
− Supply voltage (VDD): 1.8 to 3.3 V
− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
Low power Consumption
− TBD µΑ Typ. (Internal power supply on and display OFF)
Package Type
− Gold bump chip or TCP
1
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
DB0
DB1
COMS1
COM
Test1
Test2
BLOCK DIAGRAM
SEG127
SEG126
VDD
V0
V1
V2
V3
V4
VSS
:
SEG125
:
SEG2
SEG1
SEG0
128 SEGMENT
DRIVER CIRCUITS
COMS
COM0
:
:
:
82 COMMON
DRIVER CIRCUITS
79
V0
VR
INTRS
VEXT
REF
VOUT
C1-
C1+
C2C2+
C3+
C4+
C5+
VCI
V / F
CIRCUIT
V / R
CIRCUIT
V / C
CIRCUIT
INTERNAL
POWER
SUPPLY
PAGE
ADDRESS
CIRCUIT
SEGMENT CONTROLLER
DISPLAY DATA RAM
81 X 128 = 10,368Bits
COLUMN ADDRESS
CIRCUIT
INSTRUCTION DECODER & REGISTER
MPU INTERFACE (PARALLEL & SERIAL)
COMMON CONTROLLER
DISPLAY
LINE
ADDRESS
CIRCUIT
STATUS REGISTERBUS HOLDER
TIMING
GENERATOR
CIRCUIT/
OSCILLATOR
Test3
Test4
RESETB
DB2
DB3
DB4
DB5
DB6(SCLK)
DB7(SID)
RW_WR
E_RD
RS
CS1B
PS0
PS1
Figure 1. Block Diagram
2
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
. . . . . . . . . . . .
KS0
759
(TOP VIEW
,PAD UP)
. . . . . . . . . . . . . . . . . . . . .
....
PAD CONFIGURATION
313
343
Normal Pad Dummy Pad
Y
(0,0)
X
1 123
Figure 2. KS0759 Chip Configuration
Table 1. KS0759 Pad Dimension
Item Pad No.
Chip size - 9980 2380
Input 1 to 123 70
Size
X Y
155312
154
124
Unit
125 to 152
Output
Pad pitch
NC*
Bumped pad size (Max.)
Bumped pad height All pad 14 (Typ.)
157 to 310
315 to 342
124,343 70
154,155,312,313 80
153,156,311,314 70 / 80
1 to 123 50 100
124 110 60
125 to 152 110 40
153 to 154 110 60
155 to 156 60 110
157 to 310 40 110
311 to 312 60 110
313 to 314 110 60
315 to 342 110 40
343 110 60
60
[[ Dummy to Dummy pad pitch is 80 um. Dummy to normal pad pitch is 70 um.
um
3
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
42 m
108 m
+465)
30 m
30 m
30 m
30 m
30 m
30 m
+375)
42 m
108 m
COG Align Key Coordinate ILB Align Key Coordinate
30µ
30µ
30µ
30µ
30µ
30µ
42µ
(-4310, -510)
108µm
108µm
(+4265,
(+4265,
(4310, 510)
4
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 1. Pad Center Coordinates
[Unit: µm]
NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y
1 PAD_CK -4270 -1075 51 VSS -770 -1075 101 V4 2730 -1075 151 COM13 4843 650
2 TEST_CL -4200 -1075 52 VSS -700 -1075 102 V4 2800 -1075 152 COM12 4843 710
3 SCL -4130 -1075 53 VSS -630 -1075 103 V4 2870 -1075 153 DUMMY 4843 780
4 SDA -4060 -1075 54 VOUT -560 -1075 104 V3 2940 -1075 154 DUMMY 4843 860
5 VSS -3990 -1075 55 VOUT -490 -1075 105 V3 3010 -1075 155 DUMMY 4740 1043
6 VDD -3920 -1075 56 VOUT -420 -1075 106 V3 3080 -1075 156 DUMMY 4660 1043
7 VDD -3850 -1075 57 VOUT -350 -1075 107 V3 3150 -1075 157 COM11 4590 1043
8 PS0 -3780 -1075 58 VOUT -280 -1075 108 V2 3220 -1075 158 COM10 4530 1043
9 VSS -3710 -1075 59 VOUT -210 -1075 109 V2 3290 -1075 159 COM9 4470 1043
10 VDD -3640 -1075 60 VOUT -140 -1075 110 V2 3360 -1075 160 COM8 4410 1043
11 PS1 -3570 -1075 61 VOUT -70 -1075 111 V2 3430 -1075 161 COM7 4350 1043
12 VSS -3500 -1075 62 C5+ 0 -1075 112 V1 3500 -1075 162 COM6 4290 1043
13 CS1B -3430 -1075 63 C5+ 70 -1075 113 V1 3570 -1075 163 COM5 4230 1043
14 VDD -3360 -1075 64 C5+ 140 -1075 114 V1 3640 -1075 164 COM4 4170 1043
15 VDD -3290 -1075 65 C5+ 210 -1075 115 V1 3710 -1075 165 COM3 4110 1043
16 RESETB -3220 -1075 66 C3+ 280 -1075 116 V0 3780 -1075 166 COM2 4050 1043
17 RS -3150 -1075 67 C3+ 350 -1075 117 V0 3850 -1075 167 COM1 3990 1043
18 VSS -3080 -1075 68 C3+ 420 -1075 118 V0 3920 -1075 168 COM0 3930 1043
19 RW_WR -3010 -1075 69 C3+ 490 -1075 119 V0 3990 -1075 169 COMS 3870 1043
20 E_RD -2940 -1075 70 C1- 560 -1075 120 VR 4060 -1075 170 SEG0 3810 1043
21 VDD -2870 -1075 71 C1- 630 -1075 121 VR 4130 -1075 171 SEG1 3750 1043
22 DB0 -2800 -1075 72 C1- 700 -1075 122 VSS 4200 -1075 172 SEG2 3690 1043
23 DB1 -2730 -1075 73 C1- 770 -1075 123 VSS 4270 -1075 173 SEG3 3630 1043
24 DB2 -2660 -1075 74 C1- 840 -1075 124 DUMMY 4843 -980 174 SEG4 3570 1043
25 DB3 -2590 -1075 75 C1- 910 -1075 125 COM39 4843 -910 175 SEG5 3510 1043
26 DB4 -2520 -1075 76 C1+ 980 -1075 126 COM38 4843 -850 176 SEG6 3450 1043
27 DB5 -2450 -1075 77 C1+ 1050 -1075 127 COM37 4843 -790 177 SEG7 3390 1043
28 DB6 -2380 -1075 78 C1+ 1120 -1075 128 COM36 4843 -730 178 SEG8 3330 1043
29 DB7 -2310 -1075 79 C1+ 1190 -1075 129 COM35 4843 -670 179 SEG9 3270 1043
30 VDD -2240 -1075 80 C2+ 1260 -1075 130 COM34 4843 -610 180 SEG10 3210 1043
31 VDD -2170 -1075 81 C2+ 1330 -1075 131 COM33 4843 -550 181 SEG11 3150 1043
32 VDD -2100 -1075 82 C2+ 1400 -1075 132 COM32 4843 -490 182 SEG12 3090 1043
33 VDD -2030 -1075 83 C2+ 1470 -1075 133 COM31 4843 -430 183 SEG13 3030 1043
34 VDD -1960 -1075 84 C2- 1540 -1075 134 COM30 4843 -370 184 SEG14 2970 1043
35 VDD -1890 -1075 85 C2- 1610 -1075 135 COM29 4843 -310 185 SEG15 2910 1043
36 VCI -1820 -1075 86 C2- 1680 -1075 136 COM28 4843 -250 186 SEG16 2850 1043
37 VCI -1750 -1075 87 C2- 1750 -1075 137 COM27 4843 -190 187 SEG17 2790 1043
38 VCI -1680 -1075 88 C2- 1820 -1075 138 COM26 4843 -130 188 SEG18 2730 1043
39 VCI -1610 -1075 89 C2- 1890 -1075 139 COM25 4843 -70 189 SEG19 2670 1043
40 VCI -1540 -1075 90 C4+ 1960 -1075 140 COM24 4843 -10 190 SEG20 2610 1043
41 VCI -1470 -1075 91 C4+ 2030 -1075 141 COM23 4843 50 191 SEG21 2550 1043
42 VCI -1400 -1075 92 C4+ 2100 -1075 142 COM22 4843 110 192 SEG22 2490 1043
43 VCI -1330 -1075 93 C4+ 2170 -1075 143 COM21 4843 170 193 SEG23 2430 1043
44 VSS -1260 -1075 94 VSS 2240 -1075 144 COM20 4843 230 194 SEG24 2370 1043
45 VSS -1190 -1075 95 REF 2310 -1075 145 COM19 4843 290 195 SEG25 2310 1043
46 VSS -1120 -1075 96 VEXT 2380 -1075 146 COM18 4843 350 196 SEG26 2250 1043
47 VSS -1050 -1075 97 VDD 2450 -1075 147 COM17 4843 410 197 SEG27 2190 1043
48 VSS -980 -1075 98 INTRS 2520 -1075 148 COM16 4843 470 198 SEG28 2130 1043
49 VSS -910 -1075 99 VSS 2590 -1075 149 COM15 4843 530 199 SEG29 2070 1043
50 VSS -840 -1075 100 V4 2660 -1075 150 COM14 4843 590 200 SEG30 2010 1043
5
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y
201 SEG31 1950 1043 251 SEG81 -1050 1043 301 COM43 -4050 1043
202 SEG32 1890 1043 252 SEG82 -1110 1043 302 COM44 -4110 1043
203 SEG33 1830 1043 253 SEG83 -1170 1043 303 COM45 -4170 1043
204 SEG34 1770 1043 254 SEG84 -1230 1043 304 COM46 -4230 1043
205 SEG35 1710 1043 255 SEG85 -1290 1043 305 COM47 -4290 1043
206 SEG36 1650 1043 256 SEG86 -1350 1043 306 COM48 -4350 1043
207 SEG37 1590 1043 257 SEG87 -1410 1043 307 COM49 -4410 1043
208 SEG38 1530 1043 258 SEG88 -1470 1043 308 COM50 -4470 1043
209 SEG39 1470 1043 259 SEG89 -1530 1043 309 COM51 -4530 1043
210 SEG40 1410 1043 260 SEG90 -1590 1043 310 COM52 -4590 1043
211 SEG41 1350 1043 261 SEG91 -1650 1043 311 DUMMY -4660 1043
212 SEG42 1290 1043 262 SEG92 -1710 1043 312 DUMMY -4740 1043
213 SEG43 1230 1043 263 SEG93 -1770 1043 313 DUMMY -4843 860
214 SEG44 1170 1043 264 SEG94 -1830 1043 314 DUMMY -4843 780
215 SEG45 1110 1043 265 SEG95 -1890 1043 315 COM53 -4843 710
216 SEG46 1050 1043 266 SEG96 -1950 1043 316 COM54 -4843 650
217 SEG47 990 1043 267 SEG97 -2010 1043 317 COM55 -4843 590
218 SEG48 930 1043 268 SEG98 -2070 1043 318 COM56 -4843 530
219 SEG49 870 1043 269 SEG99 -2130 1043 319 COM57 -4843 470
220 SEG50 810 1043 270 SEG100 -2190 1043 320 COM58 -4843 410
221 SEG51 750 1043 271 SEG101 -2250 1043 321 COM59 -4843 350
222 SEG52 690 1043 272 SEG102 -2310 1043 322 COM60 -4843 290
223 SEG53 630 1043 273 SEG103 -2370 1043 323 COM61 -4843 230
224 SEG54 570 1043 274 SEG104 -2430 1043 324 COM62 -4843 170
225 SEG55 510 1043 275 SEG105 -2490 1043 325 COM63 -4843 110
226 SEG56 450 1043 276 SEG106 -2550 1043 326 COM64 -4843 50
227 SEG57 390 1043 277 SEG107 -2610 1043 327 COM65 -4843 -10
228 SEG58 330 1043 278 SEG108 -2670 1043 328 COM66 -4843 -70
229 SEG59 270 1043 279 SEG109 -2730 1043 329 COM67 -4843 -130
230 SEG60 210 1043 280 SEG110 -2790 1043 330 COM68 -4843 -190
231 SEG61 150 1043 281 SEG111 -2850 1043 331 COM69 -4843 -250
232 SEG62 90 1043 282 SEG112 -2910 1043 332 COM70 -4843 -310
233 SEG63 30 1043 283 SEG113 -2970 1043 333 COM71 -4843 -370
234 SEG64 -30 1043 284 SEG114 -3030 1043 334 COM72 -4843 -430
235 SEG65 -90 1043 285 SEG115 -3090 1043 335 COM73 -4843 -490
236 SEG66 -150 1043 286 SEG116 -3150 1043 336 COM74 -4843 -550
237 SEG67 -210 1043 287 SEG117 -3210 1043 337 COM75 -4843 -610
238 SEG68 -270 1043 288 SEG118 -3270 1043 338 COM76 -4843 -670
239 SEG69 -330 1043 289 SEG119 -3330 1043 339 COM77 -4843 -730
240 SEG70 -390 1043 290 SEG120 -3390 1043 340 COM78 -4843 -790
241 SEG71 -450 1043 291 SEG121 -3450 1043 341 COM79 -4843 -850
242 SEG72 -510 1043 292 SEG122 -3510 1043 342 COMS1 -4843 -910
243 SEG73 -570 1043 293 SEG123 -3570 1043 343 DUMMY -4843 -980
244 SEG74 -630 1043 294 SEG124 -3630 1043
245 SEG75 -690 1043 295 SEG125 -3690 1043
246 SEG76 -750 1043 296 SEG126 -3750 1043
247 SEG77 -810 1043 297 SEG127 -3810 1043
248 SEG78 -870 1043 298 COM40 -3870 1043
249 SEG79 -930 1043 299 COM41 -3930 1043
250 SEG80 -990 1043 300 COM42 -3990 1043
6
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 2. Power Supply Pins
Name I/O Description
VDD Supply Power supply
VSS Supply
V0
V1
V2
V3
V4
I/O
Ground
LCD driver supplies voltages
The voltage determined by LCD pixel is impedance converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.
LCD bias
1/N bias
NOTE: N = 4 to 11
V1
(N-1) / N x V0
V2 V3 V4
(N-2) / N x V0 (2/N) x V0 (1/N) x V0
LCD DRIVER SUPPLY
Table 3. LCD Driver Supply Pins
Name I/O Description
C1- O Capacitor 1 negative connection pin for voltage converter
C1+ O Capacitor 1 positive connection pin for voltage converter
C2- O Capacitor 2 negative connection pin for voltage converter
C2+ O Capacitor 2 positive connection pin for voltage converter
C3+ O Capacitor 3 positive connection pin for voltage converter
C4+ O Capacitor 4 positive connection pin for voltage converter
C5+ O Capacitor 5 positive connection pin for voltage converter
VOUT I/O Voltage converter input / output pin
VCI I
VR I
REF I
VEXT I
Voltage converter input voltage pin
Voltages should have the following relationship: VDD ≤ VCI ≤ V0
V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = "L")
Selects the external VREF voltage via VEXT pin
− REF = "L": using the external VREF
− REF = "H": using the internal VREF
Externally input reference voltage (VREF) for the internal voltage regulator
It is valid only when REF is "L".
7
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
SYSTEM CONTROL
Table 4. System Control Pins
Name I/O Description
Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.
INTRS I
TEST1
to
TEST4
− INTRS = "H": use the internal resistors
− INTRS = "L": use the external resistors
VR pin and external resistive divider control V0 voltage.
Test pins
I
Don’t use these pins.
8
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 5. Microprocessor Interface Pins
Name I/O Description
RESETB I
PS0 I
PS1 I
CS1B
RS I
RW_WR I
Reset the input pin
When RESETB is "L", initialization is executed.
Parallel/Serial data input select input
PS0
H Parallel RS DB0 to DB7
L Serial RS or None SID(DB7) Write only SCLK(DB6)
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR
must be fixed to either "H" or "L".
Microprocessor interface select input pin
− PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface
− PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface
− PS0 = “L” , PS1 = "H": 4 Pin-SPI serial MPU interface
− PS0 = “L” , PS1 = "L": 3 Pin-SPI serial MPU interface
Chip select input pins
I
Data/instruction I/O is enabled only when CS1B is "L" . When chip select is non-active,
DB0 to DB7 may be high impedance.
Register select input pin
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
PS1 MPU Type RW_WR Description
H 6800-series RW
L 8080-series /WR
Interface
Mode
Data/
Instruction
Data Read / Write Serial Clock
E_RD
RW_WR
Read/Write control input pin
− RW = "H": read
− RW = "L": write
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
-
9
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
Table 6 (Continued)
Name I/O Description
Read / Write execution control pin
PS1 MPU Type E_RD Description
Read/Write control input pin
− RW = "H": When E is "H", DB0 to DB7 are in an
E_RD I
H 6800-series E
output status.
− RW = "L": The data on DB0 to DB7 are latched at
the falling edge of the E signal.
Read enable clock input pin
L 8080-series /RD
When /RD is "L", DB0 to DB7 are in an output
status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
DB0
to
DB7
I/O
bus. When the serial interface selected (PS0 = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
10
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 6. LCD Driver Outputs Pins
Name I/O Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG0
to
SEG127
COM0
to
COM79
COMS
(COMS1)
Display data M (Internal)
H H V0 V2
O
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
O
O
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open.
H L VSS V3
L H V2 V0
L L V3 VSS
Power save mode VSS VSS
Scan data M (Internal) Common driver output voltage
H H VSS
H L V0
L H V1
L L V4
Power save mode VSS
Segment driver output voltage
Normal display Reverse display
NOTE: DUMMY – These pins should be opened (floated).
11
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B for chip selection. The KS0759 can interface with an MPU only when CS1B is "L" . When these
pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be
high impedance. And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
KS0759 has four types of interface with an MPU, which are two serial and two parallel interface. This parallel or
serial interface is determined by PS 0pin as shown in Table 7.
Table 7. Parallel / Serial Interface Mode
PS0 Type CS1B PS1 Interface mode
H Parallel CS1B
L Serial CS1B
Parallel Interface (PS0 = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in
Table 8. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in Table 9.
Table 8. Microprocessor Selection for Parallel Interface
PS1 CS1B RS E_RD RW_WR DB0 to DB7 MPU bus
H CS1B RS E RW DB0 to DB7 6800-series
L CS1B RS /RD /WR DB0 to DB7 8080-series
Table 9. Parallel Data Transfer
Common 6800-series 8080-series Description
RS
E_RD
(E)
RW_WR
(RW)
E_RD
(/RD)
H 6800-series MPU mode
L 8080-series MPU mode
H 4 Pin-SPI MPU mode
L 3 Pin-SPI MPU mode
RW_WR
(/WR)
H H H L H Display data read out
H H L H L Display data write
L H H L H Register status read
L H L H L Writes to internal register (instruction)
12
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS0 = "L")
When the KS0759 is active(CS1B=”L”), serial data (DB7) and serial clock (DB6) inputs are enabled. And not
active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be
controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is
used (PS1 = “H”), data is display data when RS is high, and command data when RS is low. When RS is not used
(PS1 = “L”), the LCD Driver will receive command from MPU by default. If messages on the data pin are data
rather than command, MPU should send Data Direction command(11101000) to control the data direction and
then one more command to define the number of data bytes will be write. After these two continuous commands
are send, the following messages will be data rather than command. Serial data can be read on the rising edge of
serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM
column address pointer will be increased by one automatically. The next bytes after the display data string is
handled as command data.
Serial Mode PS0
PS1 CS1B RS
Serial-mode with RS pin L H CS1B Used
Serial-mode with software
command
L L CS1B Not used
4 Pin-SPI Interface (PS0 = "L" , PS1 = "H")
CS1B
SID
SCLK
RS
DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7
Figure 3. 4 Pin SPI Timing (RS is used)
13
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
3 Pin-SPI Interface (PS0 = "L" , PS1 = "L")
To write data to the DDRAM, send Data Direction Command in 3-Pin SPI mode. Data is latched at the rising edge
of SCLK. And the DDRAM column address pointer will be increased by one automatically.
CS1B
829 830 831
SCLK
SID
0 0 1 7 8
~
~
3 Byte (1) 2 Byte (2) 128 Byte
Page
MSB
23
LSB DDC
~
~
15
~
~
No. of
DATA
0
~
~
Data In
(1) Set Page and Column Address.
Set Page Address : 1 0 1 1 P3 P2 P1 P0
Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4
Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0
(2) Set DDC(Data Direction Command) and No. of Data Bytes.
Set Data Direction Command( For SPI mode Only):
1 1 1 0 1 0 0 0
Set No. of Data Bytes(DDL)
: D7 D6 D5 D4 D3D2D1D0
Figure 4. 3 Pin SPI Timing (RS is not used)
This command is used in 3-Pin SPI mode only. It will be two continuous commands, the first byte controls the data
direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two
commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data.
New data will be transferred serially with most significant bit first.
Notes:
l In spite of transmission of data, if CS1B will be disable, state terminates abnormally. Next state is
initialized.
l DDL Register value “0” à “1” , “127” à “128”. (decimal value)
Busy Flag
The Busy Flag indicates whether the KS0759 is operating or not. When DB7 is "H" in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
14
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
D(N)
D(N+1)
D(N+2)
N
N+1
N+2
N+3
Data Transfer
The KS0759 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 5. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure
6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
MPU signals
RS
/WR
/RD
DB0 to DB7
Internal signals
/WR
N D(N) D(N+1) D(N+2) D(N+3)
N D(N) D(N+1) D(N+2) D(N+3)
N N+1 N+2 N+3
Figure 5. Write Timing
N
Dummy D(N) D(N+1)
/RD
BUS HOLDER
COLUMN ADDRESS
N
Figure 6. Read Timing
15
81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.2 KS0759
- -
- -
- -
- -
001
- -
0
011
- -
0
101
- -
0
000
- -
1
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 81-row by 128-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 81 rows are divided into 10 pages of 8
lines and the 11th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in Figure 7. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
DB0
DB1
DB2
DB3
DB4
1 0 0 - - 1
COM0
COM1
COM2
COM3
COM4
- -
Display Data RAM LCD Display
Figure 7. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in Figure 9. It incorporates 4-bit Page
Address register changed by only the "Set Page" instruction. Page Address 10 (DB3 and DB1 are "H", DB2 and
DB0 is "L") is a special RAM area for the icons and display data DB0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in Figure 9 & Figure 10. It incorporates 7-bit Line Address register
changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame,
the contents of register are copied to the line counter which is increased by CL signal and generates the Line
Address for transferring the 128-bit RAM data to the display data latch circuit. However, display data of icons are
not scrolled because the MPU can not access Line Address of icons.
16
KS0759 PRELIMINARY SPEC. VER. 0.2 81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit
Column address circuit has a 7-bit preset counter that provides column address to the Display Data RAM as
shown in Figure 9. When set Column Address MSB / LSB instruction is issued, 7-bit [Y6:Y0] is updated. And,
since this address is increased by 1 each a read or write data instruction, microprocessor can access the display
data continuously. And the Column Address counter is independent of page address register.
ADC Select instruction makes it possible to invert the relationship between the column address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to
the following Figure 8.
SEG output
SEG
0
SEG
1
SEG
2
SEG
3
... ...
SEG
124
SEG
125
SEG
126
SEG
127
Column address [Y6:Y0] 00H 01H 02H 03H ... ... 7CH 7DH 7EH 7FH
Display data 1 0 1 0 1 1 0 0
LCD panel display
... ...
( ADC = 0 )
LCD panel display
( ADC = 1 )
... ...
Figure 8. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.
17
Loading...