Samsung KS0741 Datasheet

KS0741

permission of LCD Driver IC Team.

128 SEG / 129 COM DRIVER & CONTROLLER FOR 4 GRAY SCALE STN LCD

Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

February 8. 2000.

Ver. 1.2

Prepared by: Hyung-Suk, Kim

highndry@samsung.co.kr

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

KS0741 Specification Revision History

Version Content Date

0.0 Preliminary specification (short form) June 8, 1999

0.1 Preliminary specification (full set) July 14, 1999

0.2 Added temporary pin number (page 5,6) July 15, 1999 Removed HPMB, CS2 pins

0.3

CS1B pin → CSB pin

July 30, 1999 VOL Max.: 0.3VDD → 0.2VDD , VOH Min.: 0.7VDD → 0.8VDD (page 59) Removed CLS, OSCCK, OSC2 pins (page 7,8)

0.4

Read internal status: MF, DS ID is added, ADC is removed (Page 35, 39) RESET flag: 0: display ON, 1: display OFF

Aug. 12, 1999

→ 0: display OFF, 1: display ON (Page 39) Changed input pin order, add RESETB pin (page 5) Added VR, VEXT pin connection (page 8) VR: When using internal resistors (INTRS = "H"), open this pin VEXT: When using internal voltage regulator, connect to VDD, VSS or open this pin

0.5

Added test pin connection (page 9)

Aug. 30, 1999 TEST1,TEST2: connect to “VDD” TEST3,TEST4,TEST5: connect to “VSS” Changed OSC resistance connection (page8, 23) Between OSC1 and OSC2 → between OSC1 and VDD Removed TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 pins

0.6

Added COMS, COMS1 for ICON display.

Sep. 30, 1999 Added ICON control register ON/OFF instruction.

0.7

Remove COMS, COMS1 for ICON display. Remove ICON control register ON/OFF instruction.

Oct. 4, 1999

Added COMS, COMS1 for ICON display. Added ICON control register ON/OFF instruction.

1.0

Modified bit settings for partial display command.

Jan. 18, 2000 Relaxed VIH and VIL specifications. Modified interface timing specs. Added 6800-mode interface description for data latch with (page 14) C2 CAP value : 0.1 to 0.47uF → 0.47 to 2.0uF (page 34) Added Icon Mode Disabled to the Reset default list. (page 36)

1.1

Added description of the column address operation. (page 40) Added that Display On/Off command has priority over Entire Display On/Off and

Jan. 24, 2000 Reverse Display On/Off. (page 44)

Added N-line inversion command description (page 47) The lower limit of VOUT, V0 - V4 : +0.3V → -0.3V (page 60)

1.2 The upper limit of V1 - V4 : V0 → V0 + 0.3V (page 60) Feb. 8, 2000

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

NTENTS

INTRODUCTION ................................................................................................................................................. 1

FEATURES......................................................................................................................................................... 1

BLOCK DIAGRAM.............................................................................................................................................. 3

PAD CONFIGURATION ...................................................................................................................................... 4

PAD Center Coordinates ................................................................................................................................... 6

PIN DESCRIPTION ............................................................................................................................................. 6

POWER SUPPLY ..........................................................................................................................................9

LCD DRIVER SUPPLY..................................................................................................................................9

SYSTEM CONTROL ...................................................................................................................................10

MICROPROCESSOR INTERFACE.............................................................................................................11

LCD DRIVER OUTPUTS.............................................................................................................................13

FUNCTIONAL DESCRIPTION........................................................................................................................... 14

MICROPROCESSOR INTERFACE.............................................................................................................14

DISPLAY DATA RAM (DDRAM)..................................................................................................................18

LCD DISPLAY CIRCUITS............................................................................................................................21

LCD DRIVER CIRCUIT ...............................................................................................................................26

POWER SUPPLY CIRCUITS ......................................................................................................................29

REFERECE CIRCUIT EXAMPLES..............................................................................................................34

RESET CIRCUIT.........................................................................................................................................36

INSTRUCTION DESCRIPTION.......................................................................................................................... 37

SPECIFICATIONS............................................................................................................................................. 60

ABSOLUTE MAXIMUM RATINGS...............................................................................................................60

DC CHARACTERISTICS .............................................................................................................................61

AC CHARACTERISTICS.............................................................................................................................64

REFERENCE APPLICATIONS.......................................................................................................................... 68

MICROPROCESSOR INTERFACE.............................................................................................................68

CONNECTIONS BETWEEN KS0741 AND LCD PANEL..............................................................................70

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The KS0741 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. It contains 128 segment and 129 common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface(SPI) or 8-bit parallel display data and stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.

FEATURES

4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM and FRC Methods

DDRAM data [2n: 2n+1] 00 01 10 11

Gray scale White Light gray Dark gray Dark

(Accessible column address, n = 0, 1, 2, ……, 125, 126, 127)

Driver Output Circuits

− 128 segment outputs / 129 common outputs

Applicable Duty Ratios

Duty ratio Applicable LCD bias Maximum display area

1/16 ~ 1/128 (ICON disabled)

1/17 ~ 1/129 (ICON enabled)

− Various partial display

− Partial window moving & data scrolling

On-chip Display Data RAM

− Capacity: 129 × 128 × 2 = 33,024bits

− Bit data "1": a dot of display is illuminated.

− Bit data "0": a dot of display is not illuminated.

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− SPI (serial peripheral interface) available (only write operation)

On-chip Low Power Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x3, x4, ×5 or x6)

− Voltage regulator (temperature coefficient: -0.05%/°C, or external input)

− On-chip electronic contrast control function (64 steps)

− Voltage follower (LCD bias : 1/5 to 1/12)

Operating Voltage Range

− Supply voltage (VDD): 1.8 to 3.3V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

1/5 to 1/12 129 × 128

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

Low Power Consumption

− TBD µΑ Max. (operation)

− TBD µΑ Max. (sleep mode)

Package Type

− Slim chip for TCP

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

DB0

DB1

COMS1

COM127

COM126

TEST1

BLOCK DIAGRAM

SEG127

SEG126

VDD

V0 V1 V2 V3 V4

VSS

SEG2

SEG1

SEG0

128 SEGMENT

DRIVER CIRCUITS

SEG125

COMS

COM1

COM0

DRIVER CIRCUITS

129 COMMON

INTRS

VEXT

REF

VOUT

C1-

C1+

C2C2+ C3+ C4+ C5+

VCl

V / F

CIRCUIT

V / R

CIRCUIT

V / C

CIRCUIT

INTERNAL

POWER SUPPLY

PAGE

ADDRESS

CIRCUIT

I/O

BUFFER

DISPLAY LATCH CIRCUIT

FRC/PWM FUNCTION CIRCUIT

DISPLAY DATA RAM

129 X 128 X 2 = 33,024 Bits

COLUMN ADDRESS

CIRCUIT

STATUS REGISTER INSTRUCTION REGISTER

LINE

ADDRESS

CIRCUIT

INSTRUCTION DECODERBUS HOLDER

COMMON

OUTPUT

CONTROLLER

CIRCUIT

OSCILLATOR

/DISPLAY

TIMING

CONTROL

OSC1

MPU INTERFACE (PARALLEL & SERIAL)

DB4

DB5

DB6(SCLK)

DB7(SID)

RW_WR

E_RD

CSB

PS0

PS1

RESETB

Figure 1. Block Diagram

DB3

DB2

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

…..

KS0741

PAD CONFIGURATION

.......................

375

374

181

180

(0,0)

411

1 143

............

PAD

Figure 2. KS0741 Chip Configuration

Table 1. KS0741 Pad Dimensions

ITEM PAD NO.

Chip Size - 10580 2520

1 ~ 143 70

144 ~ 178

Pad Pitch

Bumped pad size

Bumped pad height ALL PAD 14 (TYP)

183 ~ 372 377 ~ 411 179 ~ 182 373 ~ 376

1 ~ 143 42 92

145 ~ 178 377 ~ 410

183 ~ 372 34 70

144 179 ~ 180 375 ~ 376

411 181 ~ 182 373 ~ 374

SIZE

X Y

70 34

70 62

62 70

144

UNIT

§-

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

(+4527, +624.5)

(-4690, -515)

30µm

42µm

108µm

42µm

108µm

(-4607, +704.5)

(+4770, -580)

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

42µm 108µm

42µm108µm

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y

1 DUMMY -4970 -1145 51 DUMMY -1470 -1145 101 C3+ 2030 -1145 151 COM57 5166 -586 2 DUMMY -4900 -1145 52 DUMMY -1400 -1145 102 C3+ 2100 -1145 152 COM56 5166 -534 3 DUMMY -4830 -1145 53 DUMMY -1330 -1145 103 C1- 2170 -1145 153 COM55 5166 -482 4 DUMMY -4760 -1145 54 DUMMY -1260 -1145 104 C1- 2240 -1145 154 COM54 5166 -430 5 DUMMY -4690 -1145 55 DUMMY -1190 -1145 105 C1+ 2310 -1145 155 COM53 5166 -378 6 DUMMY -4620 -1145 56 DUMMY -1120 -1145 106 C1+ 2380 -1145 156 COM52 5166 -326 7 DUMMY -4550 -1145 57 DUMMY -1050 -1145 107 C2+ 2450 -1145 157 COM51 5166 -274 8 DUMMY -4480 -1145 58 DUMMY -980 -1145 108 C2+ 2520 -1145 158 COM50 5166 -222

9 DUMMY -4410 -1145 59 VDD -910 -1145 109 C2- 2590 -1145 159 COM49 5166 -170 10 DUMMY -4340 -1145 60 TEST1 -840 -1145 110 C2- 2660 -1145 160 COM48 5166 -118 11 DUMMY -4270 -1145 61 VSS -770 -1145 111 C4+ 2730 -1145 161 COM47 5166 -66 12 DUMMY -4200 -1145 62 PS0 -700 -1145 112 C4+ 2800 -1145 162 COM46 5166 -14 13 DUMMY -4130 -1145 63 VDD -630 -1145 113 VDD 2870 -1145 163 COM45 5166 38 14 DUMMY -4060 -1145 64 PS1 -560 -1145 114 VDD 2940 -1145 164 COM44 5166 90 15 DUMMY -3990 -1145 65 VSS -490 -1145 115 REF 3010 -1145 165 COM43 5166 142 16 DUMMY -3920 -1145 66 CSB -420 -1145 116 VSS 3080 -1145 166 COM42 5166 194 17 DUMMY -3850 -1145 67 RESETB -350 -1145 117 VEXT 3150 -1145 167 COM41 5166 246 18 DUMMY -3780 -1145 68 VDD -280 -1145 118 VDD 3220 -1145 168 COM40 5166 298 19 DUMMY -3710 -1145 69 RS -210 -1145 119 INTRS 3290 -1145 169 COM39 5166 350 20 DUMMY -3640 -1145 70 RW_WR -140 -1145 120 VSS 3360 -1145 170 COM38 5166 402 21 DUMMY -3570 -1145 71 VSS -70 -1145 121 VSS 3430 -1145 171 COM37 5166 454 22 DUMMY -3500 -1145 72 E_RD 0 -1145 122 V4 3500 -1145 172 COM36 5166 506 23 DUMMY -3430 -1145 73 VDD 70 -1145 123 V4 3570 -1145 173 COM35 5166 558 24 DUMMY -3360 -1145 74 DB0 140 -1145 124 V3 3640 -1145 174 COM34 5166 610 25 DUMMY -3290 -1145 75 DB1 210 -1145 125 V3 3710 -1145 175 COM33 5166 662 26 DUMMY -3220 -1145 76 DB2 280 -1145 126 V2 3780 -1145 176 COM32 5166 714 27 DUMMY -3150 -1145 77 DB3 350 -1145 127 V2 3850 -1145 177 COM31 5166 766 28 DUMMY -3080 -1145 78 DB4 420 -1145 128 V1 3920 -1145 178 COM30 5166 818 29 DUMMY -3010 -1145 79 DB5 490 -1145 129 V1 3990 -1145 179 DUMMY 5166 884 30 DUMMY -2940 -1145 80 DB6 560 -1145 130 V0 4060 -1145 180 DUMMY 5166 964 31 DUMMY -2870 -1145 81 DB7 630 -1145 131 V0 4130 -1145 181 DUMMY 5060 1136 32 DUMMY -2800 -1145 82 VDD 700 -1145 132 VR 4200 -1145 182 DUMMY 4980 1136 33 DUMMY -2730 -1145 83 VDD 770 -1145 133 VR 4270 -1145 183 COM29 4914 1136 34 DUMMY -2660 -1145 84 VDD 840 -1145 134 VSS 4340 -1145 184 COM28 4862 1136 35 DUMMY -2590 -1145 85 VDD 910 -1145 135 VSS 4410 -1145 185 COM27 4810 1136 36 DUMMY -2520 -1145 86 VDD 980 -1145 136 VDD 4480 -1145 186 COM26 4758 1136 37 DUMMY -2450 -1145 87 VDD 1050 -1145 137 OSC1 4550 -1145 187 COM25 4706 1136 38 DUMMY -2380 -1145 88 VCI 1120 -1145 138 DUMMY 4620 -1145 188 COM24 4654 1136 39 DUMMY -2310 -1145 89 VCI 1190 -1145 139 DUMMY 4690 -1145 189 COM23 4602 1136 40 DUMMY -2240 -1145 90 VSS 1260 -1145 140 DUMMY 4760 -1145 190 COM22 4550 1136 41 DUMMY -2170 -1145 91 VSS 1330 -1145 141 DUMMY 4830 -1145 191 COM21 4498 1136 42 DUMMY -2100 -1145 92 VSS 1400 -1145 142 DUMMY 4900 -1145 192 COM20 4446 1136 43 DUMMY -2030 -1145 93 VSS 1470 -1145 143 DUMMY 4970 -1145 193 COM19 4394 1136 44 DUMMY -1960 -1145 94 VSS 1540 -1145 144 DUMMY 5166 -964 194 COM18 4342 1136 45 DUMMY -1890 -1145 95 VSS 1610 -1145 145 COM63 5166 -898 195 COM17 4290 1136 46 DUMMY -1820 -1145 96 VSS 1680 -1145 146 COM62 5166 -846 196 COM16 4238 1136 47 DUMMY -1750 -1145 97 VOUT 1750 -1145 147 COM61 5166 -794 197 COM15 4186 1136 48 DUMMY -1680 -1145 98 VOUT 1820 -1145 148 COM60 5166 -742 198 COM14 4134 1136 49 DUMMY -1610 -1145 99 C5+ 1890 -1145 149 COM59 5166 -690 199 COM13 4082 1136 50 DUMMY -1540 -1145 100 C5+ 1960 -1145 150 COM58 5166 -638 200 COM12 4030 1136

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

Table 2. PAD Center Coordinates (Continued)

[unit: µm ]

NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y

201 COM11 3978 1136 251 SEG37 1378 1136 301 SEG87 -1222 1136 351 COM73 -3822 1136 202 COM10 3926 1136 252 SEG38 1326 1136 302 SEG88 -1274 1136 352 COM74 -3874 1136 203 COM9 3874 1136 253 SEG39 1274 1136 303 SEG89 -1326 1136 353 COM75 -3926 1136 204 COM8 3822 1136 254 SEG40 1222 1136 304 SEG90 -1378 1136 354 COM76 -3978 1136 205 COM7 3770 1136 255 SEG41 1170 1136 305 SEG91 -1430 1136 355 COM77 -4030 1136 206 COM6 3718 1136 256 SEG42 1118 1136 306 SEG92 -1482 1136 356 COM78 -4082 1136 207 COM5 3666 1136 257 SEG43 1066 1136 307 SEG93 -1534 1136 357 COM79 -4134 1136 208 COM4 3614 1136 258 SEG44 1014 1136 308 SEG94 -1586 1136 358 COM80 -4186 1136 209 COM3 3562 1136 259 SEG45 962 1136 309 SEG95 -1638 1136 359 COM81 -4238 1136 210 COM2 3510 1136 260 SEG46 910 1136 310 SEG96 -1690 1136 360 COM82 -4290 1136 211 COM1 3458 1136 261 SEG47 858 1136 311 SEG97 -1742 1136 361 COM83 -4342 1136 212 COM0 3406 1136 262 SEG48 806 1136 312 SEG98 -1794 1136 362 COM84 -4394 1136 213 COMS 3354 1136 263 SEG49 754 1136 313 SEG99 -1846 1136 363 COM85 -4446 1136 214 SEG0 3302 1136 264 SEG50 702 1136 314 SEG100 -1898 1136 364 COM86 -4498 1136 215 SEG1 3250 1136 265 SEG51 650 1136 315 SEG101 -1950 1136 365 COM87 -4550 1136 216 SEG2 3198 1136 266 SEG52 598 1136 316 SEG102 -2002 1136 366 COM88 -4602 1136 217 SEG3 3146 1136 267 SEG53 546 1136 317 SEG103 -2054 1136 367 COM89 -4654 1136 218 SEG4 3094 1136 268 SEG54 494 1136 318 SEG104 -2106 1136 368 COM90 -4706 1136 219 SEG5 3042 1136 269 SEG55 442 1136 319 SEG105 -2158 1136 369 COM91 -4758 1136 220 SEG6 2990 1136 270 SEG56 390 1136 320 SEG106 -2210 1136 370 COM92 -4810 1136 221 SEG7 2938 1136 271 SEG57 338 1136 321 SEG107 -2262 1136 371 COM93 -4862 1136 222 SEG8 2886 1136 272 SEG58 286 1136 322 SEG108 -2314 1136 372 COM94 -4914 1136 223 SEG9 2834 1136 273 SEG59 234 1136 323 SEG109 -2366 1136 373 DUMMY -4980 1136 224 SEG10 2782 1136 274 SEG60 182 1136 324 SEG110 -2418 1136 374 DUMMY -5060 1136 225 SEG11 2730 1136 275 SEG61 130 1136 325 SEG111 -2470 1136 375 DUMMY -5166 964 226 SEG12 2678 1136 276 SEG62 78 1136 326 SEG112 -2522 1136 376 DUMMY -5166 884 227 SEG13 2626 1136 277 SEG63 26 1136 327 SEG113 -2574 1136 377 COM95 -5166 818 228 SEG14 2574 1136 278 SEG64 -26 1136 328 SEG114 -2626 1136 378 COM96 -5166 766 229 SEG15 2522 1136 279 SEG65 -78 1136 329 SEG115 -2678 1136 379 COM97 -5166 714 230 SEG16 2470 1136 280 SEG66 -130 1136 330 SEG116 -2730 1136 380 COM98 -5166 662 231 SEG17 2418 1136 281 SEG67 -182 1136 331 SEG117 -2782 1136 381 COM99 -5166 610 232 SEG18 2366 1136 282 SEG68 -234 1136 332 SEG118 -2834 1136 382 COM100 -5166 558 233 SEG19 2314 1136 283 SEG69 -286 1136 333 SEG119 -2886 1136 383 COM101 -5166 506 234 SEG20 2262 1136 284 SEG70 -338 1136 334 SEG120 -2938 1136 384 COM102 -5166 454 235 SEG21 2210 1136 285 SEG71 -390 1136 335 SEG121 -2990 1136 385 COM103 -5166 402 236 SEG22 2158 1136 286 SEG72 -442 1136 336 SEG122 -3042 1136 386 COM104 -5166 350 237 SEG23 2106 1136 287 SEG73 -494 1136 337 SEG123 -3094 1136 387 COM105 -5166 298 238 SEG24 2054 1136 288 SEG74 -546 1136 338 SEG124 -3146 1136 388 COM106 -5166 246 239 SEG25 2002 1136 289 SEG75 -598 1136 339 SEG125 -3198 1136 389 COM107 -5166 194 240 SEG26 1950 1136 290 SEG76 -650 1136 340 SEG126 -3250 1136 390 COM108 -5166 142 241 SEG27 1898 1136 291 SEG77 -702 1136 341 SEG127 -3302 1136 391 COM109 -5166 90 242 SEG28 1846 1136 292 SEG78 -754 1136 342 COM64 -3354 1136 392 COM110 -5166 38 243 SEG29 1794 1136 293 SEG79 -806 1136 343 COM65 -3406 1136 393 COM111 -5166 -14 244 SEG30 1742 1136 294 SEG80 -858 1136 344 COM66 -3458 1136 394 COM112 -5166 -66 245 SEG31 1690 1136 295 SEG81 -910 1136 345 COM67 -3510 1136 395 COM113 -5166 -118 246 SEG32 1638 1136 296 SEG82 -962 1136 346 COM68 -3562 1136 396 COM114 -5166 -170 247 SEG33 1586 1136 297 SEG83 -1014 1136 347 COM69 -3614 1136 397 COM115 -5166 -222 248 SEG34 1534 1136 298 SEG84 -1066 1136 348 COM70 -3666 1136 398 COM116 -5166 -274 249 SEG35 1482 1136 299 SEG85 -1118 1136 349 COM71 -3718 1136 399 COM117 -5166 -326 250 SEG36 1430 1136 300 SEG86 -1170 1136 350 COM72 -3770 1136 400 COM118 -5166 -378

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

Table 2. PAD Center Coordinates (Continued)

[unit: µm ]

NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y

401 COM119 -5166 -430 402 COM120 -5166 -482 403 COM121 -5166 -534 404 COM122 -5166 -586 405 COM123 -5166 -638 406 COM124 -5166 -690 407 COM125 -5166 -742 408 COM126 -5166 -794 409 COM127 -5166 -846 410 COMS1 -5166 -898 411 DUMMY -5166 -964

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pin Description

Name I/O Description

VDD Supply Power supply

VSS Supply Ground

LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier

V0 V1 V2 V3 V4

I/O

for application. Voltages should have the following relationship; V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias.

LCD bias V1 V2 V3 V4

1/N bias (N-1) / N x V0 (N-2) / N x V0 (2/N) x V0 (1/N) x V0

NOTE: N = 5 to 12

LCD DRIVER SUPPLY

Table 4. LCD Driver Supply Pin Description

Name I/O Description

C1- O

C1+ O

C2- O C2+ O C3+ O C4+ O C5+ O

VOUT I/O

VCl I

VR I

REF I

VEXT I

OSC1

Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter

Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Capacitor 4 positive connection pin for voltage converter Capacitor 5 positive connection pin for voltage converter Voltage converter input / output pin Voltage converter input voltage pin

V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin Selects the external VREF voltage via the VEXT pin

− REF = “H”: using the internal VREF

− REF = “L”: using the external VREF

Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L" When using internal voltage regulator, connect to VDD, VSS or open this pin

When using internal clock oscillator, connect a resistor between OSC1 and VDD.

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

SYSTEM CONTROL

Table 5. System Control Pin Description

Name I/O Description

Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level

INTRS I

TEST1 O

− INTRS = "H": use the internal resistors.

− INTRS = "L": use the external resistors

VR pin and external resistive divider control V0 voltage Test pins

Don’ t use this pin.

− TEST1: Open this pin.

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

MICROPROCESSOR INTERFACE

Table 6. Microprocessor Interface Pin Description

Name I/O Description

RESETB I

PS0 I

PS1 I

CSB I

RS I

RW_WR I

Reset input pin When RESETB is “L”, initialization is executed.

Parallel / Serial data input select input

PS0

H Parallel RS DB0 to DB7

L Serial RS or None SID (DB7) Write only SCLK (DB6)

*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.

Microprocessor interface select input pin

− PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface

− PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface

− PS0 = “L” , PS1 = "H": 4 pin-SPI MPU interface

− PS0 = “L” , PS1 = "L": 3 pin-SPI MPU interface

Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance.

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

C68 MPU type RW_WR Description

H 6800-series RW

L 8080-series /WR

Interface

mode

Data /

instruction

Data Read / Write Serial clock

E_RD

RW_WR

Read / Write control input pin

− RW = “H” : read

− RW = “L” : write

Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

Table 7. Microprocessor Interface Pin Description (Continued)

Name I/O Description

Read / Write execution control pin

PS1 MPU Type E_RD Description

Read / Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 are in an

E_RD I

H 6800-series E

output status.

− RW = “L”: The data on DB0 to DB7 are latched at the falling edge of the E signal.

DB0

DB7

I/O

L 8080-series /RD

Read enable clock input pin When /RD is “L”, DB0 to DB7 are in an output status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS0 = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID)

When chip select is not active, DB0 to DB7 may be high impedance.

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER OUTPUTS

Table 8. LCD Driver Output Pin Description

Name I/O Description

LCD segment driver outputs The display data and the M signal control the output voltage of segment driver.

SEG0

SEG127

COM0

COM127

COMS

(COMS1)

Display data M (Internal)

H H V0 V2

LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver.

Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.

H L VSS V3

L H V2 V0 L L V3 VSS

Power save mode VSS VSS

Scan data M (Internal) Common driver output voltage

H H VSS H L V0

L H V1 L L V4

Power save mode VSS

Segment driver output voltage

Normal display Reverse display

NOTE: DUMMY – These pins should be opened (floated).

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There is CSB pin for chip selection. The KS0741 can interface with an MPU when CSB is "L". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.

Parallel / Serial Interface

KS0741 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 9.

Table 9. Parallel / Serial Interface Mode

Type PS1 CSB PS0 Interface mode

Parallel

Serial

Parallel Interface (PS0 = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in table 10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11.

PS1 CSB RS E_RD RW_WR DB0 to DB7 MPU bus

H CSB RS E RW DB0 to DB7 6800-series

L CSB RS /RD /WR DB0 to DB7 8080-series

Common 6800-series 8080-series

H H H L H Display data read out H H L H L Display data write

L H H L H Register status read L H L H L Writes to internal register (instruction)

H 6800-series MPU mode

E_RD

(E)

CSB H

CSB L

Table 10. Microprocessor Selection for Parallel Interface

Table 11. Parallel Data Transfer

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

8080-series MPU mode

4-pin SPI mode 3-pin SPI mode

Description

NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this

case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at RS, RW_WR as in case of 6800-series mode.

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

Serial Interface (PS0 = "L")

When the KS0741 is active(CSB=”L”), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is used (PS1 = “H”), data is display data when RS is high, and command data when RS is low. When RS is not used (PS1 = “L”), the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are send, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data.

Serial Mode

4-Pin SPI mode L H CSB Used 3-Pin SPI mode L L CSB Not used

4-pin SPI mode (PS0 = "L" , PS1 = "H")

CSB

SID

SCLK

Figure 3. 4-pin SPI Timing (RS is used)

PS0 PS1 CSB RS

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

3 Byte (1)

2 Byte (2)

104 Byte

3-pin SPI mode (PS0 = "L" , PS1 = "L")

To write data to the DDRAM, send Data Direction Command in 3-pin SPI mode. Data is latched at the rising edge of SCLK. And the DDRAM column address pointer will be increased by one automatically.

CSB

SCLK

SID

DATA

Page

MSB

LSB DDC

No. of

(1) Set Page and Column Address.

Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0

(2) Set DDC(Data Direction Command) and No. of Data Bytes.

Set Data Direction Command( For SPI mode Only):

1 1 1 0 1 0 0 0

Set No. of Data Bytes : D7 D6 D5 D4 D3 D2 D1 D0

(3) This figure is example for 104 Data bytes to be transfered .

Figure 4. 3-pin SPI Timing (RS is not used)

829 830 8310 0 1 7 8 15

Data In

This command is used in 3-pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first.

NOTE: In spite of transmission of data, if CSB will be disable, state terminates abnormally. Next state is initialized.

Busy Flag

The Busy Flag indicates whether the KS0741 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

D(N)

D(N+1)

D(N+2)

N+1

N+2

N+3

Data Transfer

The KS0741 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 5. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.

MPU signals

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

MPU signals

/WR

/RD

DB0 to DB7

Internal signals

/WR

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 5. Write Timing

Dummy D(N) D(N+1)

/RD

BUS HOLDER

COLUMN ADDRESS

Figure 6. Read Timing

128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 129-row (17 page by 8 bits) by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons.

KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column Address Circuit has a 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 7-bit [Y7:Y1] are set and lowest bit, Y0 is set to “0”. Since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 7EH. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register.

ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7.

SEG output

SEG

... ...

SEG

124

SEG

125

SEG

126

SEG

127

Column address [Y7:Y1] 00H 01H 02H 03H ... ... 7CH 7DH 7EH 7FH

Internal column

address [Y7:Y0]

HEX01HEX02HEX03HEX04HEX05HEX06HEX07HEX

... ...

HEXF9HEXFAHEXFBHEXFCHEXFDHEXFEHEXFFHEX

Display data (ADC = 0) 1 1 1 0 0 0 0 1 ... ... 1 0 1 1 0 0 0 1

LCD panel display ... ...

Display data (ADC = 1) 0 1 0 0 1 1 1 0 ... ... 0 1 0 0 1 0 1 1

LCD panel display ... ...

Figure 7. The Relationship between the Column Address and The Segment Outputs

Segment Control Circuit

This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.

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