Samsung KS0717UM-L4CC, KS0717TB-XX-L0TF, KS0717UM-L0CC, KS0717TB-XX-L4TF Datasheet

KS0717

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

January.2000

Ver. 1.0

Prepared by: Yong-Jin, Jeon

Yjjeon@samsung.co.kr

Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

written permission of LCD Driver IC Team.

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

KS0717 Specification Revision History

Version Content Date

0.0 Apr.1999

1.0

Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V

Jan.2000

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

NTENTS

INTRODUCTION ..................................................................................................................................................1

FEATURES..........................................................................................................................................................1

BLOCK DIAGRAM...............................................................................................................................................3

PAD CONFIGURATION .......................................................................................................................................4

PAD CENTER COORDINATES ............................................................................................................................5

PIN DESCRIPTION ..............................................................................................................................................7

POWER SUPPLY ..........................................................................................................................................7

LCD DRIVER SUPPLY..................................................................................................................................7

SYSTEM CONTROL .....................................................................................................................................8

MICROPROCESSOR INTERFACE.............................................................................................................10

LCD DRIVER OUTPUTS.............................................................................................................................12

FUNCTIONAL DESCRIPTION............................................................................................................................ 13

MICROPROCESSOR INTERFACE.............................................................................................................13

DISPLAY DATA RAM (DDRAM)..................................................................................................................17

LCD DISPLAY CIRCUITS............................................................................................................................20

LCD DRIVER CIRCUIT ...............................................................................................................................22

POWER SUPPLY CIRCUITS ......................................................................................................................23

REFERECE CIRCUIT EXAMPLES..............................................................................................................30

RESET CIRCUIT.........................................................................................................................................32

INSTRUCTION DESCRIPTION...........................................................................................................................33

SPECIFICATIONS..............................................................................................................................................47

ABSOLUTE MAXIMUM RATINGS...............................................................................................................47

DC CHARACTERISTICS .............................................................................................................................48

REFERENCE DATA....................................................................................................................................51

AC CHARACTERISTICS.............................................................................................................................53

REFERENCE APPLICATIONS........................................................................................................................... 57

MICROPROCESSOR INTERFACE.............................................................................................................57

CONNECTIONS BETWEEN KS0717 AND LCD PANEL..............................................................................58

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The KS0717 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 55 common and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8bit parallel display data and stores in an on-chip display data RAM of 65 x 100 bits. It provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.

FEATURES

Driver Output Circuits

− 55 common outputs / 100 segment outputs

On-chip Display Data RAM

− Capacity: 65 x 100 = 6,500 bits

− Bit data "1": a dot of display is illuminated.

− Bit data "0": a dot of display is not illuminated.

Multi-chip Operation (Master, Slave) Available Applicable Duty Ratios

Duty ratio Applicable LCD bias Maximum display area

1/55 1/8 or 1/6

55 × 100

1/34 1/6 or 1/5

34 × 100

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− Serial interface (only write operation) available

On-Chip Low Power Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x2, x3, x4, x5)

− Voltage regulator (temperature coefficient: -0.05%/°C or external input)

− Voltage follower (LCD bias: 1/5, 1/6 or 1/8)

− Electronic contrast control function (64 steps)

Operating Voltage Range

− Supply voltage (VDD): 2.4 to 3.6 V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Wide Operating Temperature Range

− Ta = -40°C to 85 °C

Low Power Consumption

− 100 µΑ Max. (VDD = 3V, x4 boosting, V0 = 11V, internal power supply ON)

− 10 µΑ Max. (during power save [standby] mode)

Package Type

− Gold bumped chip or TCP

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

Series Specifications

Product code Temp. coefficient Package Chip thickness

KS0717UM-L0CC

670 µm

KS0717UM-L4CC

COG

470 µm

KS0717TB-XX-L0TF 670 µm KS0717TB-XX-L4TF

-0.05% / °C TCP

470 µm

XX: TCP ordering number

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

BLOCK DIAGRAM

MS CL M FRS DISP DUTY

VDD

V0 V1 V2 V3 V4

VSS

HPMB

INTRS

VEXT

REF

VOUT

C1-

C1+

C2-

C2+

C3-

C3+

DCDC5B

V / C

CIRCUIT

V / R

CIRCUIT

V / F

CIRCUIT

MPU INTERFACE (PARALLEL & SERIAL)

INSTRUCTION DECODERBUS HOLDER

COLUMN ADDRESS

CIRCUIT

LINE

ADDRESS

CIRCUIT

PAGE

ADDRESS

CIRCUIT

DISPLAY DATA RAM

65 X 100 = 6,500 Bits

SEGMENT CONTROLLER

DISPLAY

TIMING

GENERATOR

CIRCUIT

COMMON CONTROLLER

DB0

DB1

DB2

DB3

DB4

DB5

DB6(SCLK)

DB7(SID)

C68

RESETB

RW_WR

E_RD

CS2

CS1B

OSCILLATOR

I/O

BUFFER

STATUS REGISTER INSTRUCTION REGISTER

CLS

56 COMMON

DRIVER CIRCUITS

COMS

COM53

COM0

COMS

SEG99

SEG98

SEG66

SEG65

SEG64

SEG1

SEG0

100 SEGMENT

DRIVER CIRCUITS

TEMPS

Figure 1. Block Diagram

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

PAD CONFIGURATION

ррр ррррррррррррррррррр

- - - - - - - - - -

ррррррррррррррррррр

ððð

117

228

116

22987258

KS0717

(TOP VIEW)

(0,0)

рррррррррррррррррррррр

- - - - - - - - - -

ррррррррррррррррррррррр

ðððð

- - - -

ðððð

ðððð ðððð

Figure 2. KS0717 Chip Configuration

Table 1. KS0717 Pad Dimensions

Size

Item Pad No.

X Y

Unit

Chip size - 9000 2350

1 to 86 90

Pad pitch

87 to 258 70

1 to 86 56 114

87 to 116 108 50

117 to 228 50 108

Bumped pad size

229 to 258 108 50

Bumped pad height 1 to 258 17 (Typ.)

µm

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

(-3855, -500)

30µm 30µm 30µm

(+3815, -548)

42µm 108µm

108

(-4170, +1065)

(+4170, +1065)

42µm108µm

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

No. Name X Y No. Name X Y No. Name X Y

1 DUMMY -3825 -1051 51 C3- 675 -1051 101 COM13 4341 -35 2 FRS -3735 -1051 52 C1- 765 -1051 102 COM12 4341 35 3 M -3645 -1051 53 C1- 855 -1051 103 COM11 4341 105 4 CL -3555 -1051 54 C1+ 945 -1051 104 COM10 4341 175 5 DISP -3465 -1051 55 C1+ 1035 -1051 105 COM9 4341 245 6 VSS -3375 -1051 56 C1+ 1125 -1051 106 COM8 4341 315 7 CS1B -3285 -1051 57 C2+ 1215 -1051 107 COM7 4341 385 8 CS2 -3195 -1051 58 C2+ 1305 -1051 108 COM6 4341 455

9 VDD -3105 -1051 59 C2- 1395 -1051 109 COM5 4341 525 10 E_RD -3015 -1051 60 C2- 1485 -1051 110 COM4 4341 595 11 RESETB -2925 -1051 61 C2- 1575 -1051 111 COM3 4341 665 12 VSS -2835 -1051 62 VDD 1665 -1051 112 COM2 4341 735 13 RS -2745 -1051 63 VEXT 1755 -1051 113 COM1 4341 805 14 RW_WR -2655 -1051 64 REF 1845 -1051 114 COM0 4341 875 15 DB0 -2565 -1051 65 VSS 1935 -1051 115 COMS 4341 945 16 DB1 -2475 -1051 66 V1 2025 -1051 116 DUMMY 4341 1015 17 DB2 -2385 -1051 67 V1 2115 -1051 117 DUMMY 3885 1016 18 DB3 -2295 -1051 68 V2 2205 -1051 118 DUMMY 3815 1016 19 DB4 -2205 -1051 69 V2 2295 -1051 119 DUMMY 3745 1016 20 DB5 -2115 -1051 70 V3 2385 -1051 120 DUMMY 3675 1016 21 DB6 -2025 -1051 71 V3 2475 -1051 121 DUMMY 3605 1016 22 DB7 -1935 -1051 72 V4 2565 -1051 122 DUMMY 3535 1016 23 VSS -1845 -1051 73 V4 2655 -1051 123 SEG0 3465 1016 24 MS -1755 -1051 74 V0 2745 -1051 124 SEG1 3395 1016 25 CLS -1665 -1051 75 V0 2835 -1051 125 SEG2 3325 1016 26 VDD -1575 -1051 76 VR 2925 -1051 126 SEG3 3255 1016 27 DCDC5B -1485 -1051 77 VR 3015 -1051 127 SEG4 3185 1016 28 C68 -1395 -1051 78 VSS 3105 -1051 128 SEG5 3115 1016 29 VSS -1305 -1051 79 VSS 3195 -1051 129 SEG6 3045 1016 30 VSS -1215 -1051 80 PS 3285 -1051 130 SEG7 2975 1016 31 VSS -1125 -1051 81 HPMB 3375 -1051 131 SEG8 2905 1016 32 VSS -1035 -1051 82 VDD 3465 -1051 132 SEG9 2835 1016 33 VSS -945 -1051 83 INTRS 3555 -1051 133 SEG10 2765 1016 34 VSS -855 -1051 84 TEMPS 3645 -1051 134 SEG11 2695 1016 35 VSS -765 -1051 85 VSS 3735 -1051 135 SEG12 2625 1016 36 DUTY -675 -1051 86 DUMMY 3825 -1051 136 SEG13 2555 1016 37 VDD -585 -1051 87 DUMMY 4341 -1015 137 SEG14 2485 1016 38 VDD -495 -1051 88 COM26 4341 -945 138 SEG15 2415 1016 39 VDD -405 -1051 89 COM25 4341 -875 139 SEG16 2345 1016 40 VDD -315 -1051 90 COM24 4341 -805 140 SEG17 2275 1016 41 VDD -225 -1051 91 COM23 4341 -735 141 SEG18 2205 1016 42 VDD -135 -1051 92 COM22 4341 -665 142 SEG19 2135 1016 43 VDD -45 -1051 93 COM21 4341 -595 143 SEG20 2065 1016 44 VOUT 45 -1051 94 COM20 4341 -525 144 SEG21 1995 1016 45 VOUT 135 -1051 95 COM19 4341 -455 145 SEG22 1925 1016 46 VOUT 225 -1051 96 COM18 4341 -385 146 SEG23 1855 1016 47 C3+ 315 -1051 97 COM17 4341 -315 147 SEG24 1785 1016 48 C3+ 405 -1051 98 COM16 4341 -245 148 SEG25 1715 1016 49 C3- 495 -1051 99 COM15 4341 -175 149 SEG26 1645 1016 50 C3- 585 -1051 100 COM14 4341 -105 150 SEG27 1575 1016

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

No. Name X Y No. Name X Y No. Name X Y

151 SEG28 1505 1016 201 SEG78 -1995 1016 251 COM48 -4341 -525 152 SEG29 1435 1016 202 SEG79 -2065 1016 252 COM49 -4341 -595 153 SEG30 1365 1016 203 SEG80 -2135 1016 253 COM50 -4341 -665 154 SEG31 1295 1016 204 SEG81 -2205 1016 254 COM51 -4341 -735 155 SEG32 1225 1016 205 SEG82 -2275 1016 255 COM52 -4341 -805 156 SEG33 1155 1016 206 SEG83 -2345 1016 256 COM53 -4341 -875 157 SEG34 1085 1016 207 SEG84 -2415 1016 257 COMS -4341 -945 158 SEG35 1015 1016 208 SEG85 -2485 1016 258 DUMMY -4341 -1015 159 SEG36 945 1016 209 SEG86 -2555 1016 160 SEG37 875 1016 210 SEG87 -2625 1016 161 SEG38 805 1016 211 SEG88 -2695 1016 162 SEG39 735 1016 212 SEG89 -2765 1016 163 SEG40 665 1016 213 SEG90 -2835 1016 164 SEG41 595 1016 214 SEG91 -2905 1016 165 SEG42 525 1016 215 SEG92 -2975 1016 166 SEG43 455 1016 216 SEG93 -3045 1016 167 SEG44 385 1016 217 SEG94 -3115 1016 168 SEG45 315 1016 218 SEG95 -3185 1016 169 SEG46 245 1016 219 SEG96 -3255 1016 170 SEG47 175 1016 220 SEG97 -3325 1016 171 SEG48 105 1016 221 SEG98 -3395 1016 172 SEG49 35 1016 222 SEG99 -3465 1016 173 SEG50 -35 1016 223 DUMMY -3535 1016 174 SEG51 -105 1016 224 DUMMY -3605 1016 175 SEG52 -175 1016 225 DUMMY -3675 1016 176 SEG53 -245 1016 226 DUMMY -3745 1016 177 SEG54 -315 1016 227 DUMMY -3815 1016 178 SEG55 -385 1016 228 DUMMY -3885 1016 179 SEG56 -455 1016 229 DUMMY -4341 1015 180 SEG57 -525 1016 230 COM27 -4341 945 181 SEG58 -595 1016 231 COM28 -4341 875 182 SEG59 -665 1016 232 COM29 -4341 805 183 SEG60 -735 1016 233 COM30 -4341 735 184 SEG61 -805 1016 234 COM31 -4341 665 185 SEG62 -875 1016 235 COM32 -4341 595 186 SEG63 -945 1016 236 COM33 -4341 525 187 SEG64 -1015 1016 237 COM34 -4341 455 188 SEG65 -1085 1016 238 COM35 -4341 385 189 SEG66 -1155 1016 239 COM36 -4341 315 190 SEG67 -1225 1016 240 COM37 -4341 245 191 SEG68 -1295 1016 241 COM38 -4341 175 192 SEG69 -1365 1016 242 COM39 -4341 105 193 SEG70 -1435 1016 243 COM40 -4341 35 194 SEG71 -1505 1016 244 COM41 -4341 -35 195 SEG72 -1575 1016 245 COM42 -4341 -105 196 SEG73 -1645 1016 246 COM43 -4341 -175 197 SEG74 -1715 1016 247 COM44 -4341 -245 198 SEG75 -1785 1016 248 COM45 -4341 -315 199 SEG76 -1855 1016 249 COM46 -4341 -385 200 SEG77 -1925 1016 250 COM47 -4341 -455

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pins Description

Name I/O Description

VDD Supply Power supply VSS Supply Ground

LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier

for application. Voltages should have the following relationship; V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias.

LCD bias V1 V2 V3 V4

1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

V0 V1 V2 V3 V4

I/O

LCD DRIVER SUPPLY

Table 4. LCD Driver Supply Pins Description

Name I/O Description

C1- O Capacitor 1 negative connection pin for voltage converter

C1+ O Capacitor 1 positive connection pin for voltage converter

C2- O Capacitor 2 negative connection pin for voltage converter

C2+ O Capacitor 2 positive connection pin for voltage converter

C3- O Capacitor 3 negative connection pin for voltage converter

C3+ O Capacitor 3 positive connection pin for voltage converter

VOUT I/O Voltage converter input / output pin

DCDC5B I

5 times boosting circuit enable input pin. When this pin is low in 4 times boosting circuit, the 5 times boosting voltage appears at VOUT

VR I

V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = “L”)

VEXT I External VREF input pin for the LCD power supply voltage regulator

REF I

Selects the external VREF voltage via the VEXT pin

− REF = "H": using the internal VREF

− REF = "L": using the external VREF

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

SYSTEM CONTROL

Table 5. System Control Pins Description

Name I/O Description

Master / Slave operation select pin

− MS = "H": master operation

− MS = "L": slave operation

The following table depends on the MS status.

MS CLS

OSC

circuit

Power supply

circuit

CL M FRS DISP

H Enabled Enabled Output Output Output Output

L Disabled Enabled Input Output Output Output

L - Disabled Disabled Input Input Output Input

MS I

CLS I

Built-in oscillator circuit enable / disable select pin

− CLS = “H”: enable

− CLS = “L”: disable (external display clock input to CL pin)

CL I/O

Display clock input / output pin When the KS0717 is used in master / slave mode (multi-chip), the CL pins must be connected each other.

M I/O

LCD AC signal input / output pin When the KS0717 is used in master/slave mode (multi-chip), the M pins must be connected each other.

− MS = “H”: output

− MS = “L”: input

FRS O

Static driver segment output pin This pin is used together with the M pin.

DISP I/O

LCD display blanking control input/output When KS0717 is used in master/slave mode

(multi-chip), the DISP pins must be connected each other.

− MS = “H”: output

− MS = “L”: input

INTRS I

Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level.

− INTRS = "H": use the internal resistors

− INTRS = "L": use the external resistors

V0 voltage is controlled by VR pin and external resistive divider.

HPMB I

Power control pin of the power supply circuit for LCD driver

− HPMB = "L": high power mode

− HPMB = "H": normal mode

This pin is valid in master mode

TEMPS I

Test pin This pin is fixed to High or Low.

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Table 6. System Control Pins Description (Continued)

Name I/O Description

DUTY I

The LCD driver duty ratio select pin

− DUTY = "L": 1/34

− DUTY = "H": 1/55

NOTE: DUMMY – These pins should be opend (floated).

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

MICROPROCESSOR INTERFACE

Table 7. Microprocessor Interface Pins Description

Name I/O Description

RESETB I

Reset input pin When RESETB is “L”, initialization is executed.

Parallel / Serial data input select input

Interface

mode

Chip

select

Data /

instruction

Data Read / Write Serial clock

H Parallel

CS1B,

CS2

RS DB0 to DB7

E_RD

RW_WR

L Serial

CS1B,

CS2

RS SID (DB7) Write only SCLK (DB6)

PS I

*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.

C68 I

Microprocessor interface select input pin

− C68 = "H": 6800-series MPU interface

− C68 = "L": 8080-series MPU interface

CS1B

CS2

Chip select input pins Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB7 may be high impedance.

RS I

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

C68 MPU type RW_WR Description

H 6800-series RW

Read/Write control input pin

− RW = “H”: read

− RW = “L”: write

L 8080-series /WR

Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.

RW_WR I

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Table 8. Microprocessor Interface Pins Description (Continued)

Name I/O Description

Read / Write execution control pin

C68 MPU type E_RD Description

H 6800-series E

Read/Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 are in an output status.

− RW = “L”: The data on DB0 to DB7 are latched at the falling edge of the E signal.

L 8080-series /RD

Read enable clock input pin When /RD is “L”, DB0 to DB7 are in an output status.

E_RD I

DB0

DB7

I/O

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID)

When chip select is not active, DB0 to DB7 may be high impedance.

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

LCD DRIVER OUTPUTS

Table 9. LCD Driver Outputs Pins Description

Name I/O Description

LCD segment driver outputs The display data and the M signal control the output voltage of segment driver.

Segment driver output voltage

Display data M

Normal display Reverse display H H V0 V2 H L VSS V3

L H V2 V0 L L V3 VSS

Power save mode VSS VSS

SEG0

SEG99

LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver.

Scan data M Common driver output voltage

H H VSS H L V0

L H V1 L L V4

Power save mode VSS

COM0

COM53

COMS O

Common output for the icons The output signals of two pins are same. When not used, these pins should be left open. In multi-chip (master / slave) mode, all COMS pins on both master and slave units are the same signal.

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for chip selection. The KS0717 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.

Parallel / Serial Interface

KS0717 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 10.

Table 10. Parallel / Serial Interface Mode

PS Type CS1B CS2 C68 Interface mode

H 6800-series MPU mode

H Parallel CS1B CS2

L 8080-series MPU mode

L Serial CS1B CS2

*×

Serial-mode

*×: Don't care

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in Parallel Interface and the type of MPU is selected by C68 as shown in table 11. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 12.

Table 11. Microprocessor Selection for Parallel Interface

C68 CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus

H CS1B CS2 RS E RW DB0 to DB7 6800-series L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series

Table 12. Parallel Data Transfer

Common 6800-series 8080-series

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

Description

H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

Serial Interface (PS = "L")

When the KS0717 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.

CS1B

CS2

SID

SCLK

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. Serial Interface Timing

Busy Flag

The Busy Flag indicates whether the KS0717 is operating or not. When DB7 is “H” in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Data Transfer

The KS0717 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure

5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.

/WR

DB0 to DB7

N D(N) D(N+1) D(N+2) D(N+3)

Internal signals

MPU signals

/WR

BUS HOLDER

COLUMN ADDRESS

N N+1 N+2 N+3

N D(N) D(N+1) D(N+2) D(N+3)

Figure 4. Write Timing

55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD KS0717

/WR

/RD

DB0 to DB7

MPU signals

Dummy D(N) D(N+1)

Internal signals

/WR

/RD

BUS HOLDER

COLUMN ADDRESS

D(N)

D(N+1)

D(N+2)

N+1

N+2

N+3

Figure 5. Read Timing

KS0717 55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 65-row by 100-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.

COM0 - -

COM1 - COM2 - COM3 - COM4 - -

DB0 0 0 1 - - 0 DB1 1 0 0 - - 1 DB2 0 1 1 - - 0 DB3 1 0 1 - - 0

DB4 0 0 0 - - 1

Display Data RAM LCD Display

Figure 6. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit Line Address register changed by only the Initial Display Line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 100-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.

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