Samsung KS0093 Datasheet

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

KS0093

written permission of LCD Driver IC Team.

Prepared by: Won-Sik, Kang

K2w3@samsung.co.kr

Nov. 1999.

Ver. 0.4

Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

KS0093 Specification Revision History

Version Content Date

0.0 Original Jun.1998

0.1 Miss typed contents changed Jan.1999

0.2 RESETB pin VIL,VIH added Mar.1999

0.3 VDD change (2.4V~5.5V -> 2.4V~3.6V) Nov.1999

0.4 VDD change (2.4V~3.6V -> 2.4V~5.5V) Dec.1999

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

CONTENTS

INTRODUCTION.......................................................................................................................................... 1

FEATURES ................................................................................................................................................. 1

BLOCK DIAGRAM ...................................................................................................................................... 3

PAD CONFIGURATION............................................................................................................................... 4

PAD CENTER COORDINATES...................................................................................................................5

PIN DESCRIPTION...................................................................................................................................... 6

POWER SUPPLY.................................................................................................................................6

LCD DRIVER SUPPLY......................................................................................................................... 6

SYSTEM CONTROL............................................................................................................................. 7

MPU INTERFACE ................................................................................................................................ 7

LCD DRIVER OUTPUTS...................................................................................................................... 8

TEST....................................................................................................................................................8

FUNCTION DESCRIPTION.......................................................................................................................... 9

SYSTEM INTERFACE..........................................................................................................................9

ADDRESS COUNTER (AC)................................................................................................................ 13

DISPLAY DATA RAM (DDRAM)......................................................................................................... 13

CHARACTER GENERATOR ROM (CGROM)..................................................................................... 13

CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 15

SEGMENT ICON RAM (ICONRAM).................................................................................................... 17

LOW POWER CONSUMPTION MODE .............................................................................................. 18

LCD DRIVER CIRCUIT....................................................................................................................... 18

INSTRUCTION DESCRIPTION .................................................................................................................. 19

INITIALIZING & POWER SAVE MODE SETUP......................................................................................... 29

HARDWARE RESET.......................................................................................................................... 29

INITIALIZING AND POWER SAVE SETUP......................................................................................... 30

LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 33

VOLTAGE CONVERTER.................................................................................................................... 34

VOLTAGE REGULATOR .................................................................................................................... 35

ELECTRONIC CONTRAST CONTROL (32 STEPS)........................................................................... 36

VOLTAGE GENERATOR CIRCUIT .................................................................................................... 38

MPU INTERFACE...................................................................................................................................... 39

APPLICATION INFORMATION FOR LCD PANEL.................................................................................... 41

FRAME FREQUENCY............................................................................................................................... 43

MAXIMUM ABSOLUTE RATINGS............................................................................................................. 44

ELECTRICAL CHARACTERISTICS.......................................................................................................... 45

DC CHARACTERISTICS.................................................................................................................... 45

AC CHARACTERISTICS.................................................................................................................... 47

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

INTRODUCTION

The KS0093 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 2 or 3 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator, voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line vertical scroll functions are supported.

FEATURES

Driver Outputs

- Common outputs: 26 common

- Segment outputs: 80 segment

Applicable Panel Size

Font Display Duty Contents of outputs

2-line x 16 characters 1 / 17 2 x 16 characters + 80 icons

5 x 8

3-line x 16 characters 1 / 25 3 x 16 characters + 80 icons

Internal Memory

- Character Generator ROM (CGROM): 10,240 bits (256 characters x 5 x 8 dots)

- Character Generator RAM (CGRAM): 320 bits (8 characters x 5 x 8 dots)

- Display Data RAM (DDRAM): 512 bits (16 characters x 4 lines)

- Segment Icon RAM (ICONRAM): 80 bits (80 icons)

MPU Interface

- No busy MPU interface (no busy check or no execution waiting time)

- 8-bit parallel interface mode: 68-series and 80-series are available.

- 4-bit parallel interface mode: 68-series and 80-series are available.

- Serial interface mode: 4 pins clock synchronized serial interface

Function Set

- Various instruction set: display control, power save, power control, etc.

- COM / SEG bi-directional (4-type LCD application available)

- H/W reset (RESETB)

Built-in Analog Circuit

- Internal RC oscillator circuit or external clock

- Electronic volume for contrast control (32 steps)

- Voltage converter / voltage regulator / voltage follower & bias circuit

Low Power Operation

- Sleep mode operation (5µA Max.)

- Normal mode operation (80µA Max.)

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Operating Voltage Range

- Power supply voltage (VDD): 2.4V ~ 5.5V

- LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.

Package Type

- Gold bumped chip or TCP

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

(DR)

BLOCK DIAGRAM

RESETB

M I

CSB

RW_WR

E_RD

DB7

(SI)

DB6

(SCL)

DB5-

DB4

DB3-

DB0

Parallel

Interface

4 bit/8 bit

Serial

Interface

Input Buffer

Data Output

Icon

RAM

80 bits

Instruction

(IR)

Data

(OR)

Character Generator

RAM

(CGRAM)

320 bits

Address

Counter

Instruction

Decoder

Data RAM

(DDRAM)

Character Generator

ROM

(CGROM)

10240 bits

Display

512 bits

Timing GeneratorOscillator

Cursor

and

Blink

Controlle

80 bits

Shift

25 bits

Shift

80 bits

Latch

Circuit

Common

Driver

Segment

Driver

LCD

Driver

Voltage

Selector

COM1-

COM24 COM I1

COM I2

SEG1-

SEG80

5 5

GND

Voltage Converter Voltage Regulator Voltage Follower & Bias Resistor

CAP1+ CAP1- CAP2+ CAP2- VOUT V0 VEXT REF VR V1 V2 V3 V4 DIRS

Segment Data Conversion

LCD Driving Power Circuit

Figure 1. Block Diagram

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

............................

...

73 87

166

(-3065, -445)

(-2965, -405)

108

(-3440, +740)

(+3440, +740)

PAD CONFIGURATION

167

179

(0,0)

...........................

Figure 2. Pad Configuration

Table 1. KS0093 Pad Dimensions

Item Pad No.

Chip size - 7020 1620

1 ~ 73 90

Pad pitch

74 ~ 179 80

1 ~ 73 60 100

74 ~ 86 100 50

Bumped pad size

87 ~ 166 50 100

X Y

DUMMY PAD PAD

Size

Unit

µm

Bumped pad height All pad 17

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

167 ~ 179 100 50

30µm 30µm 30µm

42µm 108µm

42µm108µm

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

Pad

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Pad

name

DUMMY DUMMY DUMMY DUMMY DUMMY RS VSS RW_WR VDD E_RD CSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD VDD VDD VSS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 V0 V0 VR VR VOUT VOUT CAP2CAP2CAP2+ CAP2+ CAP1CAP1CAP1+ CAP1+ VEXT VSS VSS VSS REF DIRS VDD VDD VDD CK VSS

X Y

-3240

-3150

-3060

-2970

-2880

-2790

-2700

-2610

-2520

-2430

-2340

-2250

-2160

-2070

-1980

-1890

-1800

-1710

-1620

-1530

-1440

-1350

-1260

-1170

-1080

-990

-900

-810

-720

-630

-540

-450

-360

-270

-180

-90 0

90 180 270 360 450 540 630 720 810 900 990

1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070

-700

Pad

No.

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

Pad

name

PS VDD IF VSS MI VDD RESETB TEST DUMMY DUMMY DUMMY DUMMY DUMMY COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34

X Y

2160 2250 2340 2430 2520 2610 2700 2790 2880 2970 3060 3150 3240 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3160 3080 3000 2920 2840 2760 2680 2600 2520 2440 2360 2280 2200 2120 2040 1960 1880 1800 1720 1640 1560 1480 1400 1320 1240 1160 1080 1000

920 840 760 680 600 520

-700

-520

-440

-360

-280

-200

-120

-40 40

120 200 280 360 440 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700

Pad

No.

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179

Pad

name

SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9

X Y

440 360 280 200 120

-40

-120

-200

-280

-360

-440

-520

-600

-680

-760

-840

-920

-1000

-1080

-1160

-1240

-1320

-1400

-1480

-1560

-1640

-1720

-1800

-1880

-1960

-2040

-2120

-2200

-2280

-2360

-2440

-2520

-2600

-2680

-2760

-2840

-2920

-3000

-3080

-3160

-3400

700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 440 360 280 200 120

-40

-120

-200

-280

-360

-440

-520

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Pin Description

Name I/O Description

VDD

Power

Power supply Connect to MPU power supply pin.

VSS

V0 V1 V2 V3 V4

LCD DRIVER SUPPLY

Name I/O Description

CAP1+ O Capacitor + connecting pin for the internal voltage converter

CAP1- O Capacitor - connecting pin for the internal voltage converter

CAP2+ O Capacitor + connecting pin for the internal voltage converter

CAP2- O Capacitor - connecting pin for the internal voltage converter

VOUT I/O DC/DC voltage converter output (7.2V)

VR I

VEXT I

REF I

0V (GND) Bias voltage level for LCD driving

Voltages should have the following relationship; V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the built-in power circuit is active and internal 1/5 bias resistors are used.

LCD bias

I/O

1/5 bias

When the built-in power circuit is active and internal 1/4 bias resistors are used.

LCD bias

1/4 bias

Table 3. Pin Description (Continued)

Voltage adjust pin This pin gives a voltage between V0 and VSS by resistance-division of

voltage. External reference voltage for internal regulator (instead of the internal

VREF, 2V) REF = "Low (VSS)": VEXT is not used (open). REF = "High (VDD)": VEXT is reference input voltage of internal voltage regulator.

Select the input voltage of internal voltage regulator REF = "Low (VSS)": The input voltage of internal Voltage regulator is the internal VREF(2V). REF = "High (VDD)": The input voltage of internal Voltage regulator is the voltage of VEXT.

V1 V2 V3 V4

(4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

V1 V2 V3 V4

(3/4) x V0 (2/4) x V0 (1/4) x V0

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

SYSTEM CONTROL

Table 3. Pin Description (Continued)

Name I/O Description

External clock input. It must be fixed to "High" or "Low" when the internal

CK I

MI I

PS I

IF I

DIRS I

oscillation circuit is used. In case of the external clock mode, CK is used as the clock and OS bit should be OFF.

MPU interface selection input MI = "Low": 80-series MPU MI = "High": 68-series MPU

Parallel / serial selection input When PS = "Low": serial mode When PS = "High": 4-bit / 8-bit bus mode

Interface data length selection pin for parallel data input When PS = "Low" IF = "Low" or "High": serial interface mode When PS = High IF = "Low": 4-bit bus mode IF = "High": 8-bit bus mode

SEG direction selection input When DIRS = "Low” SEG1 → SEG2 → SEG79 → SEG80 When DIRS = "High” SEG80 → SEG79 → SEG2 → SEG1

MPU INTERFACE

Table 3. Pin Description (Continued)

Name I/O Description

RESETB I

CSB I

RS I

RW_WR I

E_RD I

Reset input KS0093 is initialized while RESETB is low.

Chip selection input KS0093 is selected while CSB is low.

In 80-series MPU interface mode This pin is connected to WR pin of MPU and is a active low write signal In 68-series MPU interface mode This pin is connected to R/W pin of MPU When RW_WR = "Low", write mode When RW_WR = "High", read mode

In 80-series MPU interface mode This pin is connected to RD pin of MPU and is a active low read signal In 68-series MPU interface mode This pin is connected to E pin of MPU and enable read or write command according to RW_WR signal.

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Table 3. Pin Description (Continued)

Name I/O Description

DB0 ∼ DB3 DB4 ∼ DB5

DB6 (SCL),

DB7 (SI)

I/O When 8-bit bus mode, used as bi-directional data bus DB0 ∼ DB7

LCD DRIVER OUTPUTS

Name I/O Description

COM1 ∼ COM24

COMI1, COMI2 O SEG1 ∼ SEG80

O Common signal output for driving LCD

O Segment signal output for driving LCD

TEST

Name I/O Description

TEST I

During 4-bit bus mode, only DB4 ∼ DB7 are used. In this case DB0 ∼ DB3 pins are not used.

When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI) is used as serial data input pin.

Table 3. Pin Description (Continued)

Common signal output for icon display These are the same signal but the name is different.

Table 3. Pin Description (Continued)

Test pin This pin is not used for normal operation. TEST: Open

NOTE: DUMMY – These pins should be opened (floated).

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

FUNCTION DESCRIPTION

SYSTEM INTERFACE

KS0093 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by MI pin.

Table 4. Various Kinds of MPU Interface according to PS, MI and IF

PS MI IF CSB RS RW_WR E_RD DB0∼∼DB3 DB4∼∼DB5 DB6 DB7

68 series

Bus mode

(H)

Serial mode

(L)

NOTES:

1. Don’t care (high, low or open)

2. Fixed high (VDD) or low (VSS)

(H)

80 series

(L)

(H)/(L)

8 bit (H) CSB RS R/W E DB0∼DB3 DB4∼DB5 DB6 DB7

4 bit (L) CSB RS R/W E ∗

8 bit (H) CSB RS WR RD DB0∼DB3 DB4∼DB5 DB6 DB7

4 bit (L) CSB RS WR RD

(2)

(H)/(L) CSB RS (H)/(L) (H)/(L)

(1)

∗

∗ ∗

DB4∼DB5 DB6 DB7

SCL SI

PS: "High" = bus mode, "Low" = serial mode MI: "High" = 68-series MPU, "Low" = 80-series MPU IF: "High" = 8 bit mode, "Low" = 4 bit mode (PS: "High") CSB: "High" = chip is not selected, "Low" = chip is selected RS: "High" = data register, "Low" = instruction register RW_WR: Read / Write indicating signal in 68 mode or active low signal for enabling write in 80 mode E_RD: Active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode. SCL (DB6): Serial clock input SI (DB7): Serial data input

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

CSB

RW_WR

E_RD

DB7∼DB0

Data

Interface with MPU in Parallel Mode (PS = "High")

During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and one of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to store instruction code transferred from MPU. To select DR or IR register, RS input pin is used.

During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used as temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAMs is selected by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit bus mode (figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting, first and second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy read make the address counter (AC) increased by 1. So it is recommended to set address again before writing. The instruction read cycle is not supported and it is regarded as a no operation cycle.

In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7∼DB4) by two times. The high order bits (for 8-bit mode DB7∼DB4) are written before the low order bits (for 8-bit mode DB3∼DB0) in write and low order bits (for 8bit mode DB3∼DB0) are read before the high order bits (for 8-bit mode DB7∼DB4) in read transaction. The DB0∼DB3 pins are floated in this 4-bit bus mode. After RESETB resets, KS0093 considers first 4-bit data from MPU as the high order bits.

Valid

Instruction

NOP RAM

Dummy

Data

Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

CSB

RW_WR

E_RD

DB7∼DB0

Data

CSB

RW_WR

E_RD

DB7∼DB4

4-bit

CSB

RW_WR

E_RD

DB7∼DB4

4-bit

Valid

Instruction

NOP RAM

Dummy

Data

Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

upper

lower

Instruction Write Dummy Read Data WriteNOP

lower

upper

lower

Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

upper

lower

upper

lower

Instruction Write Dummy Read Data WriteNOP RAM Read

Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

KS0093 26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Interface with MPU in Serial Mode (PS = "Low")

When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, RESETB (reset input), SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB(chip selection input) are used.

By setting CSB to "Low", KS0093 can receive SCL input. If CSB is set to "High", KS0093 resets the internal 8-bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6).

At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS input of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).

CSB

SI (DB7)

SCL (DB6)

D7 D6 D5 D4 D3 D2 D1 D0 D7

1 2 3 4 5 6 7 8 9

Figure 7. Timing Diagram of Serial Data Transfer

26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD KS0093

ADDRESS COUNTER (AC)

Address Counter (AC) in KS0093 stores DDRAM/ CGRAM/ ICONRAM address. After writing into or reading from

DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and stores the address among DDRAM / CGRAM / ICONRAM.

DISPLAY DATA RAM (DDRAM)

DDRAM stores display data of maximum 64 x 8 bits (Max. 64 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number.

1st Ch. 16th Ch.

COM1 ∼ COM8 COM9 ∼ COM16

Hidden Line Hidden Line

SEG1 SEG80

COM1 ∼ COM8 COM9 ∼ COM16 COM17 ∼ COM24

Hidden Line

SEG1 SEG80

04 05 06 07 08 09 0A 0B 0C 0D 0E 0F00 01 02 03 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F10 11 12 13 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F20 21 22 23 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F30 31 32 33

(1) 2 line mode DDRAM Address

04 05 06 07 08 09 0A 0B 0C 0D 0E 0F00 01 02 03 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F10 11 12 13 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F20 21 22 23 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F30 31 32 33

(2) 3 line mode DDRAM Address

Figure 8. DDRAM Address

CHARACTER GENERATOR ROM (CGROM)

CGROM has 5 x 8-dot 256 characters. The CG bit of the instruction table selects the 8 characters (00h ~ 07h) of CGROM or CGRAM.

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