Page 1
Chapter 2
Circuit Description
2-1 008 Base B’d..............................................2-3
2-2 Mem Card................................................2-14
2-3 3 TRK Card..............................................2-17
2-4 6 TRK Card..............................................2-18
2-5 8 SLI Card................................................2-19
2-6 2 SLI Card................................................2-21
2-7 8 DLI Card................................................2-22
2-8 MISC Card...............................................2-23
2-9 S0T0 Card................................................2-28
2-10 PRI Card ..................................................2-36
2-11 PLL B’d ....................................................2-40
2-12 Ringer B’d................................................2-42
2-13 SIM Module..............................................2-42
2-14 DPIM Module...........................................2-45
2-15 Digital Keyset...........................................2-47
2-16 KDB-d B’d................................................2-60
2-17 KDB-s B’d ................................................2-62
2-18 Power Supply...........................................2-63
Page 2
Page 3
Chapter 2. Circuit Description
2-1 008 Base B’d
°‹008 Base B’d performs as a Mother B’d. The processor (MC68EC000) collects and analyzes
all the signal data occurred when the system operates, and determines the system operation.
°‹Memory consists of 1 M Bytes program ROM (To expand system program, ROM 1M Bytes
can be added) in the MEM B’d, and 256K Bytes RAM in the MEM B’d (basic 256K Bytes and
option 256K Bytes) .
512K Bytes RAM in the RAM B’d (include option 256K Bytes) is backed up by the battery to
save data in case of long time power failure (about 1 week). The backup switch should be
ON position to back up the memory.
°‹DTMF SENDER, TONE GENERATOR, TIMING GENERATOR, DSP TONE RECEIVER,
TIME SWITCH & CONFERENCE are composed into one ASIC STC-9604.
°‹DSP in the DKP ENGINE STC9604 receives the DTMF signal from the C.O. line. It can treat
4 channels (MAX) received at the same time.
°‹Time switch of the STC9604 accomodates 256 channels. Conference can be performed with
6 groups of 5 parties.
2-3
Page 4
Chapter 2. Circuit Description
2-1-1 Block Diagram
MEM CARD
REAL TIME CLOCK(72423)
RESET AND WATCHDOG
ROM BASIC 1M bytes
Option. 1M bytes
RAM BASIC 256K bytes
Option. 256K byte
RING BOARD
SINE-WAVE RING
GENERATION
4SLI CARD
RING RELAY CONTROL
SLT HOOK DETETION
SLT LOOP DISCONNECT
MISC1(2) CARD
(AA 4 CHANNEL)
DTMFR 4 CHANNEL
B.G.M 1 PORT
DRY CONTACT 3 PORT
SERIAL DATA INTERFACE
R2 MFC or CALLER ID°ø4
CPU : 68EC000FN8/16
DKP ENGINE : STC9604
INTERRUPT LOGIC
LINE INTERFACE LOGIC
2/4 SLT CONTROL
B.G.M 1 PORT
M.O.H 1 PORT
DRY CONTACT 1
8 DGP INTERFACE
SLOT 1-6 : LINE CARD
1) EXP-8DLI : ANY SLOT
2) EXP-8SLI : ANY SLOT
3) EXP-6TRK : ANY SLOT
4) VDIAL : ANY SLOT
5) AA : ANY SLOT
6) EXP-3TRK : ANY SLOT
7) 4S0T0 : ANY SLOT
SLOT 7 : DCS PRI CARD
DKP MAIN ENGINE
STC9604, 208 PIN ASIC
CLOCK GENERATOR
TONE GENERATOR
DSP TONE RECEIVER
DECODING LOGIC
T-S/W & CONFERENCE
PROCESSOR SUPPORT
LOGIC
DPLL FOR 4 S0T0
2-4
Page 5
Chapter 2. Circuit Description
2-1-2 Memory Map
ADDRESS SIG NAME READ WRITE REMARK
0XXXXX
1XXXXX
OROMEN1B
OROMEN2B
PROGRAM ROM(1MBYTE) : WORD
OPERATION, 27C4001°ø2 MEMCARD
PROGRAM ROM(1MBYTE) : WORD
OPERATION, 27C4001°ø2MEM CARD,
OPTION
2XXXXX
300001
300011
300021
3XXXXX 300031
300041
300051
300061
300071
400XX1
420001
420011
420021
420031
420041
OPCMCIAENB
CPM
DTMF/TONE
DETECTION
CONTROL
RTC
RESULT OF CH1 DETECTION
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ AA DSP SW RSTB
DSP CONTROL DSP CONTROL
SPEECH MEMORY £ ≠
CONF.1 CONTROL CONF.1 CONTROL
CONF.2 CONTROL CONF.2 CONTROL
CONF.3 CONTROL CONF.3 CONTROL
CONF.4 CONTROL CONF.4 CONTROL
CONF.5 CONTROL CONF.5 CONTROL
DETECT CNTL L
DETECT CNTL H
DOWNLOAD
DOWNLOAD
4XXXXX
420051
420061
420071
420801~
4209FF
440001~
440FFF
460001~
461FFF
TIME SWITCH
CONF.6 CONTROL
CONF.6 CONTROL BIT7=°Æ1°Ø: CM
READ ENABLE
OVERFLOW HIGHWAY ENABLE
STATUS CONTROL
£ ≠
SIGNALING
MEMORY
CONTROL CONTROL
MEMORY L
CONTROL CONTROL
MEMORY H
SM REGISTER
READ ENABLE
£ ≠
2-5
Page 6
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
5XXXXX
TMC
£ ≠
6XXXXX
7XXXXX
800000~81FFFF
820000~83FFFF
840000~85FFFF
860000~87FFFF
880000~89FFFF
8A0000~8BFFFF
8C0000~8DFFFF
8EXXXX
QDMC
SIO
LINE CARD
ENABLE
/INTIDB
£ ≠
INTERNAL UART CONTROL & DPLL
MISC EN
RESERVED
RESERVED
SLOT1 (/CS1)
SLOT2 (/CS2)
SLOT3 (/CS3)
/UART (68681) EN
INTSIO : INT SIO (INTS) DATA FROM
SLOT1 TO SLOT7
D0 : /INTS0 (INTERNAL DMC)
D1 : /INTS1 (CS1 EN)
D2 : /INTS2 (CS2 EN)
D3 : /INTS3 (CS3 EN)
D4 : /INTS4 (EXP1 EN)
D5 : /INTS5 (EXP2 EN)
D6 : /INTS6 (EXP3 EN)
D7 : /INTU (UART & MODEM INT : MISC)
8FXXXX
9XXXXX
A00000~A7FFFF
A80000~AFFFFF
B00000~B7FFFF
B80000~BFFFFF
/INTIDB
/RAM1EN
/RAM2EN
/RAM3EN
/RAM4EN
INTDASL : INT DASL(INTD) DATA FROM
SLOT1 TO SLOT7
D0 : /INTS0 (INTERNAL DMC)
D1 : /INTS1 (CS1 EN)
D2 : /INTS2 (CS2 EN)
D3 : /INTS3 (CS3 EN)
D4 : /INTS4 (EXP1 EN)
D5 : /INTS5 (EXP2 EN)
D6 : /INTS6 (EXP3 EN)
RESERVED
512KBYTES, 681000°ø4, MEM CARD
512KBYTES, 681000°ø4, RESERVED
512KBYTES, 681000°ø4, RESERVED
512KBYTES, 681000°ø4, RESERVED
2-6
Page 7
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
C00000~C1FFFF
/EXP1 EN
C20000~C3FFFF
C40000~C5FFFF
C60000~C7FFFF
C80000~C9FFFF
CA0000~CBFFFF
CC0000~CDFFFF
CE0000~CFFFFF
D00007~
D007FF
D00800~
D00FFF
D01000~
D017FF
D01801
D01811
D01821
LINE CARD
ENABLE(RSVB)
DTMF/TONE
GENERATION
/EXP2 EN
/EXP3 EN
/EXP4 EN
RESERVED
/WAT EN
/LED EN(monitor)
RING SYNC. INTERRUPT CLEAR
GAIN GAIN
STEP SIZE STEP SIZE
ACC RAM ACC RAM
CADENCE1 CADENCE1
CADENCE2 CADENCE2
MODE MODE
DXXXXX D01831
D01841
D01851
D01861
D01871
D01C01
D01C11
D01C21
D01C31
CONTROL
REGISTERS
CPM
DTMF/TONE
DETECTION
£ ≠ CNTL REG A
£ ≠ CNTL REG B
£ ≠ CNTL REG C
£ ≠ CNTL REG D
£ ≠ CNTL REG E
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
2-7
Page 8
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
E00001
RESULT OF CH1 DETECTION
DETECT CNTL L
EXXXXX
E00011
E00021
E00031
E00041
E00051
E00061
E00071
E00081
E00091
E000A1
E000B1
F00001
F00011
F00021
F00031
EXP 1
(DSPMODE)
DTMF/TONE
DETECTION
CONTROL
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ DSP SW RSTB
DSP CONTROL DSP CONTROL
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
RESULT OF CH1 DETECTION
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DETECT CNTL H
DOWNLOAD CNTL L
DOWNLOAD CNTL H
DETECT CNTL L
DETECT CNTL H
DOWNLOAD CNTL L
DOWNLOAD CNTL H
FXXXXX
8, 9, E, FXXXXX
F00041
F00051
F00061
F00071
F00081
F00091
F000A1
F000B1
EXP 2
(DSPMODE)
DTMF/TONE
DETECTION
CONTROL
OEXDENB
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ DSP SW RSTB
DSP CONTROL DSP CONTROL
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
£ ≠
2-8
Page 9
°‹A0 - A23 (Address Bus) : 16M byte Memory
°‹D0 - D15 (Data Bus) : LDS for D0 - D7, UDS for D8 - D15
°‹AS (Address Strobe) : Address is available while AS is low
°‹R/W (Read/Write)
°‹UDS, LDS (Upper and Lower Data Strobe)
°‹DTACK (Data Transfer Acknowledge) : Wait signal
°‹IPL2 ~ IPL0 (Interrupt Priority Level) : Interrupt priority level of 68EC000 is determined
with this 3 signal inputs.
Engine (STC-9604)
Clock generator
The 16MHz system clock output from 16MHz oscillator is provided to STC9604. Engine
(STL9604) generates 8.192MHz, 4.096MHz, 2.048MHz, 1KHz, and 20/25Hz, 8.192MHz is
provided to CPU and the rests are provided to the line control IC.
Time Switch
It performs switching for 8 highway (total 256 channels). 8-steps gain control is available.
Chapter 2. Circuit Description
2-9
UDS
0
0
1
1
LDS
0
1
0
1
Data Byte Selected
Word operation
Upper byte (D8 - D15)
Lower byte (D0 - D7)
No valid data
2-1-3 Circuit Description
CPU
CPU is fabricated using Motorola 68EC000FN8/16. 68EC000FN8/16 is compatible with 8-bit or
16-bit mode operation. 16-bit mode is available by setting MODE pin to high or open. In this
system. 16-bit mode is used. 8.192MHz supplied from STC9604 is used for clock and it is
required to apply over than 100ms for reset time.
Pin Description
Page 10
Chapter 2. Circuit Description
Digital Conference
It is possible to support 6 groups of 5 parties. Any 5 of 256 channels can be assigned to the
station who is joined into the conference.
Tone/DTMF Generation
It generates 15 Dual/signal tones and 16 DTMFs at each 32 channels by using the sine wave
from data in STC9604.
Tone/DTMF Detection
Highway data from the time slot determined in TSAC is supplied from IDSPIN (Pin61) of
STC9604. The input signal is converted to 8-bit parallel data and stored into the allocated
registers for each channels.
The DSP core (inside STC9604) starts detecting by reading the enabled channel PCM data at
every 125µs interrupt, Detecting is achieved only with tone detect control register enabled
channel from CH1 to CH4 during 125µs interrupt. If a valid tone or DTMF signal is detected, the
result is recorded to the relevant register of each channels. CPU will read the data at the
register.
Digital Line Interface (DLI)
8 DLIs equipped into the 008 Base B’d performs interface between SIM, DPIM, and digital
phone. It uses QDASL chip (TP3404). The QDASL uses 2B+D at each port.
Signal transmission is achieved with 144 kbps full duplex AMI (Alternative Marking Inversion)
code transmission mode. End to end communication supports voice channel B1 and B2, and
two extension phones can be connected to 1 port.
192 kbps is used for actual transmission between DLI and digital phone, 16 kbps for sync, and
the rests are used for null data.
Transmission distance between DLI and digital phone covers a maximum of 400m by using
AWG26 transmission code.
2-10
Page 11
Chapter 2. Circuit Description
Parallel control data out from UART of internal DMC (in the STC9604) is converted to serial
data and transmitted to DASL. DASL transmits the control data to the digital phone in a format
of AMI code. The control data out from the digital phone is transmitted to the CPU through the
reverse process.
Internal DMC interface
Address A4, 5, 8, 9, 10, 11, 16 are used for communication between DMC and CPU. There are
Addresses to read/write each port D CH’s data, to be masking INT status, to read INT status of
DASL and to be setting as the LOOP BACK MOOD for test. The interface includes the data bus
D0 - D7 and INT Rx0, Rx1, and INT Tx0, Tx1. The Rx INT will be enable when even one byte is
received in the buffer, and Tx INT will be enable when the buffer is empty.
If INT is enabled, CPU reads the INT status and performs INT service for the port of the
selected bit. The INT status is cleared as soon as CPU read it. For highway (B-CH) control
HC125 (Tristate Buffer) is located between the time switch and DASL, it is enabled by TRS
(pin14) of DASL. BCLKx (2.048MHz), B4M, and CCLK (1.028MHz) are provided for clock.
QDASL Interface
DX & DR can transmit D-CH’s serial data of each port. B-CH & D-CH are scrambled to the AMI
code and transmitted with line.
INT0 - INT1 are used to control the micro channel interrupt of each channel. DASL INT is
occured only when micro channel access. No signal (C0), Out of SYNC (C1), and Bipolar
violation (C7) are required to generate DASL INT. Since INT occurs only when power turns on
at first time and the DASL status is changed by some error, INT is designed to tie up with UART
Tx by using AND gate.
DGP Interface
DLT1 (T2-5, T7-10) is used for matching transformer. Resistance (100Ω) at L0 of DASL is for
matching Impedance. 2 µF are used to reduce noise. Zener Diode is for hazard protection.
2-11
Page 12
Chapter 2. Circuit Description
TMC
Internal TMC (Trunk 8 Channel)
BGM 1 Port
008 Base B’d has one optional background music input 1 port. It can be selected between
Internal and External. In case of Internal, used to melody IC.
PAGE 1 Port
The port is for external paging. PCM data (from highway 0 Rx) is switched to analog signal and
the analog signal is fed to transformer (T2).
DRY Contact
It is dry contact relay 1 port. It makes use of EXTACT signal that received from engine to
operate Relay.
Control Signal for 2 or 4 SLI
It is generated at TMC port (in engine) to control 2 or 4 SLI card.
MISC Interface
It includes Dry contact, external MOH, RS232C interface, 4 Channel DTMF receiver, 4 Channel
Automatic Attendant (AA), Caller ID, Alarm Sensing.
2-12
Page 13
Chapter 2. Circuit Description
Expand B’d Interface
64pin connector is provided to connect the signals to expand the B’ds. Refer to the circuit
diagram for the pin assignment.
DPLL (Digital Phase Locked Loops)
°‹Produced 4.096MHz for S0T0
°‹2 kinds of DPLL support for PRI (Primary Rate Interface) - for testing
°‹Use Clock Burst Correction Scheme with using Master Clock Divide
Address Bus
$ 700,001H
$ 700,011H
Data Bus (D7 - D0)
Micro-processor Write
D-PLL Control Register Write
D-PLL Test Register Write
D-PLL Register Map
Micro-processor Read
Readable
Readable
2-13
Page 14
Chapter 2. Circuit Description
2-2 MEM Card
Capacity
Basic ROM
Option ROM
Basic RAM
Option RAM
1M Bytes
Address Scope : $000,000H$-OFF, FFFH
1M Bytes
Address Scope : $100,000H-$1FF, FFFH
256K Bytes Basic
Address Scope : $A00,000H-$A3F, FFFH
256K Byte
Address Scope : $B00,000H-$B3F, FFFH
27C4001 °ø 2
27C4001 °ø 2
681000 °ø 2
681000 °ø 2
2-2-1 Circuit Description
Real Time Clock (RTC)
RTC72423 (U12) which has small access time is used for RTC (Real Time Clock). It is
equipped in the MEM Card for battery back up function. CPU is connected at data bus D8 - D11
and A1 - A4 is used.
Memory Backup
60mAH battery equipped in the MEM Card is used for memory backup by 4 RAMs and RTC IC
in case of power failure for a maximum of one week. To erase the RAM and the RTC data, set
the backup switch to OFF and turn the power OFF. Software reset also available.
Watch Dog
It monitors the address within the specified range and reset the system if it cannot access the
address within a specified time. If the program does not work properly, the watch dog address
can not be accessed within a specified time, and Watch dog circuit resets CPU. Watchdog is
inserted to ST*of Micromonitor Chip DS1232S (DALLAS).
2-14
Page 15
5V
Chapter 2. Circuit Description
10 mSec
More than 20nsec when DS1232 is used.
TD
TIMEOUT (mSec)
GND
FLOAT
Vcc
Min
62.5
250
400
Watchdog timeouts of DS1232
Typical
150
600
1200
Max
250
1000
2000
When watchdog works DS1232 guratees the reset time of minimum 250 ms, which result in
CPU reset time to be of 100ms. Output reset time is adjustable by controlling TP pin of
DS1232.
Power On Reset
DS1232S resets the CPU when power turns ON. It stabilizes the system operation. DS1232
accepts a minimum of 250ms as reset time and the reset voltage to be 4.5V by adjusting TOL
pin.
Voltage
TOL Pin 3
VCC
GND
Min
– 5V
– 5V
Typical
4.5V
4.75V
Max
+ 5V
+ 5V
DS1232S Minimum Reset voltage
Manual Reset
Manual Reset can be operated by turn on TACT SWITCH being connected PBRST*pin.
2-15
Page 16
Chapter 2. Circuit Description
LED Indication
One LED which shows the system status according to the system programming is equipped in
the mem card.
LED Off : Abnormal power
LED On : Power is normal but system does not work properly
LED Flicker : Both power and system are normal. (Normal system means memory read/write
and decoding logic work properly)
2-16
Page 17
2-3 3-TRK Card
2-3-1 Block Diagram
Chapter 2. Circuit Description
2-3-2 Circuit Description
Loop Trunk Interface 3 Port
Sending and Receiving voice frequency range (300 ~ 3400Hz) between keyphone system and
trunk line are achived with DC Current Bypass Circuit, Matching Transformer, Balancing
Network, Hybrid Circuit, PCM Codec, Channel Assign Timing Control, Digital Gain Control
circuit. DC By-pass circuit is needed for using small transformer with DC bypass before T1, T2,
T3 transformer. Off-hook (H.O.S) & Ring Signal Detecting Circuit are in this internal circuit.
Loop Start Trunk is applied to system which has complex resistive impedance.
2-17
Page 18
Chapter 2. Circuit Description
Surge and Over Voltage Protection Circuit
FUSE TYPE SURGE - Absorber for first protection circuit, T.V.S (1.5KE15A) for second
protection circuit and ZENER DIODE for third protection circuit are provided to protect the
system from surge and over voltage damage at 3 trunk lines.
P.R.S (Hook On/Off Sensing) Circuit
It is signal polarity reverse detecting circuit of C.O line interface. Be careful TIP - RING LEAD’s
polarity when installing system at the site.
Ring incoming signal detection circuit
Ring Incoming signal from C.O is available when TRK interface is hook-on status, regardless of
trunk type. DC voltage of Ring signal is cut by poly - capacity (0.82µF/250V) and ring signal
above reference value (relation with Zener diode (5.1V)) is passed.
Ring signal generates Ring Detection Signal when above setting voltage (1.2V) is flowed
through serial connected Diode (2EA) and parallel connected photo coupler input. It switched
high if righ signal is applied.
DC Current Bypass Circuit
This circuit seizures DC LOOP and passes AC signal to the next step. It generates output of
H.O.S detection to the system with photo coupler.
Caller ID Relay
It makes PATH (by RL4, RL5, RL6) to Detect Caller ID in 1200 bps FSK signal received
between ring and ring during ON HOOK state. DSP for Caller ID is in the MISC card.
Balance Network
It is used for 2W/4W interface. Tx uses OP AMP(3404) and Rx uses OP AMP in the codec.
2-4 6 TRK Card
It has 6 loop start trunk port and 2 PFT port.
2-18
Page 19
2-5 8 SLI Card
2-5-1 Block Diagram
Chapter 2. Circuit Description
SURGE
PROTECTION
CC°ØT
RING
GENERATION
CC°ØT
FEEDING
CC°ØT
MATCHING
TRANS.
SBS 9401
¶UMODE CONTROL
¶UTIME SLOT ASSIGNMENT
¶UUART(4PORTS)
¶UDIAL PULSE GEN.(4PORTS)
¶UI/O DETECT
(HOS/LOOP DISCONNECT)
GAIN
BALANCE
CC°ØT
A-LAW
CODEC
(TP3057)
TSAC
2-5-2 Circuit Description
Voice Path
The voice signal from subscriber is fed to primary T1 with AC plus DC forms. The output signal
from T1 is AC signal. Balance logic with using OP - AMP (MC34072D) transmits and receives
+2.0dBm to the Tx port of CODEC, –7.0 dBm down to the subscriber from Rx port, then is
supplied to HIGHWAY 0 after converts signal as PCM Code by CODEC.
CODEC receives 2.048MHz clock frequency, and loads 8KHz Delayed PCM DATA to DX & DR
by sampling for each 8KHz. A - LOW is used by Pull UP BCLKR, 7th Pin of codec.
2-19
Page 20
Chapter 2. Circuit Description
SLI Interface
– DC Loop Disconnection
It is composed with Connection and Disconnection DC Loop. If LD Signal pin (output of ASIC
IC (SBS9401)) is LOW, DC(–48) is supplied to the LINE and restricted current flowing to the
LOOP by connecting 300Ohm. If LD Signal is HIGH, DC loop is cut.
– Loop & Pulse Detection
LOOP DETECTION detects hook on/off state of single line telephone. When hook - off is
occured, DC loop is enabled. TR (Q33) EMITTER port is lower than GND LEVEL, so TR
(Q41) is off and output is HIGN. Normal state output is LOW.
When subscriber uses DIAL PULSE, detects DIGIT state as the same above procedure.
– Ring Trip
If the subscriber lift handset when the telephone is ringing, Relay are released to finish the
ring signal transmission. When the subscriber hook - off during ringing, Collector of TR (Q41)
outputs HIGH.
– Ring Generator Circuit
Ring (80Vrms/40mA, 20/25Hz) is transmitted to the line with driving RELAY (TQ - 5V)
controlled by RCO - 1 received from BASE008 B’D when to generate Ring. Ringer circuit is
composed of pulse for small and simple.
– Balance Network
It is used for 2W/4W SLC interface. In this circuit, Hybrid IC (KP0070SA) equipped with 4 port
OP - AMP uses at each Tx port and OP AMP in the codec uses at Rx port.
2-20
Page 21
2-6 2-SLI Card
It is used to same card with COMPACT.
2-6-1 Block Diagram
Chapter 2. Circuit Description
TIP
RING
Loop
relay
HYBIC
KP-SLC05
Matching
trans
(5692)
HOS
Balance
Codec
(TP3057)
PCM Data
to 008
BASE B°Ød
2-6-2 Circuit Description
SLI Voice Interface
The signal from the regular telephone is fed to primary T1 (5692) through the pins 2,3,7, and 6
of K1, and C103, C104. The output signal from T1 is fed to VFXI (pin15) of U102 through the
balance circuit HYB4, then is supplied to Highway 0 in a format of PCM data.
DC Feeding
–55V DC, the power to operate a single line telephone, comes out from pin 2 and 4, and is
supplied to the regular telephone.
Hook Detection & Dial Pulse Detection
HYB1 is used to detect hook on/off signal or pulse dial on a signal line telephone. If the phone
is off - hook of during the make time of pulse, HYB1 pin5 becomes low, and if the phone is on -
hook of during the break time of pulse, HYB1 pin5 becomes high. The condition of pin 5
transfers to the pin 23 of U20 in the 008 Base B’d.
2-21
Page 22
Chapter 2. Circuit Description
Ring Trip
If the station user lift the handset when the phone is ringing, Relay K1 and K2 are released to
finish the ring signal transmission. The pin 5 of HYB1 and 2 become high. TMC (U20) can
detect the signal status.
2-7 8 DLI Card
It is option card required 8 digital extension lines. U1 (STI9511) controls 8 digital extension
lines. The card contains the followings.
°‹DMC Interface
°‹DASL Interface
°‹DGP Interface
Block Diagrm
ADDR & DATA
CLK
4MHz
FSX
/RST
QDMC
(STI 9511)
DLI
8PORT
QDASL
TP-3404
MATCH
TRANS
DLT-1
HWx
HWr
DGP
SIM
DPIM
AOM
2-22
Page 23
Chapter 2. Circuit Description
2-8 MISC Card
It has 2 kinds of card (MISC1, MISC2).
MISC1 Card performs many operation. – DTMF RECEIVER (4CH), RS232C PORT (2PORTS),
MODEM (OPTION).
MISC2 Card performs menu operation. – DTMF RECEIVER (4CH), RS232C PORT (2PORTS),
AA, MODEM (OPTION).
2-8-1 Block Diagam
MAIN BUS
ADDRESS BUS
DATA BUS
STC9604
NEW ENGINE
(FOR AA)
– BIDIRECTIONAL BUFFER
– 4 CH. DTMFR
LOCAL BUS
27C512 (64Kbyte EPROM)
PROGRAM MEMORY
27C4001(512Kbyte EPROM)
MEMORY FOR FIXED MESSAGE
CONTROL & A-D BUS
HIGHWAY
CONTROL & A-D BUS
HIGHWAY
CONTROL & A-D BUS
MC68EC000
PROCESSOR FOR AA
8-BIT MODE
STL7065
ENGINE
DTMFR 4 CHANNEL &
R2MFC SENSOR
MC68681
2 CH. UART
STL7053 (TMC)
TISAC & PARALLEL I/O
PORT(RELAY) CONTROL
BATTERY
SERIAL D.
TISAC
681000*8EA (1Mbyte SRAM)
MEMORY FOR VARIABLE MESSAGE
NiCd BATTERY FOR
MESSAGE RESTORING
STB9404
NEW ASIC
CALLER ID 8 CH. OR
R2MFC REC. 4 CH.
MC145407 *2EA
2 PORT RS232C SUPPORT
TP3057-A (OR TP3054-U)
EXT.PAG. & B.G.M SUPPORT
– ALARM SENSING 1 CH.
– DRY CONTACT 3 PORTS.
2-23
Page 24
Chapter 2. Circuit Description
2-8-2 Circuit Description
Dry contact
It is used to signal’s ON/OFF for EXT.PAGING, BGM SOURCE or other purpose’s ON/OFF.
The 3 ports control ON/OFF and Mute Port (TMC) controls the 3 port.
ZONE 1 = MUTE 0 (WRITE 800000 D6)
ZONE 2 = MUTE 1 (WRITE 800100 D6)
ZONE 3 = MUTE 2 (WRITE 800200 D6)
DATA ‘0’ = NORMAL OPEN
DATA ‘1’ = RELAY ON
External MOH
There are External/Internal MOH Interface in the 008 base board. External MOH in the MISC
board is prepared for 1 more port needed. External music source is supplied to the pin 6 and 38
of P3 connector in the MISC B’d through the pins 6 and 38 of P4 in the 008 Base B’d. Input
impedance is matched to 600Ohms.
This circuit is divided by transformer, and output impedance is 600Ohm. Adjust gain with using
OP - AMP and MOH LEVEL is –17dBm. The signal goes to the HWR0 though Codec, then
switched at the T-switch of the 008 base board.
RS232C Interface
It is composed with RS232C DRIVER 2 PORT to communicate serial data for SMDR & PC
MMC. MC68681 is used for UART. BAUD RATE can be changed from 75bps to 19.2kbps by
S/W programming. Interface that reading DATA at the CPU is interrupt mode, and /WAIT signal
is inserted to the CPU (in the 008base board) by DTARK SIGNAL that generated when control
command is written. Interrupt level is main process’s level 5, same as DLI SIO Rx INT. S/W can
distinguish type whether SIO Rx or DUART.
(ref. MOTOROLA DATA BOOK for MC68682 SPEC.)
MC68681 is used as RS232 LINE DRIVER/RECEIVER IC, satisfied with EIA - 232D & CCITT
V.28. Power of MC68681 uses +5V to the RS232C connection part, and 5V/GND to the logic
circuit. Internal Logic is made up of Inverter. If output data of MC68681 is low, outputs +3.9V
(3.5 min, RL = 3KOhm), but if high, output –4.3V (–4.0V min, RL 3kOhm) to the connection
port.
2-24
Page 25
Chapter 2. Circuit Description
When data is inserted from external device, 1.80V (1.35V min) is operated as Input Trun On
Voltage (low input to the MC68681) and 1.0V (1.25V max) is operated as Turn Off Voltage (high
input to the MC68681).
Both of 2 ports (RS232C connection) is 9 pin connector (DB9).
PIN NO.
FUNCTION
1 2 3 4 5 6 7 8 9
DCD RXD TXD DTR GND (N.C) RTS CTS (N.C)
Serial Interface Port Pin Description
4 Channel DTMF Receiver
Engine (STL7065) is used to 4 channel DTMF receiver, and used to only DSP (for DTMF). See
the 008 base board circuit description for the DTMF receiver.
4 Channel Automatic Attendant (A.A)
The circuit performs auto attendant that provides automatic answering of incoming calls,
presentation of choices to the caller, and connection to extensions based on those choices.
– A.A Feature
°‹A Number of Channel : 4 Channel
°‹AA Recording time : (120sec Recording Regeneration +60sec Regeneration)/Channel
°‹A Number of AA DTMF Receiver : 4 Channel
°‹Processor : 68EC000 FN16
°‹AA Memory Size : SRAM 1M ®MVoice data and program
EPROM 512K ®MVoice data
EPROM 64K ®MProgram memory
°‹IPC with main memory : using 2 latch of 1 byte in the STC9604
°‹RECORDING DATA BACKUP : Using 3.6V NiCd battery
°‹It is possible to record with BGM port in the 008Base board and hanset
2-25
Page 26
Chapter 2. Circuit Description
Internal Address Map
ADDRESS SIG NAME READ WRITE REMARK
00XXXX
ROEN1B
27C512 CEB, 64KB Program ROM
08XXXX
08XXXX
10XXXX
20XXXX
28XXXX 28XXXX
0AXXXX
0CXXXX
0EXXXX
10XXXX
12XXXX
14XXXX
16XXXX
18XXXX
2A0XXX
2A4XXX
2A8XXX
2ACXXX
RE0B
RE1B
RE2B
RE3B
RE4B
RE5B
RE6B
RE7B
ROEN2B
DSPCEB
SRENB
WEB0
WEB1
WEB2
WEB3
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
KM681000 CS1B
27C512 CEB, 64KB VM ∞Ì¡§Data
AAMODE DTMF RCV Control1
HWP 8Bit RD ENB £ ≠
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
128KB
SRAM
Working£´
AA
registration
128KB
SRAM
AA fixed
Data
2CXXXX
2EXXXX
30XXXX
38XXXX
2B0XXX
2B4XXX
2B8XXX
2BCXXX
2E0XXX
2E4XXX
2E8XXX
2F4XXX
2F8XXX
2FCXXX
WEB4
WEB5
WEB6
WEB7
AASWRSTB
AIPCWRB
AIPCRDB
AACHB
AIPCSTRDB
AIPCSTSETB
INTSETB
DSPEN1B
DSPEN2B
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
£ ≠ HWX P2S LOADB
£ ≠ AASWRSTB
£ ≠ AA IPC WR ENB
£ ≠ £ ≠
CDENB of TMC
AA IPC STATUS
RD ENB
£ ≠
£ ≠
DSPMODE STL 7065C Control
DSPMODE STL 7065C Control
AA IPC STATUS
WRB
Stimulate AA INT
Signal
£ ≠
CPM READ
This Status
2-26
Page 27
Chapter 2. Circuit Description
CPM CPU to AA ADDRESS MAP
ADDRESS SIG NAME READ WRITE REMARK
0F2000
CIPCRDB
CPM IPC RD ENB £ ≠
F2080
F2100
F2180
CIPCWRB
CDIDB
SVALIDB
£ ≠ CPM IPC WR ENB
AA Card ID RDB £ ≠
CPM IPC STATUS £ ≠
RD ENB
CPM CPU
Read The
ID of AA B°Ø
d when this
signal is low
Caller ID (USA only)
The circuit offers function that detecting caller ID with C.O signal and transmitting it to the main
processor with data.
PCM highway is enable to 8 port to analysis Caller ID’s data, Generates Time Slot matched
with corresponding channel in the internal TISAC, then stores it in the PCM DATA STORE
REGISTER and at the same time, informs it to the CPU by interruptting the Int1 port of DSP
Core. CPU resets DSP and then downloading. Because program that operates DSP core in the
CPU must be stored at internal 2K WORD RAM. If it is done completely, turned download
enable signal to LOW and then operate DSP in succession.
DSP prepares to receive caller ID data with port enable signal that CPU writes, and read each
port data that is in the PCM DATA STORE REGISTER when 8KHz interrupt occured. Analysis
that is ‘1’ or ‘0’ and if DSP writes the results unconditionally at each port’s double buffer RAM,
CPU polling each 20mSec whether occurs READY or not, if occured READY, read 8 byte data
to the BURST immediately.
Error flag is occured when CPU didn’t access during 8.33m*16=129.28mSec and Caller ID is
invalid. And there are flags of sync, mark data, DSP receive end for each data in the DSP
program.
ALARM SENSING
It is possible to detect ON/OFF with TMC PORT under the condition that they are connected
between ON/OFF connection port for external sensing and system through MDF.
METGNE 0 = ‘1’ : DETECT
= ‘0’ : IDLE
2-27
Page 28
Chapter 2. Circuit Description
2-9 S0T0 Board
– Support 4 Port (Each port : 2B + D) ISDN Basic Rate Interface
– Possible to operate as TRK (TE mode) and Line interface (NT mode)
°‹Include 4 port
°‹Interface between PCM HIGHWAY in the key - system and each channel of ISDN
°‹Tx/Rx signal and control information between EURO - ISDN S INTERFACE and KEY-
SYSTEM
°‹Supply network SYNC signal to the KEY-SYSTEMCLOCK GENERATION PART
°‹Support available space to store code and use data
2-9-1 Block Diagram
MAIN BUS
CONTROL &
8KHz,
ACTIVE
HIGHWAY
A-D BUS
LOCAL A-D
STL7066
- DUAL PORT RAM
- DECODING
- INTERRUPT
HANDLER
MC68EC000
BUS
PROCESSOR
16BIT MODE
CLOCK LOGIC
PEB2054 (EPIC)
CH. CHANGE &
IOM2 BUS CONTROL
PEB2075 (IDEC)
HDLC CONTROLLER
LOCAL
BUS
27C2001
(EPROM 256K byte)¶J2EA
PROGRAM MEMORY
681000
(SRAM 128 Kbyte)¶J2EA
DATA MEMORY
1.535MHzIOM-2 BUS
PEB2084
(QUAT-S)
LAYER 1CONT
-ROLLER FOR
4 PORTS
RELAY &
S-PORT
RELAY &
S-PORT
£ ≠55V
LM337H
LINEAR
REGULATOR
£ ≠55V to £ ≠42V
RELAY &
S-PORT
£ ≠42V
RELAY &
S-PORT
2-28
Page 29
2-9-2 Memory map
Chapter 2. Circuit Description
BASE£´0X1F,FFF~
BASE£´0X10,000
BASE£´0X1F,FFF~
BASE£´0X10,000
READ CARD IDENTIFICATION
D0/RESET
WRITE D1/LSA9
D7/LSA10
BASE£´0X0F,FFF DPRAM #4
READ
DPRAM #3
DPRAM #2
BASE£´0X00,000 DPRAM #1
[Table 1.] Memory map for keystem side
HEXADECIMAL ADDRESS MEMORY MAP
0X600,000£ ≠0X6FFF,FFF UNUSED
0X5E0,000£ ≠0X5FF,FFF SIO
0X5C0,000£ ≠0X5DF,FFF EPIC(2054)
0X5A0,000£ ≠0X5BF,FFF IDEC(2075)
0X580,000£ ≠0X59F,FFF DPRAM
0X560,000£ ≠0X57F,FFF UNUSED
RESET LATCH
0X540,000£ ≠0X55F,FFF D13-IDEC/EPIC RESET(L)
D12-QUATS RESET(L)
0X520,000£ ≠0X53F,FFF WATCHDOG
0X500,000£ ≠0X51F,FFF LED
0X420,000£ ≠0X4FF,FFF UNUSED
SIGNAL LATCH
D13 £ ≠CONFORM BIT(L)
0X400,000£ ≠0X41F,FFF D10 £ ≠WATCHDOG DISABLE(H)
D9 £ ≠ENABLE 8KHZ(H)
D8 £ ≠L1 ACTIVATE(H)
0X280,000£ ≠0X3FF,FFF UNSUED
0X240,000£ ≠0X27F,FFF SRAM(DATA MEMORY)
0X100,000£ ≠0X23F,FFF UNUSED
0X080,000£ ≠0X0FF,FFF ROM(EXPANDABLE)
0X000,000£ ≠0X07F,FFF ROM(CODE MEMORY)
[Table 2.] Memory for card side
2-29
Page 30
Chapter 2. Circuit Description
2-9-3 Circuit Description
Control Part
CPU (MC69EC000)
MC68EC000 used in this card is emphasized on cost. It is operated under 16 bit operation
mode and 16.384MHz clock speed. It can control the control BUS, but external processor can’t.
Reset Logic
DS1232S is used in reset logic. DS1232S displays input voltage and supply reset-pulse to the
input/output circuit that is related with CPU. It performs watchdog. When Falling Edge is not
generated during 60mSec, DS1232S generates reset - pulse. During initial feeding power time,
can’t watchdog with H/W method. After H/W initialation, D10 in the 0X400,000 address turned
to high is possible to watchdog. After in this time, Falling dege is occured, whenever access
0X52000 address. CPU reset and halt are composed of OPEN DRAIN output matched with
electric characteristic, and connected with CPU, BUFFER, and CONTROL ASIC.
TO I/O
DS1232S
(POWER MONITOR)
BUFFER(HC244)
CPU(MC68EC000)
CONTROL ASIC
(STL7066)
The reset logic for EURO-ISDN S interface trunk card
2-30
Page 31
Chapter 2. Circuit Description
Control ASIC (STL 7066) Interface
All the peripherals connected with external memory to Tx/Rx are used to CONTROL ASIC
7066. Basic function used in control ASIC is as follows.
– Address decoding for the generation of memory chip - select signals
– Address decoding for the generation of I/O chip-select signals
– Interrupt control and priority encoding for CPU
– Communication between signalling processor and internal processor at the key - system
using internal DPRAM
MODE CHARACTERISTIC : IMODE of control ASIC is pulled high. So, internally, SIO can’t
be used and SIO pin is used to decord signal.
DPRAM (dual port ram) : DPRAM IS MEMORY ALLOCATED FOR INTERNAL
PROCESSOR COMMUNICATION.
It is 1024byte size for 512 byte Tx buffer and 512 byte Rx buffer.
dual port RAM
write
read
card side
DPRAM Structure for EURO-ISDN S interface trunk card
transmitter
(521byte)
receiver
(512byte)
read
write
key-system side
2-31
Page 32
Chapter 2. Circuit Description
INTERRUPT : LEVEL 7 … NON-MASKABLE INTERRUPT USED IN DEBUGGER
LEVEL 6 … IDEC INTERRUPT FOR D CHANNEL MESSAGE AND CIC
(COMMAND AND INDICATION) HANDLER
LEVEL 5 … EPICS INTERRUPT FOR THE CONTROL OF MONITER
CHANNEL BETWEEN EPIC AND QURT-S
LEVEL 4 … 1mSec INTERVAL TIMMER INTERRUPT FOR PERIORITY TASK
GENERATION
LEVEL 3 … INTERRUPT FOR PROHIBITED MEMORY-ACCESS
LEVEL 2 … SIO INTERRUPT
INTERNAL LATCH : Internal latch allocated at 0x540,000 address is used to Reset Latch -
Signal
ADDRESS DECODING : Chip select signal which decoded in the control ASIC transmit to the
memory and input/output device.
Control–signal latch for I/O interface
Control signal is needed to communicate between input/output device and CPU.
– D8 (layer 1 activated) : This bit indicates layer 1 status whether it is available or not.
– D9 (enable 8KHz) : It is start bit of 8KHz generation logic to sync with received signal
from line.
– D10 (conform bit) : If this bit is high, card is Power-On-Reset status. But if this bit is low,
1KHz generated in the key-system is supplied continuously, and
periodic port access is not necessary.
– D13 (confirm bit) : This bit is used for stopping offerred frame sync.
BRI (Basic Rate Interface) part
4S0T0 Card has 4 ports-BRI, and BRI is composed with 2 B-CH (64kBPS voiceband), call
channel, and 16kBPS D-Ch for signalling.
EPIC-S (PEB 2054, Extended PCM interface controller-small)
EPIC is switching element for control the path 4¶J24channel.
To control path, EPIC-S switchs serial interface between PCM highway and IOM2.
Capacity of EPIC-S (in the 4S0T0 card) is as follows.
– Interface between PCM HIGHWAY OF KEY-SYSTEM AND IOM2 (SIEMENS ELEMENT)
2-32
Page 33
Chapter 2. Circuit Description
– B-channel interface between interfaces of 4 S-interface network lines.
– Monitor channel control for the access of QUAT-S.
– For interface of key-system using Tri-state control, receive selected 1/2 of PCM HIGHWAY.
(FIRST 16 CHANNEL AND LAST 16 CHANNELS)
IDEC (PEB2075. ISDN D channel exchange contaoller)
IDEC has 4 channel HDLC FIFO for Tx/Rx layer2 information through D-channel. This element
controls call control and signal information of D-channel.
– D-channel FIFO handling for layer2 function of four port (each channel has 1 D-channel)
– Command and indication handling for the state control and monitoring of layer1, physical
condition in QUAT-S.
QUAT-S (PEB2084, Quadratic tranceivers for S/T interface)
QUAT-S is phsical Rx/Tx device for 4 channel, and it satisfies standard I.430 of layer 1 which is
standard access unit of ISDN.
– 4¶J2B+D subscriber Rx/Tx interface capacity
– IOM2 INTERFACE
– Support JTAG (Join Test Action Group) boundary scan test
– CMOS element of low comsumtion power
Operating of BRI interface element
Interface is designed on the basis of IOM2 organized with special disign element (EPIC, IDEC,
QUAT-S) for multiple port. Physical interface (layer1) about I.430 standard Framing (2B+D) is
formed by PEB2084 (QUAT-S), interface about LAPD PACKETIZING is formed by PEB2075
(IDEC;ISDN D-CH exchage controller). Data path & switching for voice channel is formed by
PEB2045 (EPIC-S;extended PCM interface controller small). Connection among QUAT-S, EPIC
and IDEC is described at the Block Diagram. (2B+1D) Channel about each port of QUAT-S is
possible to communicate from S Interface to IOM2 Serial interface. QUAT-S has various 4 BRI
interface at the 1 IOM2 serial communication interface. IOM2 serial interface is designed by
SIEMENS, and its speed is fixed as 2.048MHz in the EURO-ISDN S INTERFACE TRUNK
CARD. IOM2 interface has 32 channel of 64kBPS. Each port has 4 CH among 32 CH in the
IOM2 HIGHWAY (IDP0, IDP1), 4 CH are composed with 2 B-CH, 1 D and 1
command/indication handling, MONITOR CHANNEL PROTO among QUAT-S, IDEC, EPIC.
Consequentely, 1 card uses 16 channel of each 64kBPS. Each D-CH from IOM2 communicates
2-33
Page 34
Chapter 2. Circuit Description
with IDEC that has 4 independant FIFO with layer2 operation. Command and state of physical
layer1 is indicated by IDEC C/I(command and indication). C/I channel reports interrupt level
when state is changed at physical line.
Each B1, B2 channel is transmited for switching B-ch between QUAT-S and EPIC-S from QUAT
to EPIC-S throgh IOM2 serial interface. EPIC-S switchs each B-channel between IOM2 and
PCM HIGHWAY. IOM2 is serial interface to the S-interface line, and Highway is interface for
key-system B-channel. Connection memory and data memory is for assigning PCM highway
and each time band. Monitor channel is Control and Response Channel for EPIC-S can control
bidirectional control register(QUAT-S CONTROL REGISTER).
IOM2 INTERFACE
(B)IOM2 SIGNAL DEFINITION
FSC
IDO
IDI
OUAT-S
(PEB2084)
2B+1D(A)HARDWARE CONNECTION
PORT1 PORT2 PORT3 PORT4...UNUSED... PORT8
B1 CH B2 CH
S INTERFACE TRANSFORMER
S INTERFACE TRANSFORMER
S INTERFACE TRANSFORMER
S INTERFACE TRANSFORMER
MONITOR
CHANNEL
FCS : 8KHz
IDI : 2.048MHz from IDEC/EPIC-S to QUAT-S
IDO : 2.048MHz from QUAT-S to IDEC/EPIC-S
DCL : 4.096MHz clock signal
D1,
D2
C/I
MR,
MX
S-INTERFACE
Interface between IOM2 and fore port of S interface IDEC/EPIC
2-34
Page 35
Chapter 2. Circuit Description
Key-system interface part
Key-system interface part has 2 important capacity. One is DPRAM. DPRAM performs internal
process interface between CPU of card and SP(signal processor) of key-system. Card
transmits data about call control message and card array with D-channel. Key-system transmits
data about call control message and card array, too. This message controls BRI card to use its
own digital signal.
Second capacity is B channel interface and switching between IOM2 B CHANNEL and
HIGHWAY B CANNEL.
These capacity are performed at EPIC-S.
System clock interface
BRI card is BRI trunk card installed at LT-T mode. So, Clock from BRI line is used as standard
clock of system.
2-35
Page 36
Chapter 2. Circuit Description
2-10 PRI Card
– CPU AND MEMORY
– KEYPHONE SYSTEM INTERFACE
– PCM DATA HIGHWAY INTERFACE
– PRI NETWORK INTERFACE
2-10-1 Block Diagram
2-36
Page 37
2-10-2 Memory Map
Chapter 2. Circuit Description
RESOURCE
EPROM
RAM
MAIN ENGINE
IPC MEMORY
LED PORT
SERIAL PORT
ACCESS TYPE
R
R/W
R/W
R/W
W
R/W
ADDRESS RANGE
0000000 – 007FFFF
0080000 – 08007FF
0800000 – 08007FF
0580000 – 05807FF
0500000
05E0000
SIZE
512KB
256KB
–
1KB
–
–
BUS WIDTH
16BIT
16BIT
8BIT*
8BIT*
8BIT*
8BIT*
CPU AND MEMORY
CPU(MOTOROLA 68302, 16BIT) : Motorola 68302 has 68000 capacity and Communication
between Processor capacity.
Reset Logic
DS1232s(the power monitor and the reset circuit) is used as Reset logic. DS1232s indicates
input voltage level and 1KHz clock input, and offers Reset Pulse to the CPU and I/O. If 1KHz
clock input is not inserted during 600msec, DS1232s resets system automatically. The other
source of reset is CDRST and SRST generated from keyphone system.
2-10-3 Keyphone system interface
Control ASIC(STL7066) Interface
Refer to STL7066 manual for detailed explanation. In this document, Needing usage will be
described.
– STL7066 has capacity as followings.
a. Chip select generation for serial port and LED access.
b. Interrupt control and priority encoding.
c. 1024 byte dual port memory resource for the CPU and the signal processor in K/P system
d. CPU cycle termination
2-37
Page 38
Chapter 2. Circuit Description
– DPRAM(dual port memory)
The DPRAM is very sensitive memory, it is used to communicate between processor.
DPRAM is divided by 2, one is used as received buffer, the other is used to transmitted buffer.
Address decoding
CPU needs interface with SRAM, EPROM, STL7066, STL7065 and serial port. Selection signal
between SRAM and EPROM CHIP is generated from 68302. Decoding of STL7066, 7065 is
achived at the internal ASIC, and serial port chip selection signal is generated at the STL7066.
Interrupt
4 kinds of interrupt are available. 3 kinds of interrupt is coded in the STL7066 ASIC CHIP, and
decided priority. The other one is generated by the internal factor of 68302.
Interrupt source priority is as follows.
1)LEVEL7 : NMI, USED IN VME DEBUGGER
2)LEVEL4 : INTERNAL HDLC CONTROLLER
3)LEVEL3 : 1mSEC Interval Timer Interrupt for Periodic Operation.
4)LEVEL1 : SIO(SERIAL IO) INTERRUPT
2-10-4 PCM Data highway interface
PCM Highway is composed of PCM TRANSMIT DATA(DSI), PCM RECEIVE DATA(DSO),
SC2B, SC4B, SFOB. STL7065 is used as Time Switch.
2-38
Page 39
Chapter 2. Circuit Description
2-10-5 PRI Network Interface
PRI NETWORK INTERFACE is composed of MT89790B, Tx/Rx Converter and
MH89791(CEPT PCM 30 TRANSMITTER EQUALIZER). MH89790B support interface between
2.048kBPS DIGITAL TRUNK and MITEL’S SERIAL TELECOM BUS(ST-BUS).
ST-BUS is composed of three control line, two transmit and rceive data line, frame sync, 2MHz
and 8MHz clock.
CSTI0, CSTI1, CST0 is control line. CSTI0, CSTI1 is input of chip received from time switch
STL7065. CST0 is input from CHIP to STL7065.
Rx/Tx PCM data is composed of 30 B-Channel, 1 D-Channel and control channel. Each
channel is 8 bit and 64kBPS. Time slot 0 is control channel and time slot 16 is D-channel. PCM
transmition line from keyphone system is connected to the TIME SWITCH. D-channel is
inserted to the TIME SLOT 0 by 68302.
Impedance of receive line is made to 75Ω or 120Ω by using jumper JP14.
2-39
Page 40
Chapter 2. Circuit Description
2-11 PLL
2-11-1 General Description
PLL B’d is composed of circuit that is for locking 8KHz sync signal generated at the BRI or PRI
B’d used, and generates 4M clock and FOI for being used as reference clock to realize Multislot ISDN B’d of DCS COMPACT II & COMPACT II PLUS System.
2-11-2 Block Diagram
4MHz GENE
8KHz SELECT
LOGIC
4MHz
8MHz
VCXO OXC.
/FOI GENE
APLL LOGIC
/FOI
£´12V
£ ≠12V
4MHz, /FOI
SELECT LOGIC
£´/£ ≠12V GENE
04MHz
/OFOI
E1/T1 4MHz
E1/T1 /FOI
£´5V
8KHz
ACT
8KHz
DEVIDE
LOGIC
008
BASE
16.384 MHz
2-40
Page 41
Chapter 2. Circuit Description
2-11-3 Circuit Description
APLL(Analog phase locking logic
APLL part receives devided 2kHz from 8kHz select logic Part, 8kHz select logic part selects
that, 8kHz comes from ISDN (BRI, PRI) card equipped in each slot of 008 Base B’d, and
devided 2kHz from 8.192MHz VCXO Oscillator. It is used to supply to the CA3410 and the
output of CA3410 is inserted to the 8.91MHz VCXO Oscillator as reference value to oscillate. It
is possible to supply 4MHz to the whole system by dividing oscillation frequency with 2, and
used as sync clock of whole system.
8KHz Select logic part
In the COMPACTII and the COMPACT II(PLUS)system, BRI B’d at the universal slot, E1 and
PRI at the 4th expansion rack can be installed. The highest priority B’d clock is used to sync.
clock of the whole system. 74HC148 is used to priority encoder.
Priority is that PRI or E1/T1 in the 4th expansion slot is highest and from left side in the
universal slot is high.
4MHz, /FOI select logic part
When digital trunk card(E1) is installed in expansion rack 4th slot, 4MHz and /FOI which are
supplied from digital trunk card(E1) is used as sync clock through whole system by setting T1
DET as high to the 74HC4053. When ISDN card is installed, T1 DET is changed to low, and
4MHz and /FOI is supplied to the engine.
4MHz, /FOI Generation
Generates 4MHz by dividing (by 2) output of 8.192MHz VCXO OSCILLATOR synchronized at
the reference ISDN card, and /FOI by dividing output of 8.192MHz VCXO OSCILLATOR
synchronized at the reference ISDN card and then supplys to 4MHz/FOI SELECT LOGIC.
2-41
Page 42
Chapter 2. Circuit Description
+/–12V Generation
+12V is made by +12 exclusive DC/DC converter(LT1108) with supplied +5V and -12V is made
by common DC/DC converter(MC34063), and then supply it to the CA3410. It is possible to
improve performance.
– – If New engine(STC9604) is used, BRI card uses internal DPLL in the engine, so it is
unnecessary to use a PLL option board. because of internal DPLL in the engine is not so good
in respect of accuracy. So, if PRI or BRi card is used, then PLL option board is needed.
2-12 Ringer B’d
Ringer B’d generates sine wave ring signal and provides it to single line telephone. It is
composed of Wein bridge oscillation part, and amplification.
2-13 SIM Module
2-13-1 General
SIM is the interface for digital line and data. One data terminal can be connected to one SIM.
2-13-2 Block Diagram
DLI Port
Digital Line Interface
Processor Memory
RS232C InterfaceRS232C
2-42
Page 43
2-13-3 Memory Map
0000
002F
0030
Chapter 2. Circuit Description
Vector table
Port 7 Pin function
7FFF
8000
DFFF
FF00
FF7F
FF90
FF9F
FFB0
FFFF
ROM ADDRESS
ROM ADDRESS
not-used
ITAL rigister ADDRESS
not-used
on-chip register field
not-used
on-chip resister field
: ROM : 32K byte
: ROM : 24K byte
P70 P71 P72 P73 P74 P75 P76 P77
RESERVED RESERVED RESERVED RESERVED /AS /WR /RD /WAIT
OUTPUT OUTPUT OUTPUT OUTPUT
P7DDR = 0 x FF
P7DD4 = 0 x FF
2-43
Page 44
Chapter 2. Circuit Description
2-13-4 Circuit Description
Serial Communication Interface
H8/325 has 2 serial communcation Interface module. SCI is used to transmit and receive Dchannel signalling data between processor and DASL. It contains the following:
°‹Communication mode : Asynchronous mode
°‹Data length : 8bits
°‹Parity Even
°‹SCI Input / Output pins
°‹Serial clock SCK0=32k
°‹Serial Receive data RxD0=DASL DR
°‹Serial Transmit data TxD0=DASL DX
RAM
SIM uses external RAM while H8/325 uses 1kbyte RAM of internal on-chip memory.
°‹RAM size : 24kbyte RAM
°‹RAM enable bit (RAME)
To enable the external memory, on-chip RAM should be disabled and RAME bit should be set.
RAME
0 on-chip RAM is disabled
1 on-chip RAM is enabled
ROM
32kbyte internal ROM is used. To enable the internal ROM, assign the operating mode 2.
ITAC is installed in the data terminal and DASL. It converts the data from terminal to be proper
for ISDN protocol according to rate adaptation.
Mode MD1 MD0 on-chip ROM
2(expanded made) 1 0 Enabled
2-44
Page 45
Chapter 2. Circuit Description
2-14 DPIM Module
2-14-1 General
DPIM converts the digital signal from digital keyphone to analog signal to communicate with the
analog door phone. The allowable distance between DPIM and main system is of 400m. It is a
maximum of 200m between DPIM and the door phone, and a maximum of 600m between the
main system and door phone.
2-14-2 Block Diagram
2-14-3 Circuit Description
The DPIM(Digital Door pnone interface Module) uses the door box (which has been used for
the 816 analog keyphone and speaker). DPIM converts the digital signal form digital keyphone
system into the analog signal to send to the door box, and sends the analog signal from the
door to the digital keyphone system after converting to digital signal.
2-45
Page 46
Chapter 2. Circuit Description
Amplifier and Matching
The analog signal out from HFC and door box is amplified at TL084. TL084 is equipped with
100kOhm for input resistance.
T5692, the same one equipped in the door box, is used for matching transformer. 1kOhm(R14)
resistance guarantees the best transmission quality, and 100kOhm (R9, R10) is used for blance
resistance to prevent the speaker input signal from flowing to MIC input pin 19 HFC.
Door Locker Control
Door locker can be installed in DPIM. Relay switch is used to open the door, P10 (pin 48) in
MCU is the relay control port, Which is the key scan port in the digital phone. D6(IN4148) is to
get rid of the opposite electric power generated at the relay, and capacitor and resistor is used
to bypass the spark generated at relay contact.
Switch Detect
A push switch in the door is used by a visitor to call the one inside. DPIM detects whether the
switch is pushed or not with photo coupler, and supply the signal into the MCU port 46(pin 15)/
The MCU sends the data in a format of serial data to TP3406 U5 through D channel. The main
system transmits the signal to the preassigned port to connect the visitor to the user inside.
The switch detect signal consists of two lines because it is transmitted through the center tap of
matching transformer. Even though +5V is fed to the transformer, it does not damage the
transformer.
+12V Generator
+12V power with 5Vp.p (+5V reference) should be supplied to the OP amp(TL084). The step up
DC to DC converter (LT1109, U11) is used to generate +12V output from +5V input with simple
peripheral circuit.
2-46
Page 47
Chapter 2. Circuit Description
2-15 Digital Keyset
2-15-1 General
The digital phone exclusively designed for DCS COMPACT II(PLUS)system provides a lot of
serivices. A digital phone equipped with LCD shows up to 32 letters message through the 2 line
x 16 letters LCD display in front of the phone.
A digital phone without LCD performs the same function as the LCD phone except the LCDrelated features. And a basic phone basically performs the same function compared with the
LCD phone except no LCD display and less function keys.
The Add On Module (AOM) device has 48 DSS keys, LED display.
LEDs are attached in all the function keys and the programmable keys on the LCD phone. Dual
color LEDs (red & green) are used. However the AOM uses only a red LED.
The allowable maximum distance between the main system and the digital phone is 400m. 2
line twist pair is used and connected with modular jack.
It is selectable for desk top use or wall mount. Wall mount bracket is supplied.
Digital telephone is connected to the main system through the Digital line interface (DLI), and
sends or receives voice and data signal after AMI coding as 2B+D format.
u-Law or A-law voice signal is selectable according to the PCM coding mode, which is
adjustable by high feature codec software setting.
MCU uses masking type of H8/325 series made in Hitachi. MCU is preprogrammed several
functions.
2-47
Page 48
Chapter 2. Circuit Description
2-15-2 Block Diagram (Phone with LCD)
POWER
£´5V
TRANS
LCD
MODULE
DASL
(TP3406)
CONTROL
B-Channel
TIMING
LOGIC
D-CH
MCU
(H8/325)
2-15-3 Circuit Description
Microcontroller(MCU)
Hitachi H8/300 series are used for the MCU of the digital keyphone. It is 8-bit single chip
microcontroller with flat package type.
The MCU is composed of CPU core, ROM, RAM, Input/Output ports, 2 types timers, serial
communication interface, and clock generator. 6.144MHz clock is provided from high feature
codec (TC35320F). It is devided into two 3.072MHz clocks inside MCU.
2-48
Page 49
Specifications
Chapter 2. Circuit Description
Item
Clock Frequency
Instruction Execution Time
Supply voltage
Operating Temperature
Package Type
Memory
Interrupt
SIO
Operating Modes
* one time PROM
* masked ROM
ROM
RAM
External
UART
H8/325
3.072MHz
0.325 us
5V
–25 ~ 75˚C
FP-64A
32K byte
1K byte
4
2
Mode 1, 2, 3
HD6473258F
HD6433258F
Remark
6.144MHz External Clock
5V ±10˚C
0 ~ 50˚C
See “Pin Package”
H8/324:ROM 24K, RAM 1K bytes
H8/323:ROM 16K, 512K bytes
H8/322:ROM 28K, 256K bytes
2(IRQ0, IRQ1)
2
Mode 3: Single Chip Mode
64P QFP (FP-64A)
2-49
Page 50
Chapter 2. Circuit Description
Block Diagram of MCU Port
P41
P66
P42
P26
P27
P65
P62
P61
P30
P37
P40
(TXD1) P53
(RXD1) P54
(SCK) P55
P70
P71
P72
P73
P74
P75
P76
(FTCI) P60
(IRQ0) P64
P43
P44
P45
P47
(TXD0) P50
(RXD0) P51
(SCK) P52
P46
P77
P10
P17
KDB /CS
KDB /INT
KDB /SHD
KDB DECODING OUT(INITIAL INPUT PORT)
KDB DECODING OUT(INITIAL INPUT PORT
.
KATA BUS
.
KDB
KDB
KDB
32K
|
<HIGH FEATURE CODEC>
D7 H0
D0 H1
T
A0
C
A1 SPO
3
A2 MI
5
3
\CE CLKO
2
\RD WCK
0
\WR XCK
F
\RST TXD
\INT RXD
<DASL>
\INT BR
T
P
CI BX
3
CO BCLK
4
\CS FSA
0
CCLK FSC
6
DX MCLK
V
DR DCLK
COUNTER
HOOK ON/OFF(H : ON L :OFF)
LED MATRIX
(8 °l6=48EA)
EN LCD
R/\W MODULE
RS D0-D7
N.C
KEY MATRIX
HANDSET
MIC
TIMING
LOGIC
2.048M
(8 °l6=48EA)
BUF D0
.
(ID)
.
D3
AMP SPEAKER
SPEAKER AMP
/EN
P20
P25
P66
|
DRIVER
L : SED H : KEY COLUMN SELECT
2-50
Page 51
H8/32F Memory Map (Mode3)
The address map shown below is based on H8/325.
H°Ø0000
H°Ø002F
H°Ø0030
H°Ø7FFF
H°ØFB80
H°Ø7FFF
H°ØFB80
H°ØFF9F
H°ØFBB0
H°ØFFFF
.
.
.
.
.
.
.
.
.
.
.
.
ON-CHIP REGISTER FIELD
.
.
.
.
ON-CHIP REGISTER FIELD
<ADDRESS SPACE MAP>
Chapter 2. Circuit Description
VECTOR TABLE
ON-CHIP ROM
32K BYTES
ON-CHIP RAM
1K BYTES
Note : The memory map shows the address space. I/O address of each port is as follows. DDR
determines Input or Output. 0 is input, 1 is output. Input and output of each port are
determined by the default setting.
(Port I/O Address)
PORT NO. DDR ADDR.. DR ADDR..
PORT 1 FFB0 FFB2
PORT 2 FFB1 FFB3
PORT 3 FFB4 FFB6
PORT 4 FFB5 FFB7
PORT 5 FFB8 FFBA
PORT 6 FFB9 FFBB
PORT 7 FFBC FFBE
2-51
Page 52
Chapter 2. Circuit Description
Phone Types
No.
1
Reserved (Simple) 0
2
LCD Phone (without LCD) 0
3
Reserved (wide LCD phone) 0
4
AOM 0
5
Reserved 0
6
Reserved 0
7
DPIM (Door Phone Interface) 0
8
Reserved 0
9~16
Note : During the IC initial check, if the P40 input port is low, the system regards it as a basic
phone. If R4 is pull-up and the port is high, it is regarded as a output port and the system retry
to read ID. The value of the ID is provided above.
Types 3
1
D2 D1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
X X
2-15-4 Display
DMC16230 is used for LCD display and is controlled by u-processor H8/325F.
Specifications
Item
Supply voltage (V)
Operating Temperature
Power Current (mA)
Format
Display
Module Size (W x H x T)
Fonts
Min
0
0
–
16 Characters x 2 Line
5 x 7 Dots + Cursor
122 x 44 x 11 (mm)
Typical
–
–
0.5
Standard Value
Max.
0.7
+50˚C
2.0
Remark
Vcc ~ Vss + 5V
Vcc = +5V
2-52
Page 53
Chapter 2. Circuit Description
D7
.
H8/325
MCU
.
D0
En
R/\W
RS
2-15-5 Key & LED Matrix
Key matrix
When composing of the matrix, the column and row method is used to reduce the number of
port.
Key scan is the section to detect key input from the key matrix which composed with 8 row x 6
column.
If any 1 row among 8 rows is optionally selected and set to high and the rest set to output low, it
will be inverted through ULN2803. The column state can be read. The direction of U11/U12
buffer(74HC224) should be determined P63 port of MCU. When it reads key, it is H, and when it
writes LED, it is L.
74HC244 has eight buffers inside and it is possible to control each four buffers. The control
terminal is divided into two groups, 1G and 2G, 2G is used during key input and 1G is used
during LED output. The output terminal which is not used is in tri-state, and does not affect
each other. When common row is selected, it shows which key is pressed by reading the ports
P20-P25 of P10-P17 colume.
To prevent malfunction of keys, key scan counter is set to 2, with the key scan timing 18msec
minimum and 32msec maximum.
2-53
Page 54
Chapter 2. Circuit Description
Led Matrix
LED display control is operated with the dynamic mode, and is made up of 8 row and 6
columns. If any 1 row among 8 row is optionally selected and set to high and the rest set to
output low, it will be inverted through ULN2803. After writing column output. LED turns off for
2ms at interval of every 17ms. To turn on LED you want, you should decide the direction of
U11/U12 buffer.
The direction of the buffer U11/U12 is determined by P63 port of MCU and is low during LED
writing.
Digital Line Interface
The digital keyphone exclusively used for the keyphone system connects master and slave with
2line and uses 2B+D format to send/receive signals between master and slave. The AMI code
sent from master in the burst mode is divided into B-ch and D-ch through the interface. The
PCM data of B-ch is sent to codec and D-ch is used communicate with UART and MCU.
Connection Diagram between Master and Slave
2-54
Page 55
Specifications of TP3406
Item
Transmission
Interface
Transmission Speed
B Ch Speed
Signalling Speed
PLL Type
Line Coding
Coding Type
Loop Range
Line Impedance
Loop Resistance
Input Clock
Master/Slave
Pakage
Power
Power Feeding
Chapter 2. Circuit Description
2-15-6 High Feature Codec
High Feature
TC35320 is used for this feature. TC35320 is designed to be used with TC335321 (Data
transmission LSI). It features as follows
°‹Enable to control the levels of Tx, Rx, and side tone with software program
°‹Built-in speakerphone. Gain control with software program is allowed.
°‹Single Power Supply
°‹Beep tone source equipped. Adjustable level with software program.
°‹Equipped with DTMF sender
°‹Can generate various rings by mixing up with 5 frequencies.
°‹u-law or A-law is selectable.
°‹Allowable to interface with MPU by serial and parallel.
2-55
Page 56
Chapter 2. Circuit Description
TC35320 Block Diagram
DSP
PCM IN
PCM IN
DECODER
CODER
MICRO-PROCESSOR INTERFACE
Specifications
Item
Supply Voltage
Input Voltage
Clock Deviation
Operating Temperature
Storage Temperature
Soldering Temperature
Current Consumption
Digital Current Donsumption
Analog Current Consumption
TONE GEN
NETWORK
CONTROL
SPEAKER
PHONE
RX-LPF
TX-BPF
RX-UPF
Symbol
VDD
VID
∆fCLK
Ta
Tstg
Tsol
IDD
ISSD
ISSA
DA AMP
AD
DA
Condition
12.288MHz
VDD=5V
Rating
4.75 to 5.25
0 to VDD
–100 to +100
–10 to 70
–55 to 150
260
52 to 65
40
12
HANDSET
MIC
SPEAKER
Unit
V
PPM
˚C
mA
2-56
Page 57
2-15-7 PCM Interface
Block Diagram
Chapter 2. Circuit Description
TRANS
POWER
+5V
Module
Circuit Description
LCD
DASL
(TP3406)
Control
°ÿ
PCM I/F
Logic
MCU
(H8/325)
High
Feature
CODEC
(TP35320)
ControlD-Channel
Handset
Mic
Speaker
Key & LED
Matrix
The PCM In/Out clock must be 2.048MHz which is the master clock. Data is transmitted from
RISING of time BCLK at TP3406, and is received to FALLING time of XCK at TC35320F.
WCK inverted to BCLK and is fed to CK of D-F/F.
2-57
Page 58
Chapter 2. Circuit Description
PCM Interface Block Diagram
TP3403
BCLK
FSC
FSA
BX
BR
INVERT
CLK QA
QB
CLR QC
QD
74HC383
D Q
DF/F
CK
INVERT
AND OR
BCLK
TP35320
AND
WCK
TXD
RXD
2-15-8 Handset Microphone
Dynamic unit is used for a handset in a digital phone. OP amp LM359 is provided for TX
gain(50). The reference voltage of OP amp is 2.5V.
The output of TC35320F is used for Handset RX. Switching diode is added to the terminal of
TX and RX to protect high feature codec from ESD.
OP amp is also used for the microphone input, which amplifies the microphone output level.
2-15-9 Tone & Ring
Beep Tone
Beep tone is generated at TC35320F and is selected from 1KHz or 2KHz. Default is 1KHz.
Beep tone is out from handset or speaker. The levels are adjustable with software programming
2-58
Page 59
Chapter 2. Circuit Description
Ring Tone
Ring tone is selected from 5 kinds of single frequency source (300, 400, 600, 800, 1kHz). It is
generated by frequency modulation with 2 of them or amplitude modulation using software
control.
Ring level is adjustable when the unit rings or with the volume up/down keys.
AMP
External amp circuit activates the speaker output port in high feature codec. MC34119 is used
for the low power audio amplifier circuit and it has an advantage to gain stable output at the low
voltage. The speaker impedance is 32Ohm.
2-15-10 Power CC’T Part
The power used in a digital phone is single 5V which is converted from -55VDC through the DLI
port of main system. Bridge diode is used to stabilize power irrespective of the polarity.
The 5V is devided into +5A(analog +5) and +5D (digital +5V) to be used.
2-59
Page 60
Chapter 2. Circuit Description
2-16 KDB-D B’d
KDB(Keyset Daughter B’d) is an option b’d which uses 2B+1D, the basic form of digital phone
and is an additional interface device.
There are two kinds of board : KDB-DLI and KDB-SLI, KDB-DLI can be equipped into a digital
key phone, and KDB-SLI can be equipped into a single line telephone.
Two highway channel is allocated at the digital phone user’s port to use 2B+D.
If 2B is given to the digital phone, B1 and B2 can be used respectively within a prectetermined
distance because FSA, FSB, BX, BR, and BCLK can not used externally. KDB can solve the
problem by connecting digital phone to the modular jack on the KDB.
To operate, the interface ICshould be set to master mode and digital phone should be set to
slave mode.
The MCU in the digital phone controls digital phone and all interface ICs in the KDB, SIO-1 and
SIO-2 control D-channel. The interace IC has B1 and B2 channel which are controlled by FSA,
and FSB respectively.
To divide B1 and B2, 3-state buffer is used, which is controlled by FSA and FSB.
Short frame sync FSC is used and BCLK in the interface-2 IC is commonly used.
The interface-2 IC is to relay the PCM signal from B2 channel and retransmits the D-channel
data to interface-2 IC through SIO-2 from SIO-1.
To manage the system control, SIM (serial interface module) will be used.
2-60
Page 61
Connection Diagram between Digital phone and KBD
Chapter 2. Circuit Description
2-61
Page 62
Chapter 2. Circuit Description
2-17 KDB-S B’d
2-17-1 General
Regular telephone interface KDB-SLI performs 2B voice data conversion using code TP3057.
KDB-SLI supports 1 line regular telephone interface and composed of codec (D/A0, -5V power,
regular phone feeding (+56V), and ringer. DTMF detection is achieved by DSP in KSU engine.
Connection to digital phone is made with 2 line through DLI port. A regular phone can be
connected to the digital phone by using the optional KDB-SLI.
2-17-2 Block Diagram
2-62
Page 63
2-18 Power Supply
2-18-1 Block Diagram
Chapter 2. Circuit Description
2-63
Loading...