Samsung KP70DM1 Circuit Descriptions
Chapter 2
Circuit Description
2-1 008 Base B’d..............................................2-3
2-2 Mem Card................................................2-14
2-3 3 TRK Card..............................................2-17
2-4 6 TRK Card..............................................2-18
2-5 8 SLI Card................................................2-19
2-6 2 SLI Card................................................2-21
2-7 8 DLI Card................................................2-22
2-8 MISC Card...............................................2-23
2-9 S0T0 Card................................................2-28
2-10 PRI Card ..................................................2-36
2-11 PLL B’d ....................................................2-40
2-12 Ringer B’d................................................2-42
2-13 SIM Module..............................................2-42
2-14 DPIM Module...........................................2-45
2-15 Digital Keyset...........................................2-47
2-16 KDB-d B’d................................................2-60
2-17 KDB-s B’d ................................................2-62
2-18 Power Supply...........................................2-63
Chapter 2. Circuit Description
2-1 008 Base B’d
°‹008 Base B’d performs as a Mother B’d. The processor (MC68EC000) collects and analyzes
all the signal data occurred when the system operates, and determines the system operation.
°‹Memory consists of 1 M Bytes program ROM (To expand system program, ROM 1M Bytes
can be added) in the MEM B’d, and 256K Bytes RAM in the MEM B’d (basic 256K Bytes and
option 256K Bytes) .
512K Bytes RAM in the RAM B’d (include option 256K Bytes) is backed up by the battery to
save data in case of long time power failure (about 1 week). The backup switch should be
ON position to back up the memory.
°‹DTMF SENDER, TONE GENERATOR, TIMING GENERATOR, DSP TONE RECEIVER,
TIME SWITCH & CONFERENCE are composed into one ASIC STC-9604.
°‹DSP in the DKP ENGINE STC9604 receives the DTMF signal from the C.O. line. It can treat
4 channels (MAX) received at the same time.
°‹Time switch of the STC9604 accomodates 256 channels. Conference can be performed with
6 groups of 5 parties.
2-3
Chapter 2. Circuit Description
2-1-1 Block Diagram
MEM CARD
REAL TIME CLOCK(72423)
RESET AND WATCHDOG
ROM BASIC 1M bytes
Option. 1M bytes
RAM BASIC 256K bytes
Option. 256K byte
RING BOARD
SINE-WAVE RING
GENERATION
4SLI CARD
RING RELAY CONTROL
SLT HOOK DETETION
SLT LOOP DISCONNECT
MISC1(2) CARD
(AA 4 CHANNEL)
DTMFR 4 CHANNEL
B.G.M 1 PORT
DRY CONTACT 3 PORT
SERIAL DATA INTERFACE
R2 MFC or CALLER ID°ø4
CPU : 68EC000FN8/16
DKP ENGINE : STC9604
INTERRUPT LOGIC
LINE INTERFACE LOGIC
2/4 SLT CONTROL
B.G.M 1 PORT
M.O.H 1 PORT
DRY CONTACT 1
8 DGP INTERFACE
SLOT 1-6 : LINE CARD
1) EXP-8DLI : ANY SLOT
2) EXP-8SLI : ANY SLOT
3) EXP-6TRK : ANY SLOT
4) VDIAL : ANY SLOT
5) AA : ANY SLOT
6) EXP-3TRK : ANY SLOT
7) 4S0T0 : ANY SLOT
SLOT 7 : DCS PRI CARD
DKP MAIN ENGINE
STC9604, 208 PIN ASIC
CLOCK GENERATOR
TONE GENERATOR
DSP TONE RECEIVER
DECODING LOGIC
T-S/W & CONFERENCE
PROCESSOR SUPPORT
LOGIC
DPLL FOR 4 S0T0
2-4
Chapter 2. Circuit Description
2-1-2 Memory Map
ADDRESS SIG NAME READ WRITE REMARK
0XXXXX
1XXXXX
OROMEN1B
OROMEN2B
PROGRAM ROM(1MBYTE) : WORD
OPERATION, 27C4001°ø2 MEMCARD
PROGRAM ROM(1MBYTE) : WORD
OPERATION, 27C4001°ø2MEM CARD,
OPTION
2XXXXX
300001
300011
300021
3XXXXX 300031
300041
300051
300061
300071
400XX1
420001
420011
420021
420031
420041
OPCMCIAENB
CPM
DTMF/TONE
DETECTION
CONTROL
RTC
RESULT OF CH1 DETECTION
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ AA DSP SW RSTB
DSP CONTROL DSP CONTROL
SPEECH MEMORY £ ≠
CONF.1 CONTROL CONF.1 CONTROL
CONF.2 CONTROL CONF.2 CONTROL
CONF.3 CONTROL CONF.3 CONTROL
CONF.4 CONTROL CONF.4 CONTROL
CONF.5 CONTROL CONF.5 CONTROL
DETECT CNTL L
DETECT CNTL H
DOWNLOAD
DOWNLOAD
4XXXXX
420051
420061
420071
420801~
4209FF
440001~
440FFF
460001~
461FFF
TIME SWITCH
CONF.6 CONTROL
CONF.6 CONTROL BIT7=°Æ1°Ø: CM
READ ENABLE
OVERFLOW HIGHWAY ENABLE
STATUS CONTROL
£ ≠
SIGNALING
MEMORY
CONTROL CONTROL
MEMORY L
CONTROL CONTROL
MEMORY H
SM REGISTER
READ ENABLE
£ ≠
2-5
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
5XXXXX
TMC
£ ≠
6XXXXX
7XXXXX
800000~81FFFF
820000~83FFFF
840000~85FFFF
860000~87FFFF
880000~89FFFF
8A0000~8BFFFF
8C0000~8DFFFF
8EXXXX
QDMC
SIO
LINE CARD
ENABLE
/INTIDB
£ ≠
INTERNAL UART CONTROL & DPLL
MISC EN
RESERVED
RESERVED
SLOT1 (/CS1)
SLOT2 (/CS2)
SLOT3 (/CS3)
/UART (68681) EN
INTSIO : INT SIO (INTS) DATA FROM
SLOT1 TO SLOT7
D0 : /INTS0 (INTERNAL DMC)
D1 : /INTS1 (CS1 EN)
D2 : /INTS2 (CS2 EN)
D3 : /INTS3 (CS3 EN)
D4 : /INTS4 (EXP1 EN)
D5 : /INTS5 (EXP2 EN)
D6 : /INTS6 (EXP3 EN)
D7 : /INTU (UART & MODEM INT : MISC)
8FXXXX
9XXXXX
A00000~A7FFFF
A80000~AFFFFF
B00000~B7FFFF
B80000~BFFFFF
/INTIDB
/RAM1EN
/RAM2EN
/RAM3EN
/RAM4EN
INTDASL : INT DASL(INTD) DATA FROM
SLOT1 TO SLOT7
D0 : /INTS0 (INTERNAL DMC)
D1 : /INTS1 (CS1 EN)
D2 : /INTS2 (CS2 EN)
D3 : /INTS3 (CS3 EN)
D4 : /INTS4 (EXP1 EN)
D5 : /INTS5 (EXP2 EN)
D6 : /INTS6 (EXP3 EN)
RESERVED
512KBYTES, 681000°ø4, MEM CARD
512KBYTES, 681000°ø4, RESERVED
512KBYTES, 681000°ø4, RESERVED
512KBYTES, 681000°ø4, RESERVED
2-6
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
C00000~C1FFFF
/EXP1 EN
C20000~C3FFFF
C40000~C5FFFF
C60000~C7FFFF
C80000~C9FFFF
CA0000~CBFFFF
CC0000~CDFFFF
CE0000~CFFFFF
D00007~
D007FF
D00800~
D00FFF
D01000~
D017FF
D01801
D01811
D01821
LINE CARD
ENABLE(RSVB)
DTMF/TONE
GENERATION
/EXP2 EN
/EXP3 EN
/EXP4 EN
RESERVED
/WAT EN
/LED EN(monitor)
RING SYNC. INTERRUPT CLEAR
GAIN GAIN
STEP SIZE STEP SIZE
ACC RAM ACC RAM
CADENCE1 CADENCE1
CADENCE2 CADENCE2
MODE MODE
DXXXXX D01831
D01841
D01851
D01861
D01871
D01C01
D01C11
D01C21
D01C31
CONTROL
REGISTERS
CPM
DTMF/TONE
DETECTION
£ ≠ CNTL REG A
£ ≠ CNTL REG B
£ ≠ CNTL REG C
£ ≠ CNTL REG D
£ ≠ CNTL REG E
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
2-7
Chapter 2. Circuit Description
ADDRESS SIG NAME READ WRITE REMARK
E00001
RESULT OF CH1 DETECTION
DETECT CNTL L
EXXXXX
E00011
E00021
E00031
E00041
E00051
E00061
E00071
E00081
E00091
E000A1
E000B1
F00001
F00011
F00021
F00031
EXP 1
(DSPMODE)
DTMF/TONE
DETECTION
CONTROL
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ DSP SW RSTB
DSP CONTROL DSP CONTROL
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
RESULT OF CH1 DETECTION
RESULT OF CH2 DETECTION
RESULT OF CH3 DETECTION
RESULT OF CH4 DETECTION
DETECT CNTL H
DOWNLOAD CNTL L
DOWNLOAD CNTL H
DETECT CNTL L
DETECT CNTL H
DOWNLOAD CNTL L
DOWNLOAD CNTL H
FXXXXX
8, 9, E, FXXXXX
F00041
F00051
F00061
F00071
F00081
F00091
F000A1
F000B1
EXP 2
(DSPMODE)
DTMF/TONE
DETECTION
CONTROL
OEXDENB
DSP RAM L £ ≠
DSP RAM H £ ≠
£ ≠ DSP SW RSTB
DSP CONTROL DSP CONTROL
£ ≠ TIME SLOT1
£ ≠ TIME SLOT2
£ ≠ TIME SLOT3
£ ≠ TIME SLOT4
£ ≠
2-8
°‹A0 - A23 (Address Bus) : 16M byte Memory
°‹D0 - D15 (Data Bus) : LDS for D0 - D7, UDS for D8 - D15
°‹AS (Address Strobe) : Address is available while AS is low
°‹R/W (Read/Write)
°‹UDS, LDS (Upper and Lower Data Strobe)
°‹DTACK (Data Transfer Acknowledge) : Wait signal
°‹IPL2 ~ IPL0 (Interrupt Priority Level) : Interrupt priority level of 68EC000 is determined
with this 3 signal inputs.
Engine (STC-9604)
Clock generator
The 16MHz system clock output from 16MHz oscillator is provided to STC9604. Engine
(STL9604) generates 8.192MHz, 4.096MHz, 2.048MHz, 1KHz, and 20/25Hz, 8.192MHz is
provided to CPU and the rests are provided to the line control IC.
Time Switch
It performs switching for 8 highway (total 256 channels). 8-steps gain control is available.
Chapter 2. Circuit Description
2-9
UDS
0
0
1
1
LDS
0
1
0
1
Data Byte Selected
Word operation
Upper byte (D8 - D15)
Lower byte (D0 - D7)
No valid data
2-1-3 Circuit Description
CPU
CPU is fabricated using Motorola 68EC000FN8/16. 68EC000FN8/16 is compatible with 8-bit or
16-bit mode operation. 16-bit mode is available by setting MODE pin to high or open. In this
system. 16-bit mode is used. 8.192MHz supplied from STC9604 is used for clock and it is
required to apply over than 100ms for reset time.
Pin Description
Chapter 2. Circuit Description
Digital Conference
It is possible to support 6 groups of 5 parties. Any 5 of 256 channels can be assigned to the
station who is joined into the conference.
Tone/DTMF Generation
It generates 15 Dual/signal tones and 16 DTMFs at each 32 channels by using the sine wave
from data in STC9604.
Tone/DTMF Detection
Highway data from the time slot determined in TSAC is supplied from IDSPIN (Pin61) of
STC9604. The input signal is converted to 8-bit parallel data and stored into the allocated
registers for each channels.
The DSP core (inside STC9604) starts detecting by reading the enabled channel PCM data at
every 125µs interrupt, Detecting is achieved only with tone detect control register enabled
channel from CH1 to CH4 during 125µs interrupt. If a valid tone or DTMF signal is detected, the
result is recorded to the relevant register of each channels. CPU will read the data at the
register.
Digital Line Interface (DLI)
8 DLIs equipped into the 008 Base B’d performs interface between SIM, DPIM, and digital
phone. It uses QDASL chip (TP3404). The QDASL uses 2B+D at each port.
Signal transmission is achieved with 144 kbps full duplex AMI (Alternative Marking Inversion)
code transmission mode. End to end communication supports voice channel B1 and B2, and
two extension phones can be connected to 1 port.
192 kbps is used for actual transmission between DLI and digital phone, 16 kbps for sync, and
the rests are used for null data.
Transmission distance between DLI and digital phone covers a maximum of 400m by using
AWG26 transmission code.
2-10
Chapter 2. Circuit Description
Parallel control data out from UART of internal DMC (in the STC9604) is converted to serial
data and transmitted to DASL. DASL transmits the control data to the digital phone in a format
of AMI code. The control data out from the digital phone is transmitted to the CPU through the
reverse process.
Internal DMC interface
Address A4, 5, 8, 9, 10, 11, 16 are used for communication between DMC and CPU. There are
Addresses to read/write each port D CH’s data, to be masking INT status, to read INT status of
DASL and to be setting as the LOOP BACK MOOD for test. The interface includes the data bus
D0 - D7 and INT Rx0, Rx1, and INT Tx0, Tx1. The Rx INT will be enable when even one byte is
received in the buffer, and Tx INT will be enable when the buffer is empty.
If INT is enabled, CPU reads the INT status and performs INT service for the port of the
selected bit. The INT status is cleared as soon as CPU read it. For highway (B-CH) control
HC125 (Tristate Buffer) is located between the time switch and DASL, it is enabled by TRS
(pin14) of DASL. BCLKx (2.048MHz), B4M, and CCLK (1.028MHz) are provided for clock.
QDASL Interface
DX & DR can transmit D-CH’s serial data of each port. B-CH & D-CH are scrambled to the AMI
code and transmitted with line.
INT0 - INT1 are used to control the micro channel interrupt of each channel. DASL INT is
occured only when micro channel access. No signal (C0), Out of SYNC (C1), and Bipolar
violation (C7) are required to generate DASL INT. Since INT occurs only when power turns on
at first time and the DASL status is changed by some error, INT is designed to tie up with UART
Tx by using AND gate.
DGP Interface
DLT1 (T2-5, T7-10) is used for matching transformer. Resistance (100Ω) at L0 of DASL is for
matching Impedance. 2 µF are used to reduce noise. Zener Diode is for hazard protection.
2-11
Chapter 2. Circuit Description
TMC
Internal TMC (Trunk 8 Channel)
BGM 1 Port
008 Base B’d has one optional background music input 1 port. It can be selected between
Internal and External. In case of Internal, used to melody IC.
PAGE 1 Port
The port is for external paging. PCM data (from highway 0 Rx) is switched to analog signal and
the analog signal is fed to transformer (T2).
DRY Contact
It is dry contact relay 1 port. It makes use of EXTACT signal that received from engine to
operate Relay.
Control Signal for 2 or 4 SLI
It is generated at TMC port (in engine) to control 2 or 4 SLI card.
MISC Interface
It includes Dry contact, external MOH, RS232C interface, 4 Channel DTMF receiver, 4 Channel
Automatic Attendant (AA), Caller ID, Alarm Sensing.
2-12
Chapter 2. Circuit Description
Expand B’d Interface
64pin connector is provided to connect the signals to expand the B’ds. Refer to the circuit
diagram for the pin assignment.
DPLL (Digital Phase Locked Loops)
°‹Produced 4.096MHz for S0T0
°‹2 kinds of DPLL support for PRI (Primary Rate Interface) - for testing
°‹Use Clock Burst Correction Scheme with using Master Clock Divide
Address Bus
$ 700,001H
$ 700,011H
Data Bus (D7 - D0)
Micro-processor Write
D-PLL Control Register Write
D-PLL Test Register Write
D-PLL Register Map
Micro-processor Read
Readable
Readable
2-13
Chapter 2. Circuit Description
2-2 MEM Card
Capacity
Basic ROM
Option ROM
Basic RAM
Option RAM
1M Bytes
Address Scope : $000,000H$-OFF, FFFH
1M Bytes
Address Scope : $100,000H-$1FF, FFFH
256K Bytes Basic
Address Scope : $A00,000H-$A3F, FFFH
256K Byte
Address Scope : $B00,000H-$B3F, FFFH
27C4001 °ø 2
27C4001 °ø 2
681000 °ø 2
681000 °ø 2
2-2-1 Circuit Description
Real Time Clock (RTC)
RTC72423 (U12) which has small access time is used for RTC (Real Time Clock). It is
equipped in the MEM Card for battery back up function. CPU is connected at data bus D8 - D11
and A1 - A4 is used.
Memory Backup
60mAH battery equipped in the MEM Card is used for memory backup by 4 RAMs and RTC IC
in case of power failure for a maximum of one week. To erase the RAM and the RTC data, set
the backup switch to OFF and turn the power OFF. Software reset also available.
Watch Dog
It monitors the address within the specified range and reset the system if it cannot access the
address within a specified time. If the program does not work properly, the watch dog address
can not be accessed within a specified time, and Watch dog circuit resets CPU. Watchdog is
inserted to ST*of Micromonitor Chip DS1232S (DALLAS).
2-14
5V
Chapter 2. Circuit Description
10 mSec
More than 20nsec when DS1232 is used.
TD
TIMEOUT (mSec)
GND
FLOAT
Vcc
Min
62.5
250
400
Watchdog timeouts of DS1232
Typical
150
600
1200
Max
250
1000
2000
When watchdog works DS1232 guratees the reset time of minimum 250 ms, which result in
CPU reset time to be of 100ms. Output reset time is adjustable by controlling TP pin of
DS1232.
Power On Reset
DS1232S resets the CPU when power turns ON. It stabilizes the system operation. DS1232
accepts a minimum of 250ms as reset time and the reset voltage to be 4.5V by adjusting TOL
pin.
Voltage
TOL Pin 3
VCC
GND
Min
– 5V
– 5V
Typical
4.5V
4.75V
Max
+ 5V
+ 5V
DS1232S Minimum Reset voltage
Manual Reset
Manual Reset can be operated by turn on TACT SWITCH being connected PBRST*pin.
2-15
Chapter 2. Circuit Description
LED Indication
One LED which shows the system status according to the system programming is equipped in
the mem card.
LED Off : Abnormal power
LED On : Power is normal but system does not work properly
LED Flicker : Both power and system are normal. (Normal system means memory read/write
and decoding logic work properly)
2-16
2-3 3-TRK Card
2-3-1 Block Diagram
Chapter 2. Circuit Description
2-3-2 Circuit Description
Loop Trunk Interface 3 Port
Sending and Receiving voice frequency range (300 ~ 3400Hz) between keyphone system and
trunk line are achived with DC Current Bypass Circuit, Matching Transformer, Balancing
Network, Hybrid Circuit, PCM Codec, Channel Assign Timing Control, Digital Gain Control
circuit. DC By-pass circuit is needed for using small transformer with DC bypass before T1, T2,
T3 transformer. Off-hook (H.O.S) & Ring Signal Detecting Circuit are in this internal circuit.
Loop Start Trunk is applied to system which has complex resistive impedance.
2-17
Chapter 2. Circuit Description
Surge and Over Voltage Protection Circuit
FUSE TYPE SURGE - Absorber for first protection circuit, T.V.S (1.5KE15A) for second
protection circuit and ZENER DIODE for third protection circuit are provided to protect the
system from surge and over voltage damage at 3 trunk lines.
P.R.S (Hook On/Off Sensing) Circuit
It is signal polarity reverse detecting circuit of C.O line interface. Be careful TIP - RING LEAD’s
polarity when installing system at the site.
Ring incoming signal detection circuit
Ring Incoming signal from C.O is available when TRK interface is hook-on status, regardless of
trunk type. DC voltage of Ring signal is cut by poly - capacity (0.82µF/250V) and ring signal
above reference value (relation with Zener diode (5.1V)) is passed.
Ring signal generates Ring Detection Signal when above setting voltage (1.2V) is flowed
through serial connected Diode (2EA) and parallel connected photo coupler input. It switched
high if righ signal is applied.
DC Current Bypass Circuit
This circuit seizures DC LOOP and passes AC signal to the next step. It generates output of
H.O.S detection to the system with photo coupler.
Caller ID Relay
It makes PATH (by RL4, RL5, RL6) to Detect Caller ID in 1200 bps FSK signal received
between ring and ring during ON HOOK state. DSP for Caller ID is in the MISC card.
Balance Network
It is used for 2W/4W interface. Tx uses OP AMP(3404) and Rx uses OP AMP in the codec.
2-4 6 TRK Card
It has 6 loop start trunk port and 2 PFT port.
2-18
2-5 8 SLI Card
2-5-1 Block Diagram
Chapter 2. Circuit Description
SURGE
PROTECTION
CC°ØT
RING
GENERATION
CC°ØT
FEEDING
CC°ØT
MATCHING
TRANS.
SBS 9401
¶UMODE CONTROL
¶UTIME SLOT ASSIGNMENT
¶UUART(4PORTS)
¶UDIAL PULSE GEN.(4PORTS)
¶UI/O DETECT
(HOS/LOOP DISCONNECT)
GAIN
BALANCE
CC°ØT
A-LAW
CODEC
(TP3057)
TSAC
2-5-2 Circuit Description
Voice Path
The voice signal from subscriber is fed to primary T1 with AC plus DC forms. The output signal
from T1 is AC signal. Balance logic with using OP - AMP (MC34072D) transmits and receives
+2.0dBm to the Tx port of CODEC, –7.0 dBm down to the subscriber from Rx port, then is
supplied to HIGHWAY 0 after converts signal as PCM Code by CODEC.
CODEC receives 2.048MHz clock frequency, and loads 8KHz Delayed PCM DATA to DX & DR
by sampling for each 8KHz. A - LOW is used by Pull UP BCLKR, 7th Pin of codec.
2-19
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