SAMSUNG KMM53216000BK Technical data

DRAM MODULE KMM53216000BK/BKG

KMM53216000BK/BKG Fast Page Mode

16M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V

The Samsung KMM53216000B is a 16Mx32bits Dynamic

RAM high density memory module. The Samsung

KMM53216000B consists of eight CMOS 16Mx4bits DRAMs

in SOJ packages mounted on a 72-pin glass-epoxy substrate.

A 0.1 or 0.22uF decoupling capacitor is mounted on the

printed circuit board for each DRAM. The KMM53216000B is

a Single In-line Memory Module with edge connections and is

intended for mounting into 72 pin edge connector sockets.

• Part Identification

- KMM53216000BK(4K cycles/64ms Ref, SOJ, Solder)

- KMM53216000BKG(4K cycles/64ms Ref, SOJ, Gold)

• Fast Page Mode Operation

• CAS

-before-RAS & Hidden Refresh capability

• RAS-only refresh capability

• TTL compatible inputs and outputs

• Single +5V±10% power supply

• JEDEC standard PDpin & pinout

• PCB : Height(1250mil), double sided component

GENERAL DESCRIPTION FEATURES

PERFORMANCE RANGE

Speed

tRAC tCAC tRC tPC

-5 50ns 13ns 90ns 35ns

-6 60ns 15ns 110ns 40ns

PIN NAMES

Pin Name Function

A0 - A11 Address Inputs

DQ0-7, DQ9-16

DQ18-25, DQ27-34

Data In/Out

Read/Write Enable

RAS0

, RAS2 Row Address Strobe

CAS0 - CAS3 Column Address Strobe

PD1 -PD4 Presence Detect

Vcc Power(+5V)

Vss Ground

NC No Connection

PRESENCE DETECT PINS (Optional)

Pin 50NS 60NS

PD1

PD2

PD3

PD4

Vss

PIN CONFIGURATIONS

Symbol

VSS

DQ0

DQ18

DQ1

DQ19

DQ2

DQ20

DQ3

DQ21

Vcc

A10

DQ4

DQ22

DQ5

DQ23

DQ6

DQ24

DQ7

DQ25

A11

Vcc

RAS2

Symbol

Vss

CAS0

CAS2

CAS3

CAS1

RAS0

DQ9

DQ27

DQ10

DQ28

DQ11

DQ29

DQ12

DQ30

DQ13

DQ31

Vcc

DQ32

DQ14

DQ33

DQ15

DQ34

DQ16

PD1

PD2

PD3

PD4

Vss

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

查询KMM53216000BK供应商

DRAM MODULE KMM53216000BK/BKG

FUNCTIONAL BLOCK DIAGRAM

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS0

RAS0

Vcc

Vss

0.1 or 0.22uF Capacitor

for each DRAM

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

CAS

RAS

DQ1

DQ2

DQ3

DQ4

A0-A11

To all DRAMs

CAS1

CAS2

RAS2

CAS3

A0-A11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DRAM MODULE KMM53216000BK/BKG

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.

ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,

address can be changed maximum once within one Fast page mode cycle time, tPC.

* NOTE :

ABSOLUTE MAXIMUM RATINGS *

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended

periods may affect device reliability.

Item Symbol Rating Unit

Voltage on any pin relative to VSS

Voltage on VCC supply relative to VSS

Storage Temperature

Power Dissipation

Short Circuit Output Current

VIN, VOUT

VCC

Tstg

IOS

-1 to +7.0

-55 to +125

°C

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)

*1 : VCC+2.0V at pulse width ≤ 20ns, which is measured at V CC.

*2 : -2.0V at pulse width ≤ 20ns, which is measured at VSS.

Item Symbol Min Typ Max Unit

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

VCC

VSS

VIH

VIL

4.5

2.4

-1.0

5.0

5.5

VCC

0.8

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)

ICC1

ICC2

ICC3

ICC4

ICC5

ICC6

I(IL)

I(OL)

VOH

VOL

Symbol Speed

KMM53216000BK/BKG

Unit

Min Max

ICC1

-5

-6

960

880

ICC2 Don′t care - 16 mA

ICC3

-5

-6

960

880

ICC4

-5

-6

560

480

ICC5 Don′t care - 8 mA

ICC6

-5

-6

960

880

II(L)

IO(L)

Don′t care

-10

-5

VOH

VOL

Don′t care

2.4

0.4

: Operating Current * (RAS, CAS, Address cycling @tRC=min)

: Standby Current (RAS=CAS=W=VIH)

: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)

: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)

: Standby Current (RAS=CAS=W=Vcc-0.2V)

: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)

: Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)

: Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)

: Output High Voltage Level (IOH = -5mA)

: Output Low Voltage Level (IOL = 4.2mA)

DRAM MODULE KMM53216000BK/BKG

CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)

Item Symbol Min Max Unit

Input capacitance[A0-A11]

Input capacitance[W]

Input capacitance[RAS0, RAS2]

Input capacitance[CAS0 - CAS3]

Input/Output capacitance[DQ0-7, 9-16,18-25, 27-34]

CIN1

CIN2

CIN3

CIN4

CDQ

Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF

Parameter Symbol

-5 -6

Unit Note

Min Max Min Max

Random read or write cycle time

tRC

90 110 ns

Access time from RAS

tRAC

50 60 ns 3,4,10

Access time from CAS

tCAC

13 15 ns 3,4,5

Access time from column address

tAA

25 30 ns 3,10

CAS to output in Low-Z

tCLZ

0 0 ns 3

Output buffer turn-off delay

tOFF

0 13 0 15 ns 6

Transition time(rise and fall)

1 50 1 50 ns 2

RAS precharge time

tRP

30 40 ns

RAS pulse width

tRAS

50 10K 60 10K ns

RAS hold time

tRSH

13 15 ns

CAS hold time

tCSH

50 60 ns

CAS pulse width

tCAS

13 10K 15 10K ns

RAS to CAS delay time

tRCD

20 37 20 45 ns 4

RAS to column address delay time

tRAD

15 25 15 30 ns 10

CAS to RAS precharge time

tCRP

5 5 ns

Row address set-up time

tASR

0 0 ns

Row address hold time

tRAH

10 10 ns

Column address set-up time

tASC

0 0 ns

Column address hold time

tCAH

10 10 ns

Column address to RAS lead time

tRAL

25 30 ns

Read command set-up time

tRCS

0 0 ns

Read command hold referenced to CAS

tRCH

0 0 ns 8

Read command hold referenced to RAS

tRRH

0 0 ns 8

Write command hold time

tWCH

10 10 ns

Write command pulse width

tWP

10 10 ns

Write command to RAS lead time

tRWL

15 15 ns

Write command to CAS lead time

tCWL

13 15 ns

Data set-up time

tDS

0 0 ns 9

Data hold time

tDH

10 10 ns 9

Refresh period

tREF

64 64 ms

Write command set-up time

tWCS

0 0 ns 7

CAS setup time(CAS-before-RAS refresh)

tCSR

5 5 ns

CAS hold time(CAS-before-RAS refresh)

tCHR

10 10 ns

RAS to CAS precharge time

tRPC

5 5 ns

Access time from CAS precharge

tCPA

30 35 ns 3

AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)

DRAM MODULE KMM53216000BK/BKG

NOTES

An initial pause of 200us is required after power-up followed

by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-

erence levels for measuring timing of input signals. Transi-

tion times are measured between VIH(min) and VIL(max) and

are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the tRCD(max) limit insures that tRAC(max)

can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then

access time is controlled exclusively by tCAC.

Assumes that tRCD≥tRCD(max).

This parameter defines the time at which the output achieves

the open circuit condition and is not referenced to VOH or

VOL.

tWCS is non-restrictive operating parameter. It is included in

the data sheet as electrical characteristics only. If

tWCS≥tWCS(min), the cycle is an early write cycle and the

data out pin will remain high impedance for the duration of

the cycle.

Either tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in

early write cycles.

Operation within the tRAD(max) limit insures that tRAC(max)

can be met. tRAD(max) is specified as reference point only. If

tRAD is greater than the specified tRAD(max) limit, then

access time is controlled by tAA.

10.

Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF

Parameter Symbol

-5 -6

Unit Note

Min Max Min Max

Fast page mode cycle time

tPC

35 40 ns

CAS precharge time(Fast page cycle)

tCP

10 10 ns

RAS pulse width(Fast page cycle)

tRASP

50 200K 60 200K ns

W to RAS precharge time(C-B-R refresh)

tWRP

10 10 ns

W to RAS hold time(C-B-R refresh)

tWRH

10 10 ns

AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)

DRAM MODULE KMM53216000BK/BKG

tCRP

RAS

VIH -

VIL -

CAS

VIH -

VIL -

VIH -

VIL -

VIH -

VIL -

VIH -

VIL -

VOH -

VOL -

READ CYCLE

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tRAD

tASR tRAH

tASC

tCAH

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

tOEZ

tRRH

tRCH

Don′t care

Undefined

tRCS

tOFF

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