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KM68V1000B, KM68U1000B Family CMOS SRAM
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
2.0
History
Initial draft
Finalize
Revise
- Change datasheet format
Draft Data
August 12, 1995
April 12, 1996
March 7, 1998
Remark
Preliminary
Final
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
• Process Technology : Poly Load
• Organization : 128Kx8
• Power Supply Voltage :
KM68V1000B family : 3.0~3.6V
KM68U1000B family : 2.7~3.3V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
GENERAL DESCRIPTION
The KM68V1000B and KM68U1000B families are fabricated
by SAMSUNG′s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The families also support low data retention voltage for
battery back-up operation with low data retention current.
• Package Type : 32-SOP, 32-TSOP1-0820F/R
PRODUCT FAMILY
Product Family Operating Temperature Vcc Range Speed(ns)
KM68V1000BL/L-L
KM68U1000BL/L-L 2.7~3.3V 100
KM68V1000BLE/LE-L
KM68U1000BLE/LE-L 2.7~3.3V 100
KM68V1000BLI/LI-L
KM68U1000BLI/LI-L 2.7~3.3V 100
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A11
1
A9
2
A8
3
A13
4
WE
5
CS2
N.C
A16
A14
A12
I/O1
I/O2
I/O3
VSS
VCC
1
2
3
4
5
A7
6
A6
7
A5
32-SOP
8
A4
9
A3
A2
10
A1
11
12
A0
13
14
15
16
32
A15
31
CS2
30
WE
29
A13
28
27
A8
26
A9
25
A11
24
OE
23
A10
22
CS1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
Name Function
CS1,CS2 Chip Select Inputs
OE Output Enable Input
WE Write Enable Input
A0~A16 Address Inputs
I/O1~I/O8 Data Inputs/Outputs
Vcc Power
Vss Ground
N.C No Connection
A15
VCC
A16
A14
A12
A12
A14
A16
A15
VCC
CS2
A13
WE
A11
6
7
8
NC
9
10
11
12
A7
13
A6
14
A5
15
A4
16
16
A4
15
A5
14
A6
13
A7
12
11
10
9
NC
8
7
6
5
4
3
A8
2
A9
1
32-TSOP
Type 1 - Forward
32-TSOP
Type 1 - Reverse
3.0~3.6V
3.0~3.6V
3.0~3.6V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
701)/100
701)/100
701)/100
FUNCTIONAL BLOCK DIAGRAM
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
CS1
CS2
WE
OE
Power Dissipation
Standby
(ISB1, Max)
50/15µA
50/15µA
100/20µA
50/15µA
100/20µA
50/15µA
Clk gen.
A4
A5
A6
A7
A12
A13
A14
A15
A16
I/O1 Data
I/O8
Control
Logic
Row
select
cont
Data
cont
Operating
(ICC2, Max)
40mA
A0 A1 A2 A3 A8 A10A9
PKG Type
32-SOP
32-TSOP1- R/F
Precharge circuit.
Memory array
512 rows
256×8 columns
I/O Circuit
Column select
A11
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
PRODUCT LIST
Commercial Temperarure Products
(0~70°C)
Part Name Function Part Name Function Part Name Function
KM68V1000BLG-7
KM68V1000BLG-10
KM68V1000BLT-7
KM68V1000BLT-10
KM68V1000BLR-7
KM68V1000BLR-10
KM68V1000BLG-7L
KM68V1000BLG-10L
KM68V1000BLT-7L
KM68V1000BLT-10L
KM68V1000BLR-7L
KM68V1000BLR-10L
KM68U1000BLG-10
KM68U1000BLT-10
KM68U1000BLR-10
KM68U1000BLG-10L
KM68U1000BLT-10L
KM68U1000BLR-10L
32-SOP,70ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
32-SOP,70ns,3.3V,LL
32-SOP,100ns,3.3V,LL
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL
32-TSOP R,70ns,3.3V,LL
32-TSOP R,100ns,3.3V,LL
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
32-SOP,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL
32-TSOP R,100ns,3.0V,LL
FUNCTIONAL DESCRIPTION
CS1 CS2 OE WE I/O Pin Mode Power
H
1)
X
1)
X
L
L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H
1. X means don′t care(Must be in high or low status.)
1)
X
1)
X
1)
X
Extended Temperarure Products
(-25~85°C)
KM68V1000BLGE-7
KM68V1000BLGE-10
KM68V1000BLTE-7
KM68V1000BLTE-10
KM68V1000BLRE-7
KM68V1000BLRE-10
KM68V1000BLGE-7L
KM68V1000BLGE-10L
KM68V1000BLTE-7L
KM68V1000BLTE-10L
KM68V1000BLRE-7L
KM68V1000BLRE-10L
KM68U1000BLGE-10
KM68U1000BLTE-10
KM68U1000BLRE-10
KM68U1000BLGE-10L
KM68U1000BLTE-10L
KM68U1000BLRE-10L
1)
X
1)
X
32-SOP,70ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
32-SOP,70ns,3.3V,LL
32-SOP,100ns,3.3V,LL
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL
32-TSOP R,70ns,3.3V,LL
32-TSOP R,100ns,3.3V,LL
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
32-SOP,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL
32-TSOP R,100ns,3.0V,LL
High-Z Deselected Standby
High-Z Deselected Standby
Industrial Temperarure Products
(-40~85°C)
KM68V1000BLGI-7
KM68V1000BLGI-10
KM68V1000BLTI-7
KM68V1000BLTI-10
KM68V1000BLRI-7
KM68V1000BLRI-10
KM68V1000BLGI-7L
KM68V1000BLGI-10L
KM68V1000BLTI-7L
KM68V1000BLTI-10L
KM68V1000BLRI-7L
KM68V1000BLRI-10L
KM68U1000BLGI-10
KM68U1000BLTI-10
KM68U1000BLRI-10
KM68U1000BLGI-10L
KM68U1000BLTI-10L
KM68U1000BLRI-10L
32-SOP,70ns,3.3V,L
32-SOP,100ns,3.3V,L
32-TSOP F,70ns,3.3V,L
32-TSOP F,100ns,3.3V,L
32-TSOP R,70ns,3.3V,L
32-TSOP R,100ns,3.3V,L
32-SOP,70ns,3.3V,LL
32-SOP,100ns,3.3V,LL
32-TSOP F,70ns,3.3V,LL
32-TSOP F,100ns,3.3V,LL
32-TSOP R,70ns,3.3V,LL
32-TSOP R,100ns,3.3V,LL
32-SOP,100ns,3.0V,L
32-TSOP F,100ns,3.0V,L
32-TSOP R,100ns,3.0V,L
32-SOP,100ns,3.0V,LL
32-TSOP F,100ns,3.0V,LL
32-TSOP R,100ns,3.0V,LL
L Din Write Active
ABSOLUTE MAXIMUM RATINGS
1)
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOU -0.5 to VCC+0.5 V Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V Power Dissipation PD 0.7 W Storage temperature TSTG -65 to 150 °C -
0 to 70 °C KM68V1000BL, KM68U1000BL
Operating Temperature TA
-25 to 85 °C KM68V1000BLE, KM68U1000BLE
-40 to 85 °C KM68V1000BLI, KM68U1000BLI
Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS
Item Symbol Product Min
Supply voltage Vcc
Ground Vss All Family 0 0 0 V
Input high voltage VIH KM68V1000B, KM68U1000B Family 2.2 Input low voltage VIL KM68V1000B, KM68U1000B Family
Note:
1. Commercial Product : TA=0 to 70°C, unless otherwise specified
Extended Product : TA=-25 to 85°C, unless otherwise specified
Industrial Product : TA=-40 to 85°C, unless otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
Input capacitance CIN VIN=0V - 6 pF
Input/Output capacitance CIO VIO=0V - 8 pF
1. Capacitance is sampled not, 100% tested
1)
(f=1MHz, TA=25°C)
Item Symbol Test Condition Min Max Unit
KM68V1000B Family
KM68U1000B Family
1)
Max Unit
3.6
3.3
2)
Vcc+0.3
3.0
2.7
-0.3
Typ
3.3
3.0
3)
- 0.4 V
DC AND OPERATING CHARACTERISTICS
V
V
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS1=VIH or CS2=VIL or WE=VIL, Vio=Vss to Vcc -1 - 1 µA
Operating power supply current ICC CS1=VIL,CS2=VIH,VIN=VIH or VIL, IIO=0mA - 2 5 mA
Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V,
ICC1
Average operating current
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.2 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL - - 0.3 mA
KM68V1000BL/L-L
Standby
Current
(CMOS)
KM68V1000BLE/LE-L
KM68V1000BLI/LI-L
KM68U1000BL/L-L
KM68U1000BLE/LE-L
KM68U1000BLI/LI-L
CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
ICC2 Min cycle, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH - 30 40 mA
Low Power
Low Low Power
CS1≥Vcc-0.2V
ISB1
CS2≥Vcc-0.2V or CS2≤0.2V
Other input =0~Vcc
Low Power
Low Low Power
Low Power
Low Low Power
Low Power
Low Low Power
- 3 5 mA
-
1.0
50
-
-
-
-
-
-
-
0.5
1.0
0.5
1.0
0.55015
1.0
0.5
15
100
20
50
15
µA
µA
µA
µA
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
AC CHARACTERISTICS (Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product : TA=-40 to 85°C
KM68V1000B Family:Vcc=3.0~3.6V, KM68U1000B Family:Vcc=2.7~3.3V)
Parameter List Symbol
Min Max Min Max
Read cycle time tRC 70 - 100 - ns
Address access time tAA - 70 - 100 ns
Chip select to output tCO - 70 - 100 ns
Output enable to valid output tOE - 35 - 50 ns
Read
Write
Chip select to low-Z output tLZ 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - ns
Chip disable to high-Z output tHZ 0 25 0 30 ns
Output disable to high-Z output tOHZ 0 25 0 30 ns
Output hold from address change tOH 10 - 15 - ns
Write cycle time tWC 70 - 100 - ns
Chip select to end of write tCW 60 - 80 - ns
Address set-up time tAS 0 - 0 - ns
Address valid to end of write tAW 60 - 80 - ns
Write pulse width tWP 55 - 70 - ns
Write recovery time tWR 0 - 0 - ns
Write to output high-Z tWHZ 0 25 0 30 ns
Data to write time overlap tDW 30 - 40 - ns
Data hold from write time tDH 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - ns
1)
CL
1. Including scope and jig capacitance
Speed Bins
70ns 100ns
Units
DATA RETENTION CHARACTERISTICS
Item Symbol
Vcc for data retention VDR
KM68V1000BL/L-L
KM68V1000BLE/LE-L
Data retention current IDR
Data retention set-up time tSDR
Recovery time tRDR 5 - -
1. CS≥VCC-0.2V, CS2≥VCC-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)
KM68V1000BLI/LI-L
KM68U1000BL/L-L
KM68U1000BLE/LE-L
KM68U1000BLI/LI-L
CS11)≥Vcc-0.2V
Vcc=3.0V
CS1≥Vcc-0.2V
CS2≥Vcc-0.2V
or CS2≤0.2V
See data retention waveform
Test Condition
Low Power
Low Low Power
Low Power
Low Low Power
Low Power
Low Low Power
Low Power
Low Low Power
Min Typ Max Unit
2.0 - 3.6 V
-
1
-
0.5
-
-
-
-
-
-
-
-
-
-
-
-
0 - -
30
15
50
20
µA
25
10
25
15
ms
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VlL, WE=VIH)
tRC
Address
tAA
tAA
Data Valid
tRC
tOH
tCO1
tHZ(1,2)
tOH
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS1
CS2
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
High-Z
tLZ
tOLZ
tCO2
tOE
tOHZ
Data Valid
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
CS2
tCW(2)
tAW
tCW(2)
tWR(4)
WE
tAS(3)
Data in
tWHZ
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
Address
tAS(3)
CS1
CS2
WE
Data in
tWC
tCW(2)
tAW
tWP(1)
tWP(1)
tDW
Data Valid
tDW
Data Valid
tDH
tOW
tWR(4)
tDH
Data out
High-Z
High-Z
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
High-Z
tWP(1)
tDW
Data Valid
tDH
High-Z
DATA RETENTION WAVE FORM
CS1 controlled
VCC
1)
3.0/2.7V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS1
GND
CS2 controlled
VCC
1)
3.0/2.7V
CS2
VDR
0.4V
GND
CS1≥VCC - 0.2V
Data Retention Mode
tSDR
CS2≤0.2V
1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family
tRDR
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
PACKAGE DIMENSIONS
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
#32
#1
20.87
MAX
0.822
20.47±0.20
0.806±0.008
#17
#16
14.12±0.30
0.556±0.012
2.74±0.20
0.108±0.008
3.00
0.118
11.43±0.20
0.450±0.008
MAX
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.10 MAX
0.004 MAX
Units : millimeter(inch)
0~8°
13.34
0.525
0.80±0.20
0.031±0.008
0.71
( )
0.028
0.41
0.016
+0.100
-0.050
+0.004
-0.002
1.27
0.050
0.05
0.002
MIN
Revision 2.0
March 1998
KM68V1000B, KM68U1000B Family CMOS SRAM
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
0.50
0.0197
0~8°
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
#16
20.00±0.20
0.787±0.008
18.40±0.10
0.724±0.004
#32
8.40
0.331
#17
0.15
0.006
0.50
( )
0.020
Units : millimeter(inch)
MAX
8.00
0.315
1.00±0.10
0.039±0.004
1.20
MAX
0.047
+0.10
-0.05
+0.004
-0.002
0.25
( )
0.010
0.05
0.002
0.10MAX
0.004MAX
MIN
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
0.50
0.0197
0~8°
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#16
#1
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
20.00±0.20
0.787±0.008
18.40±0.10
0.724±0.004
#17
#32
( )
0.020
0.039±0.004
1.20
0.047
0.15
0.006
0.50
MAX
8.40
0.331
1.00±0.10
MAX
+0.10
-0.05
+0.004
-0.002
0.25
( )
0.010
8.00
0.315
0.05
MIN
0.002
0.10 MAX
0.004 MAX
Revision 2.0
March 1998
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