KM68B261A BiCMOS SRAM
32K x 8 Bit High-Speed BiCMOS Static RAM
FEATURES
• Fast Access Time 6,7,8ns(Max.)
• Low Power Dissipation
Standby (TTL) : 110 mA(Max.)
(CMOS) : 20 mA(Max.)
Operating Current : 170 mA(f=100MHz)
• Single 5V ± 5% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68B261AJ : 32-SOJ-300
FUNCTIONAL BLOCK DIAGRAM
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
I/O1-I/O8
Row Select
Data
Cont.
MEMORY ARRAY
128 Rows
256x8 Columns
I/O Circuit
Column Select
GENERAL DESCRIPTION
The KM68B261A is a 262,144-bit high-speed Static
Random Access Memory organized as 32,768 words by
8 bits. The KM68B261A uses eight common input and
output lines and has an output enable pin which
operates faster than address access time at read cycle.
The device is fabricated using Samsung`s advanced
BiCMOS process and designed for high-speed system
applications. It is particularly well suited for use in highdensity high-speed system applications. The
KM68B261A is packaged in a 300 mil 32-pin plastic
SOJ.
PIN CONFIGURATION(TOP VIEW)
/CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
/WE
1
A0
2
A1
3
A2
4
A3
5
6
7
8
SOJ
9
10
11
12
13
A4
14
A5
15
A6
16
A7
32
N.C
31
A14
30
A13
29
A12
28
/OE
27
I/O8
26
I/O7
25
Vss
24
Vcc
23
I/O6
22
I/O5
21
A11
20
A10
19
A9
18
A8
17
N.C
/CS
/WE
/OE
A7 A8 A9 A10 A11 A12 A13 A14
PIN DESCRIPTION
Pin Name Pin Function
A0-A14
/WE
/CS
/OE
I/O1-I/O8
Vcc
Vss
N.C
1
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power (5V)
Ground
No Connection
Rev 2.0
October-1994
KM68B261A BiCMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
Operating Temperature
Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device.
*
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIN,OUT
Vcc
PD
Tstg
TA
- 0.5 to 7.0
- 0.5 to 7.0
1.0
- 65 to 150
0 to 70
V
V
W
°C
°C
RECOMMENDED DC OPERATING CONDITIONS(TA= 0 to 70 °C )
Parameter Symbol Min Typ. Max Unit
Supply Voltage
Ground
Input Low Voltage
Input High Voltage
* VIL(Min) = -2.0 (Pulse Width for I
** VIH(Max) = Vcc+2.0V(Pulse width for I
≤3ns)
Vcc
Vss
VIH
VIL
≤ 8ns)
≤ 20mA
≤ 20mA
4.75
0
2.2
-0.5*
5.0
0
5.25
0
-
-
Vcc+0.5**
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(TA= 0 to 70°C, Vcc=5 V 5%, unless otherwise specified)
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Output Low Voltage
Output High Voltage
±
ILI
ILO
ICC
ISB
ISB1
VOL
VOH
VIN=Vss to Vcc
/CS=VIH or /OE=VIH or /WE=VIL
VOUT=VSS to Vcc
f=100MHz, 100% Duty, /CS=VIL,
VIN=VIH or VIL, IOUT=0mA
Min. Cycle, /CS=VIH
f=0MHz, /CS -0.2V,
≥ Vcc ≤ 0.2V
VIN -0.2V or VIN
IOL=8mA
IOH = - 4mA
≥ Vcc
-10
-10
-
-
-
-
2.4
2
10
10
170
110
20
0.4
-
October-1994
µA
µA
mA
mA
mA
V
V
Rev 2.0
KM68B261A BiCMOS SRAM
CAPACITANCE*(f=1MHz, TA =25 °C)
Item Symbol Test Condition Min. Max. Unit
Input Capacitance
Input/Output Capacitance
* Note: Capacitance is sampled and not 100% tested.
CIN
CI/O
VIN=0V
VI/O=0V
-
-
7
7
AC CHARACTERISTICS
TEST CONDITIONS ON DATA RAM(TA= 0 to 70°C, Vcc=5V 5%, unless otherwise specified.)
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Output Load (A)
DOUT
ZO=50
Ω
RL=50
Ω
Output Load (B)
for tHZ, tLZ, tWHZ, tOW, tOLZ, & tOHZ
DOUT
255
±
Ω
Value
0 to 3 V
3ns
1.5V
See below
+5V
480
Ω
5pF*
pF
pF
VL =1.5V
* Including Scope and Jig Capacitance
3
Rev 2.0
October-1994
KM68B261A BiCMOS SRAM
READ CYCLE
Parameter Symbol
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
WRITE CYCLE
Parameter Symbol
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width(/OE High)
Write Pulse Width(/OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWP
tWR
tWHZ
tDW
tDH
tOW
KM68B261A-6
Min Max
6
-
-
3
1
0
0
3
KM68B261A -6
Min Max
6
6
0
3.5
3.5
6
1
0
3
0
3
6
6
4
3
3
-
-
-
-
-
-
-
3
-
-
-
KM68B261A -7 KM68B261A -8
Unit
Min Max
-
-
-
-
7
-
-
3
1
0
0
3
KM68B261A -7 KM68B261A -8
Min Max
7
7
0
4
4
7
1
0
3.5
0
3
7
7
4
-
-
3.5
3.5
-
-
-
-
-
-
-
-
3.5
-
-
-
Min Max
8
-
-
3
1
0
0
3
Min Max
8
8
0
4.5
4.5
8
1
0
4
0
3
8
8
4
-
4
4
-
-
-
-
-
-
-
-
4
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
Rev 2.0
October-1994
KM68B261A BiCMOS SRAM
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE (/WE=VIH)
tRC
Address
tAA
tCO
/CS
/OE
Data Out
NOTES (READ CYCLE)
1.
/WE is high for read cycle.
2.
All read cycle timing is referenced from the last valid address to the first transition address.
3.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referenced to VOH or VOL levels.
4.
At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and
from device to device.
5.
Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not
100% tested.
6.
Device is continuously selected with /CS=VIL
7.
Address valid prior to coincident with /CS transition low.
8.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
and write cycle.
High-Z
t LZ (4,5)
tOE
tOLZ
Data Valid
t HZ(3,4,5)
tOHZ
tOH
TIMING WAVE FORM OF WRITE CYCLE(1) (/OE=Clock)
tRC
Address
/OE
/CS
/WE
Data In
Data Out
High-Z
tAS(4)
tOHZ(6)
tAW
tCW(3)
5
t WP(2)
High-Z(8)
tDW
Data Valid
t WR(5)
tDH
tOW
Rev 2.0
October-1994
KM68B261A BiCMOS SRAM
TIMING WAVE FORM OF WRITE CYCLE(2) ( /OE Low Fixed)
tWC
Address
tAW
/CS
/WE
Data In
Data Out
NOTES (WRITE CYCLE)
All write cycle timing is referenced from the last valid address to the first transition address.
1.
A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among
2.
/CS going low and /WE going low; A write ends at the earliest transition among /CS going high and /WE going
high. tWP is measured from the beginning of write to the end of write.
tCW is measured from the later of /CS going low to end of write.
3.
tAS is measured from the address valid to the beginning of write.
4.
tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or
5.
/WE going high.
If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs
6.
of opposite phase of the output must not be applied because bus contention can occur.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read
7.
and write cycle.
If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance
8.
state.
Dout is the read data of the new address.
9.
When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output
10.
should not be applied.
High-Z
tWHZ(6,7)
tCW(3)
tWP(2)tAS(4) tOH
tDW
Data Valid
High-Z
tDH
tOW
tWR(5)
(10) (9)
FUNCTIONAL DESCRIPTION
/CS /WE /OE Mode I/O Pin Supply Current
H
L
L
L
*Note : X means Don't Care.
X
H
H
L
X*
H
L
X
Not Select
Output Disable
Read
Write
High-Z
High-Z
DOUT
DIN
6
ISB, ISB1
ICC
ICC
ICC
Rev 2.0
October-1994
KM68B261A BiCMOS SRAM
PACKAGE DIMENSIONS
32-SOJ-300
#32
#1
21.36
Max.
0.841
20.96 ± 0.12
0.825 ± 0.005
+0.10
-0.05
0.43
0.017
+0.004
-0.002
0.71
0.028
+0.10
-0.05
+0.004
-0.002
1.27
0.050
8.51± 0.12
0.335 ± 0.005
Max.
3.76
0.148
0.95
0.037
0.10 Max.
0.004 Max.
7.62
0.300
0.69
0.027
Min.
Unit: mm / Inch
6.86±0.25
0.270±0.010
- 0.002
+ 0.004
- 0.05
+ 0.10
0.20
0.008
*Note : Do not include mold protrusion
7
Rev 2.0
October-1994
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