查询KM62256CL供应商
PRELIMINARY
KM62256C Family CMOS SRAM
32Kx8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTIONFEATURES
¡Ü
Process Technology : 0.7
¡Ü
Organization : 32Kx8
¡Ü
Power Supply Voltage : Single 5V
¡Ü
Low Data Retention Voltage : 2V(Min)
¡Ü
Three state output and TTL Compatible
¡Ü
Package Type : JEDEC Standard
§-
CMOS
¡¾
10%
28-DIP, 28-SOP, 28-TSOP I -Forward/Reverse
PRODUCT FAMILY
The KM62256C family is fabricated by SAMSUNG's advanced
CMOS process technology. The family can support various
operating temperature ranges and has various package types
for user flexibility of system design. The family also support low
data retention voltage for battery back-up operation with low
data retention current.
Product
Family
KM62256CL
Commercial (0~70¡É) 45*/55/70ns
KM62256CL-L
KM62256CLE
Extended (-25~85¡É) 70/100ns
KM62256CLE-L
KM62256CLI
Industrial (-40~85¡É) 70/100ns
KM62256CLI-L
* The parameter is measured with 30pF test load.
PIN DESCRIPTION
OE
A11
A9
WE
VCC
WE
A8
A13
A14
A12
A7
A6
A5
A4
A3
A3
A4
A5
A6
A7
A12
A14
VCC
A13
A8
A9
A11
OE
14
1
2
12
3
7
4
6
5
5
6
4
28-DIP
7
3
28-SOP
8
2
9
1
10
0
11
1
12
2
13
3
14
SS
VCC
28
WE
27
26
A13
A8
25
24
A9
23
A11
22
OE
21
A10
20
CS
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
Operating
Temperature.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28-TSOP
Type I - Forward
28-TSOP
Type I - Reverse
Speed
(ns)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
Power Dissipation
PKG Type
Standby
(ISB1, Max)
28-DIP, 28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
100
20
100
50
100
50
§Ë
§Ë
§Ë
§Ë
§Ë
§Ë
FUNCTIONAL BLOCK DIAGRAM
A0~A2, A9~11
X-Decoder
A3~A8,
A12~14
I/O1~8
Y-Decoder
Cell
Array
I/O Buffer
NameName Function
A0~A14 Address Inputs
WE Write Enable Input
CS Chip Select Input
OE Output Enable Input
I/O1~I/O8 Data Inputs/Outputs
Vcc Power(5V)
Vss Ground
Operating
(Icc2)
70mA
Control Logic
CS
WE,OE
Revision 3.0
April 1996
PRELIMINARY
Package Type : G=SOP, P=DIP, TG=TSOP Forward, RG=TSOP Reverse
KM62256C Family CMOS SRAM
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Product
(0~70¡É)
Extended Temp Products
(-25~85¡É)
Industrial Temp Products
(-40~85¡É)
Part Name Function Part Name Function Part Name Function
KM62256CLP-4
KM62256CLP-4L
KM62256CLP-5
KM62256CLP-5L
KM62256CLP-7
KM62256CLP-7L
KM62256CLG-4
KM62256CLG-4L
KM62256CLG-5
KM62256CLG-5L
KM62256CLG-7
KM62256CLG-7L
KM62256CLTG-4
KM62256CLTG-4L
KM62256CLTG-5
KM62256CLTG-5L
KM62256CLTG-7
KM62256CLTG-7L
KM62256CLRG-4
KM62256CLRG-4L
KM62256CLRG-5
KM62256CLRG-5L
KM62256CLRG-7
KM62256CLRG-7L
28-DIP, 45ns, L-pwr
28-DIP, 45ns, LL-pwr
28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 45ns, L-pwr
28-SOP, 45ns, LL-pwr
28-SOP, 50ns, L-pwr
28-SOP, 50ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 45ns, L-pwr
28-TSOP F, 45ns, LL-pwr
28-TSOP F, 55ns, L-pwr
28-TSOP F, 55ns, LL-pwr
28-TSOP F, 70ns, L-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 45ns, L-pwr
28-TSOP R, 45ns, LL-pwr
28-TSOP R, 55ns, L-pwr
28-TSOP R, 55ns, LL-pwr
28-TSOP R, 70ns, L-pwr
28-TSOP R, 70ns, LL-pwr
KM62256CLGE-7
KM62256CLGE-7L
KM62256CLGE-10
KM62256CLGE-10L
KM62256CLTGE-7
KM62256CLTGE-7L
KM62256CLTGE-10
KM62256CLTGE-10L
KM62256CLRGE-7
KM62256CLRGE-7L
KM62256CLRGE-10
KM62256CLRGE-10L
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
28-TSOP F, 70ns, L-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP F, 100ns, L-pwr
28-TSOP F, 100ns, LL-pwr
28-TSOP R, 70ns, L-pwr
28-TSOP R, 70ns, LL-pwr
28-TSOP R, 100ns, L-pwr
28-TSOP R, 100ns, LL-pwr
KM62256CLGI-7
KM62256CLGI-7L
KM62256CLGI-10
KM62256CLGI-10L
KM62256CLTGI-7
KM62256CLTGI-7L
KM62256CLTGI-10
KM62256CLTGI-10L
KM62256CLRGI-7
KM62256CLRGI-7L
KM62256CLRGI-10
KM62256CLRGI-10L
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
28-TSOP F, 70ns, L-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP F, 100ns, L-pwr
28-TSOP F, 100ns, LL-pwr
28-TSOP R, 70ns, L-pwr
28-TSOP R, 70ns, LL-pwr
28-TSOP R, 100ns, L-pwr
28-TSOP R, 100ns, LL-pwr
ORDERING INFORMATION
KM6 2 X 256 C X X X - XX X
L-Low Low Power, Blank-Low Power or High Power
Access Time : 4=45ns, 5=55ns, 7=70ns, 10=100ns
Operating temperature : Blank=Commercial, I=Industrial, E=Extended
L-Low Power or Low Low Power, Blank-High Power
Die Version : C=4th generation
Density : 256=256K bit
Blank=5V, V=3.0~3.6V, U=2.7~3.3V
Organization : 2=x8
SEC Standard SRAM
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W Storage temperature TSTG -65 to 150
TA 0 to 70
Operating Temperature
Soldering temperature and time TSOLDER 260¡É, 10sec (Lead Only) - -
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
-25 to 85
-40 to 85
¡É
¡É
¡É
¡É
KM62256CL/L-L
KM62256CLE/LE-L
KM62256CLI/LI-L
RECOMMENDED DC OPERATING CONDITIONS*
Item Symbol Min Typ** Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 - Vcc+0.5V V
Input low voltage VIL -0.5*** - 0.8 V
* 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified
2) Extended Product : TA=-25 to 85¡É, unless otherwise specified
3) Industrial Product : TA=-40 to 85¡É, unless otherwise specified
¡É
** TA=25
*** VIL(min)=-3.0V for ¡Â 50ns pulse width
CAPACITANCE* (f=1MHz, TA=25
Item Symbol Test Condition Min Max Unit
¡É
)
Input capacitance CIN VIN=0V - 6 pF
Input/Output capacitance CIO VIO=0V - 8 pF
* Capacitance is sampled not 100% tested
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
DC AND OPERATING CHARACTERISTICS
Item Symbol Test Conditions* Min Typ** Max Unit
Input leakage current ILI
Output leakage current ILO
Operating power supply current ICC
ICC1
Average operating current
ICC2
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH - - 1***** mA
KM62256CL
KM62256CL-L
Standby Current
(CMOS)
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
ISB1
VIN=Vss to Vcc
CS=VIH or WE=VIL
VIO=Vss to Vcc
CS=VIL, VIN=VIH or VIL, IIO=0mA
Cycle time=1§Á 100% duty
CS¡Â 0.2V, VIL¡Â 0.2V
¡Ã
VIN
Vcc -0.2V, IIO=0mA
Min cycle, 100% duty
CS=VIL, IIO=0mA
L(Low Power)
LL(L Low Power)
CS ¡ÃVcc-0.2V
VIN¡Ã 0.2V or
VIN ¡ÂVCC-0.2V
L(Low Power)
LL(L Low Power)
L(Low Power)
LL(L Low Power)
-1 - 1
-1 - 1 §Ë
- 7 15*** mA
- - 7**** mA
- - 70 mA
-
-
-
-
-
-
2
1
-
-
-
-
100
20
100
50
100
50
§Ë
§Ë
§Ë
§Ë
§Ë
§Ë
§Ë
* 1) Commercial Product : TA=0 to 70¡É, Vcc=5V¡¾10% unless otherwise specified
2) Extended Product : TA=-25 to 85¡É, Vcc=5V¡¾10% nless otherwise specified
3) Industrial Product : TA=-40 to 85¡É, Vcc=5V¡¾10% unless otherwise specified
¡É
** TA=25
*** 20mA for Extended and Industrial Products
****10mA for Extended and Industrial Products
*****2mA for Extended and Industrial Products
A.C CHARACTERISTICS
TEST CONDITIONS (1.Test Load and Test Input/Output Reference)*
Item Value Remark
Input pulse level 0.8 to 2.4V Input rising & falling time 5ns input and output reference voltage 1.5V -
Output load (See right)
* See DC Operating conditions
** Test load for 45ns commercial products
CL=100pF+1TTL -
**CL=30pF+1TTL -
CL*
* Including scope and jig capacitance
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
TEST CONDITIONS (2. Temperature and Vcc Conditions)
Product Family Temperature Power Supply(Vcc) Speed Bin Comments
KM62256CL/L-L 0~70
KM62256CLE/LE-L -25~85
KM62256CLI/LI-L -40~85
* The parameter is measured with 30pF test load
PARAMETER LIST FOR EACH SPEED BIN
Parameter List Symbol
¡É
¡É
¡É
5V ¡¾ 10% 45*/55/70ns Commercial
5V ¡¾ 10% 70/100ns Extended
5V ¡¾ 10% 70/100ns Industrial
Speed Bins
45ns* 55ns 70ns 100ns
Min Max Min Max Min Max Min Max
Units
Read Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
* The parameter is measured with 30pF test load
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
45 - 55 - 70 - 100 - ns
- 45 - 55 - 70 - 100 ns
- 45 - 55 - 70 - 100 ns
- 25 - 25 - 35 - 50 ns
10 - 10 - 10 - 10 - ns
5 - 5 - 5 - 5 - ns
0 20 0 20 0 30 0 35 ns
0 20 0 20 0 30 0 35 ns
5 - 5 - 5 - 5 - ns
45 - 55 - 70 - 100 - ns
45 - 45 - 60 - 80 - ns
0 - 0 - 0 - 0 - ns
45 - 45 - 60 - 80 - ns
40 - 40 - 50 - 60 - ns
0 - 0 - 0 - 0 - ns
0 20 0 20 0 25 0 35 ns
25 - 25 - 30 - 50 - ns
0 - 0 - 0 - 0 - ns
5 - 5 - 5 - 5 - ns
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
DATA RETENTION CHARACTERISTICS
Item Symbol Test Condition* Min Typ** Max Unit
Vcc for data retention VDR CS¡ÃVcc-0.2V 2.0 - 5.5 V
KM62256CL
KM62256CL-L
Data retention current IDR
Data retention set-up time
Recovery time
* 1) Commercial Product : Ta=0 to 70¡É, unless otherwise specified
2) Extended Product : TA=-25 to 85¡É, nless otherwise specified
3) Industrial Product : Ta=-40 to 85¡É, unless otherwise specified
¡É
** TA=25
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
tSDR
tRDR
DATA RETENTION WAVE FORM
1) CS Controlled
VCC
4.5V
tSDR
Vcc=3.0V
CS¡ÃVcc-0.2V
See data retention
waveform
Data Retention Mode
L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver
-
-
-
-
-
-
0 - 5 - -
1
0.5
-
-
-
-
tRDR
50
10
50
25
50
25
§Ë
ms
2.2V
VDR
CS
GND
CS¡Ã VCC - 0.2V
FUNCTIONAL DESCRIPTION
CS WE OE Mode I/O Pin Current Mode
H X X Power Down High-Z ISB ISB1
L H H Output Disable High-Z ICC
L H L Read Dout ICC
L L X Write Din ICC
* X means don't care
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled)
( CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Previous Data Valid Data Valid
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
tOLZ
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device.
High-Z
tLZ
Data Valid
tOHZ
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
WE
tAS(3)
Data in
tWP(1)
tDW tDH
Data Valid
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
tAS(3)
CS
WE
Data in
Data out High-Z
High-Z
tWHZ
tAW
tWC
tCW(2)
tWP(1)
tDW
Data Valid
Data Valid
tDH
tOW
tWR(4)
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end
at the earliest transition among CS going high and WE going high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)
#28
13.60 ¡¾ 0.20
0.535 ¡¾ 0.008
#1
1.65
( )
0.065
36.72
1.446
36.32 ¡¾ 0.20
1.430 ¡¾ 0.008
0.46 ¡¾ 0.10
0.018 ¡¾ 0.004
1.52 ¡¾ 0.10
0.060 ¡¾ 0.004
MAX
2.54
0.100
#15
#14
3.81 ¡¾ 0.20
0.150 ¡¾ 0.008
5.08
0.200
0.38
MIN
0.015
15.24
0.600
MAX
3.30 ¡¾ 0.30
0.130 ¡¾ 0.012
Units :Millimeters(Inches )
+0.10
0.25
-0.05
+0.004
0.010
-0.002
¡É
0~15
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0.89
( )
0.035
#28
#1 #14
18.69
MAX
0.736
18.29 ¡¾ 0.20
0.720 ¡¾ 0.008
0.41 ¡¾ 0.10
0.016 ¡¾ 0.004
1.27
0.050
#15
11.81 ¡¾ 0.30
0.465 ¡¾ 0.012
2.59 ¡¾ 0.20
0.102 ¡¾ 0.008
0.05
MIN
0.002
0.330 ¡¾ 0.008
3.00
0.118
8.38 ¡¾ 0.20
MAX
+0.10
0.15
-0.05
+0.004
0.006
-0.05
0.10 MAX
0.004 MAX
0~8
11.43
¡É
0.450
1.02 ¡¾ 0.20
0.040 ¡¾ 0.008
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family CMOS SRAM
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#1
0.55
0.0217
13.40 ¡¾ 0.20
0.528 ¡¾ 0.008
#28
#15#14
MAX
8.40
0.331
1.00 ¡¾ 0.10
0.039 ¡¾ 0.004
1.20
MAX
0.047
Units :Millimeters(Inches )
1.10 MAX
0.004 MAX
0.425
( )
0.017
8.00
0.315
0.05
MIN
0.002
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
13.40 ¡¾ 0.20
0.528 ¡¾ 0.008
11.80 ¡¾ 0.10
0.465 ¡¾ 0.004
#15#14
#28
0.15
0.006
0.50
( )
0.020
0.55
0.0217
0~8
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.25
TYP
0.010
¡É
0.45 ~0.75
0.018 ~0.030
#1
+0.10
-0.05
+0.004
-0.002
MAX
8.40
0.331
1.00 ¡¾ 0.10
0.039 ¡¾ 0.004
1.20
MAX
0.047
1.10 MAX
0.004 MAX
0.425
( )
0.017
8.00
0.315
0.05
MIN
0.002
Revision 3.0
April 1996
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