SAMSUNG KM6164000B Technical data

查询KM6164000BL-L供应商

KM6164000B Family

Document Title

256Kx16 bit Low Power CMOS Static RAM

Revision History

Revision No.

0.0

0.1

1.0

2.0

3.0

4.0

4.01

History

Initial draft

Revise

- Die name change ; A to B

Finalize

Revise

- Operating current update and release.
ICC(Read/Write) = 30/60 → 15/75mA
ICC1(Read/Write) = 30/60 → 15/75mA
ICC2 = 160 → 130mA

Revise

- Change datasheet format

- Remove ICC write value from table.

Revise

- Change test load at 55ns: 100pF → 50pF
Errarta correction

CMOS SRAM

Draft Data

June 28, 1996

September 19, 1996

December 17, 1996

February 17, 1997

February 17, 1998

June 22, 1998

August 8, 1998

Remark

Advance

Preliminary

Final

Final

Final

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 4.01

June 1998

KM6164000B Family

256Kx16 bit Low Power CMOS Static RAM

CMOS SRAM

FEATURES

• Process Technology : TFT

• Organization : 256Kx16

• Power Supply Voltage : 4.5~5.5V

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : 44-TSOP2-400F/R

GENERAL DESCRIPTION

The KM616V4000B families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and small package
types for user flexibility of system design. The families also
support low data retention voltage for battery back-up opera­tion with low data retention current.

PRODUCT FAMILY

Product Family Operating Temperature Vcc Range Speed(ns)

(ISB1, Max)

KM6164000BL-L Commercial(0~70°C) 4.5~5.5V

KM6164000BLI-L Industrial(-40~85°C) 4.5~5.5V 70/100 50µA

1. The parameter is measured with 50pF test load.

PIN DESCRIPTION

A4

1

A3

2

A2

3

A1

4

A0

5

CS

6

I/OI

7

I/O2

8

I/O3

9

I/O4

10
11

Vcc

44-TSOP2

12

Vss
I/O5
I/O6
I/O7
I/O8

WE
A17
A16
A15
A14
A13

13
14
15
16
17
18
19
20
21
22

Forward

Name Function Name Function

CS Chip Select Input Vcc Power
OE Output Enable Input Vss Ground

WE Write Enable Input UB Upper Byte(I/O9~16)

A0~A17 Address Inputs LB Lower Byte (I/O1~8)

I/O1~I/O16 Data Inputs/Outputs N.C No Connection

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O16

37

I/O15

36

I/O14

35

I/O13
Vss

34

Vcc

33

I/O12

32

I/O11

31

I/O10

30

I/O9

29

N.C

28

A8

27

A9

26

A10

25

A11

24

A12

23

I/O16
I/O15
I/O14
I/O13

Vss

Vcc
I/O12
I/O11
I/O10

I/O9

N.C

A10
A11

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38
37
36
35
34

44-TSOP2

33

Reverse

32
31
30
29
28

A8

27

A9

26
25
24

A12

23

1

A4

2

A3

3

A2

4

A1

5

A0

6

CS

7

I/OI

8

I/O2

9

I/O3

10

I/O4

11

Vcc

12

Vss

13

I/O5

14

I/O6

15

I/O7

16

I/O8

17

WE

18

A17

19

A16

20

A15

21

A14

22

A13

551)/70

FUNCTIONAL BLOCK DIAGRAM

A13
A14
A0
A1
A15
A16
A17
A2
A3
A4

I/O1~I/O8

I/O9~I/O16

WE
OE

Control
logic

UB
LB
CS

Power Dissipation

Standby

Operating

(ICC2, Max)

20µA

Clk gen.

Row
select

Data
cont

Data
cont

Data
cont

PKG Type

130mA 44-TSOP2-F/R

Precharge circuit.

Vcc
Vss

Memory array
1024 rows
256×16 columns

I/O Circuit

Column select

A8 A9 A10 A5 A6 A4A7

A12

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 4.01

June 1998

KM6164000B Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Product(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

KM6164000BLT-5L
KM6164000BLT-7L
KM6164000BLR-5L
KM6164000BLR-7L

44-TSOP2-F, 55ns, LL-pwr
44-TSOP2-F, 70ns, LL-pwr
44-TSOP2-R, 55ns, LL-pwr
44-TSOP2-R, 70ns, LL-pwr

KM6164000BLTI-7L
KM6164000BLTI-10L
KM6164000BLRI-7L
KM6164000BLRI-10L

44-TSOP2-F, 70ns, LL-pwr
44-TSOP2-F, 100ns, LL-pwr
44-TSOP2-R, 70ns, .LL-pwr
44-TSOP2-R, 100ns, LL-pwr

FUNCTIONAL DESCRIPTION

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

H

1)

X
L H H
L

1)

X
L L H L H Dout High-Z Lower Byte Read Active
L L H H L High-Z Dout Upper Byte Read Active
L L H L L Dout Dout Word Read Active
L
L
L

1. X means don′t care. (Must be in low or high state)

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

1)

X

High-Z High-Z Deselected Standby
High-Z High-Z Output Disabled Active

H H High-Z High-Z Output Disabled Active

L L H Din High-Z Lower Byte Write Active
L H L High-Z Din Upper Byte Write Active
L L L Din Din Word Write Active

ABSOLUTE MAXIMUM RATINGS

1)

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V ­Voltage on Vcc supply relative to Vss VCC -0.5 to7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

0 to 70 °C KM6164000BL-L

-40 to 85 °C KM6164000BLI-L

Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

3

Revision 4.01

June 1998

KM6164000B Family

CMOS SRAM

-0.5

1)

2)

Vcc+0.5

3)

- 0.8 V

V

RECOMMENDED DC OPERATING CONDITIONS

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 ­Input low voltage VIL

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : VCC+3.0V in case of pulse width ≤ 30ns

3. Undershoot : -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE

Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

1)

(f=1MHz, TA=25°C)

Item Symbol Test Condition Min Max Unit

DC AND OPERATING CHARACTERISTICS

Item

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 15 mA

Average operating current

Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current (TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 3 mA

Standby Current(CMOS)

1. Industrial Product = 50µA

Symbol

Cycle time=1µs, 100% duty, IIO=0mA

ICC1

CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

ICC2

ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - -

Test Conditions

Read - - 15
Write - - 75

Min Typ Max Unit

- - 130 mA

1)

20

mA

µA

4

Revision 4.01

June 1998

KM6164000B Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL

CL=50pF+1TTL

1)

CL

1. Including scope and jig capacitance

AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product : TA=0 to 70°C, Industrial product : TA=-40 to 85°C)

Speed Bins

Read

Write

Parameter List Symbol

Read cycle time tRC 55 - 70 - 100 - ns
Address access time tAA - 55 - 70 - 100 ns
Chip select to output tCO - 55 - 70 - 100 ns
Output enable to valid output tOE - 25 - 35 - 50 ns
Chip select to low-Z output tLZ 10 - 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - 5 - ns
UB, LB enable to low-Z output tBLZ 5 - 5 - 5 - ns
Chip disable to high-Z output tHZ 0 20 0 25 0 30 ns
OE disable to high-Z output tOHZ 0 20 0 25 0 30 ns
UB, LB disable to high-Z output tBHZ 0 20 0 25 0 30 ns
Output hold from address change tOH 10 - 10 - 10 - ns
LB, UB valid to data output tBA - 25 - 35 - 50 ns
Write cycle time tWC 55 - 70 - 100 - ns
Chip select to end of write tCW 45 - 60 - 80 - ns
Address set-up time tAS 0 - 0 - 0 - ns
Address valid to end of write tAW 45 - 60 - 80 - ns
Write pulse width tWP 45 - 55 - 70 - ns
Write recovery time tWR 0 - 0 - 0 - ns
Write to output high-Z tWHZ 0 20 0 25 0 30 ns
Data to write time overlap tDW 25 - 30 - 40 - ns
Data hold from write time tDH 0 - 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - 5 - ns
LB, UB valid to end of write tBW 45 - 60 - - 80 ns

55ns 70ns 100ns

Min Max Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 5.5 V
Data retention current IDR Vcc=3.0V - ­Data retention set-up time tSDR
Recovery time tRDR 5 - -

1. Industrial Product : 20µA

See data retention waveform

0 - -

5

1)

15

Revision 4.01

June 1998

µA
ms

KM6164000B Family

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

UB, LB

tAA

tRC

tAA

tCO

tBA

CMOS SRAM

Data Valid

tOH

tHZ

OE

tBLZ

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

High-Z

tLZ

tOE

tOLZ

Data Valid

tBHZ

tOHZ

6

Revision 4.01

June 1998

KM6164000B Family

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CMOS SRAM

tWC

CS

UB, LB

WE

Data in

Data out

Data Undefined

tAS(3)

High-Z

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

tAS(3)

CS

UB, LB

tWHZ

tAW

tWC

tCW(2)

tAW

tCW(2)

tBW

tBW

tWP(1)

tWP(1)

tDW

Data Valid

tWR(4)

tDH

High-Z

tOW

tWR(4)

WE

Data in

Data out

High-Z

tDW

Data Valid

7

tDH

High-Z

Revision 4.01

June 1998

KM6164000B Family

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

Address

CS

UB, LB

WE

Data in

tAS(3)

tWC

tCW(2)

tAW

tBW

tWP(1)

tDW

Data Valid

CMOS SRAM

tWR(4)

tDH

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

High-Z

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

CS
GND

tSDR

Data Retention Mode

CS≥VCC - 0.2V

tRDR

8

Revision 4.01

June 1998

KM6164000B Family

CMOS SRAM

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#44 #23

#1

18.81

MAX.

0.741

18.41±0.10

0.725±0.004

0.805

( )

0.032

0.35±0.10

0.014±0.004

0.80

0.0315

#22

MIN.

0.05

0.002

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

1.20

0.047

MAX.

0.004

0.10

MAX

10.16

5

1

.

0

0

.

0

0.25

( )

0.010

0.400

0

1

.

0

+

5

0

.

0

­0

0

.

0

+

0

0

.

6

0

0

-

Unit : millimeter(inch)

0~8°

( )

4

2

0.45 ~0.75

0.018 ~ 0.030

0.50

0.020

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

#1

#44 #23

18.81

MAX.

0.741

18.41±0.10

0.725±0.004

0.805

( )

0.032

0.35±0.10

0.014±0.004

0.80

0.0315

#22

MIN.

0.05

0.002

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

1.20

0.047

MAX.

0.10

0.004

MAX

10.16

1

.

0

0

.

0

0.25

( )

0.010

0.400

0

1

.

0

+

0

.

0

-

5

0

.

0

+

0

.

6

0

0

-

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

5

4

0

2

0

9

Revision 4.01

June 1998