Samsung KC74125B Datasheet
KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA
1
INTRODUCTION
The KC74125B is an interline transfer CCD area image
sensor developed for EIA 1/4 inch optical format video
cameras, surveillance cameras, object detectors and image
pattern recognizers. High sensitivity is achieved through onchip micro lenses and HAD (Hole Accumulated Diode)
photosensors.
This chip features a field integration read out system and an
electronic shutter with variable charge storage time.
FEATURES
• High Sensitivity
• Optical Size 1/4 inch Format
• No adjust Substrate Bias
• Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10,000sec)
• Low Dark Current
• Horizontal Register 3.3 to 5.0V Drive
• 14pin Ceramic DIP Package
• Field Integration Read Out System
• No DC Bias on Reset Gate
STRUCTURE
• Number of Total Pixels: 537(H) × 505(V)
• Number of Effective Pixels: 510(H) × 492(V)
• Chip Size: 4.83mm(H) × 4.04mm(V)
• Unit Pixel Size: 7.15µm(H) × 5.55µm(V)
• Optical Blacks & Dummies: Refer to Figure Below
Vertical 1 Line (Even Field Only)
14Pin Cer DIP
ORDERING INFORMATION
Device Package Operating
KC74125B 14Pin Cer DIP -10 °C ~ +60 °C
16 2 510 25
1 492 12
V-CCD
OUTP UT
Du mmy Pixels
Optical Black Pixel s
Effective Pixel s
E ffective
Imagi ng
A rea
H-CCD
1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B
2
BLOCK DIAGRAM
PIN DESCRIPTION
Figure 1. Block Diagram
Table 1. Pin Description
Pin Symbol Description Pin Symbol Description
1
Φ
V4
Vertical register transfer clock 8
V
DD
Signal output
2
Φ
V3
Vertical register transfer clock 9 GND GND
3
Φ
V2
Vertical register transfer clock 10
Φ
SUB
Substrate clock
4
Φ
V1
Vertical register transfer clock 11
V
L
Protection transistor bias
5 NC No connection 12
Φ
RG
Reset gate clock
6 GND Ground 13
Φ
H1
Horizontal register transfer clock
7
V
OUT
Signal output 14
Φ
H2
Horizontal register transfer clock
7
V
OUT
6 5 4 3 2 1
8 9 10 11 12 13 14
GND NC
Φ
V1
Φ
V2
Φ
V3
Φ
V4
V
DD
V
L
GND
Φ
H1
Φ
H2
Φ
RG
Φ
SUB
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Horizontal Shift Register CCD
(Top View)
KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA
3
ABSOLUTE MAXIMUM RATINGS
(NOTE)
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
Table 2. Absolute Maximum Ratings
Characteristics Symbols Min. Max. Unit
Substrate voltage SUB - GND -0.3 40 V
VDD, V
OUT
- SUB
-40 10 V
Vertical clock input voltage ΦV1, ΦV3, - GND
-0.3 30 V
ΦV2, Φ
V4
- GND
-0.3 17 V
ΦV1, ΦV3, - V
L
-0.3 30 V
ΦV2, Φ
V4
- VL
-0.3 17 V
ΦV1, ΦV2, ΦV3, Φ
V4
- SUB
-40 10 V
Horizontal clock input voltage ΦH1, ΦH2 - V
L
-0.3 7 V
ΦH1, ΦH2 - SUB
-30 7 V
Voltage difference between vertical and
horizontal clock input pins
ΦV1, ΦV2, ΦV3, Φ
V4
15 V
ΦH1, Φ
H2
16 V
ΦH1, ΦH2 - Φ
V4
-17 16 V
Output clock input voltage ΦRG - GND
-0.3 16 V
ΦRG - SUB
-40 16 V
Protection circuit bias voltage
VL - SUB
-40 10 V
Operating temperature
T
OP
-10 60 °C
Storage temperature
T
STG
-30 80 °C
1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B
4
DC CHARACTERISTICS
CLOCK VOLTAGE CONDITIONS
Table 3. DC Characteristics
Item Symbol Min. Typ. Max. Unit
Output stage drain bias
V
DD
14.55 15.0 15.45 V
Protection circuit bias voltage
V
L
The lowest vertical clock level
Output stage drain current
I
DD
5 mA
Table 4. Clock Voltage Conditions
Item Symbol Min. Typ. Max. Unit Remark
Read-out clock voltage
V
VH1
, V
VH3
14.55 15.0 15.45 V High level
Vertical transfer clock voltage V
VM1
~ V
VM4
-0.2 0.0 0.2 V Middle
V
VL1
~ V
VL4
-8.0 -7.5 -7.0 V Low
Horizontal transfer clock voltage V
HH1
, V
HH2
3.0 5.0 5.25 V High
V
HL1
, V
HL2
-0.05 0.0 0.05 V Low
Charge reset clock voltage V
RGH
4.75 5.0 5.25 V High
V
RGL
-0.2 0.0 0.2 V Low
Substrate clock voltage
V
ΦSUB
21.5 22.5 23.5 V Shutter
KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA
5
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V
100%
90%
10%
0%
V
VH1,VVH3
tr twh tf
V V H 1
V
VH
V V H H
V
VL L
V VL
V V L 1
V
VL H
V V H L
V
V H L
V V H H
¥Õ
V 1
V
VH
V
VHL
V VH H
V
VH H
V
VHL
V V H4
V
VL
V VL H
V
VL L
V
VL 4
¥Õ
V 4
V V HH V VHH
V
VH
V
VHL
V
VHL
V VH2
V
VL
V VL L
V VL H
V VL 2
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V 2
V VL 3
V VHH
V VL
V V HL
V V HL
V
VH3
V
VH H
V
VH
V VL H
V
VL L
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V 3
VVH= (V
VH 1
+ V
VH 2
)/2
VV L = (V V L 3 + VV L 4)/ 2
V¥ÕV= V
VH n
- V
VL n (n = 1~4)
V
VH H
= VVH+ 0.3V
VVH L = VV H - 0. 3 V
V
VL H
= V
V L
+ 0.3V
V
VL L
=
V
V L
-0.3V
1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B
6
Horizontal Transfer Clock Waveform Diagram
Reset Gate Clock Waveform Diagram
V
RGLH
is the maximum value and V
RGLL
the minimum value of the coupling waveform in the period from Point A in
the diagram about to RG rise
V
RGL
= (V
RGLH
+ V
RGLL
)/2, V
FRG
= V
RGH
- V
RGL
Substrate Clock Waveform
90%
10%
tr twh
tf
twl
V¥Õ
H
V
HL
V
RGL
+ 0.5V
twl
Point A
twh t ftr
V
RGH
V
RGL
RG waveform
V
RGLH
V
RGLL
¥Õ
H1 waveform
10%
V
¥Õ
RG
100%
90%
10%
0%
twhtr tf
V
¥Õ
SU B
V
SU B
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