Samsung KB8825 Datasheet

Final version ( 99.4.30 )

1.1GHZ DUAL PLL KB8825

INTRODUCTION

16−TSSOP−0044

The KB8825 is a high performance dual frequency synthesizer with two integrated high frequency pre-scalers for RF operation up to 1.1 GHz. The KB8825 is composed of modulus pre-scalers providing 64 and 66, no dead-zone PFD, selectable charge pump current, selectable power down mode circuits, lock detector output, and loop filter’s time constant switch. It is fabricated using the ASP5HB Bi-CMOS process and is available 16-TSSOP with surface mount plastic packaging. Serial data is transferred into the KB8825 via three-wire interface (CK, DATA, EN).

FEATURES

• Two systems for receiver and transmitter

• Very low operating current consumption: Icc = Typ. 5.5mA @ 3.0V

• Low operating power supply voltage : 2.2 ~ 5.5V ( 200MHz ~ 550MHz Operating )

2.7 ~ 3.6V ( 550MHz ~ 1.1GHz Operating )

• Modulus pre-scaler: 64 / 66

• No dead-zone PFD

• Colpitt type local oscillation

• Selectable charge pump current

• Selectable power down mode

• TSSOP 16-pin package (0.65 mm pitch)

ORDERING INFORMATION

Device Package Operating Temperature

+KB8825 16−TSSOP−0044 −30 °C to + 85 °C

+: New product

APPLICATIONS

• Cordless telephone systems

• Portable wireless communications (PCS)

• Wireless Local Area Networks (WLANs)

• Other wireless communication systems

Final version ( 99.4.30 )

KB8825 1.1GHZ DUAL PLL

BLOCK DIAGRAM

Fin1

CP1

GND

DATA

PIN CONFIGURATION

Pre_Amp 1/2

Charge

Pump

Phase

Detector

Lock

Detector

Control

Circuit

Prescaler

32, 33

Buffer

Channel 1

Program-

able

Divider

17 12

Prescaler

32, 33

Buffer

Channel 2

Program-

able

Divider

Reference

Divider

1/2 Pre_Amp 1615Fin2

Charge

Pump

Phase

Detector

Switch

Local

OSC

1/2

Buffer

CP2

GND

OSCI

OSCO

Fin1

CP1

GND

DATA

KB8825

16TSSOP

Fin2

CP2

GND

OSCI

OSCO

Final version ( 99.4.30 )

1.1GHZ DUAL PLL KB8825

PIN DESCRIPTION

Pin No. Symbol I/O Description

1 Fin1 I Input terminal of channel 1 RF signal. 2, 15 Vcc − Power supply voltage input. PIN2 and PIN15 are connected together. 3 CP1 O Output terminal of channel 1 charge pump. Charge pump is constant current output

circuit, and output current is selected by input serial data. 4, 13 GND − Terminal of GND. PIN4 and PIN13 are connected in common. 5 LD O Output terminal of lock detection. It is the open drain output. 6 CK I Input terminal of clock. 7 DATA I Input terminal of data. 8 EN I Input terminal of enable signal. 9 BO O Output terminal of buffer amplifier. The signal of local oscillation is output through the

buffer amplifier. 10 OSCO O Output terminal of local oscillation signal. 11 OSCI I Input terminal of local oscillation signal. In case of external input, connecting it to this

terminal. 12 SW O Switchover terminal for the time constant of loop filter. It is an open drain output. If

you don’t switch the time constant of loop filter, general output is available. 14 CP2 0 Output terminal of channel 2 charge pump. Charge pump is a constant current output

circuit, and the output current is selected by input serial data. 16 Fin2 I Input terminal of channel 2 RF signal.

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Power Supply Voltage Vcc 6 V Power Dissipation P Operating temperature T Storage temperature T

Take care ! ESD sensitive device

D OPR STG

600 mW

−30 ~ + 85 °C

−55~ +150 °C

Final version ( 99.4.30 )

KB8825 1.1GHZ DUAL PLL

ELECTRICAL CHARACTERISTICS

(Ta = 25°C, VCC = 3V, unless otherwise specified)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Operating Power supply voltage

Operating current consumption

Standby current I

Fin1=Fin2= 200MHz ~ 550MHz 2.2 3.0 5.5 V

Fin1=Fin2= 550MHz ~ 1.1GHz 2.7 3.0 3.6 V Fin1=Fin2=1.1GHz/ -5dBm input 3.5 5.5 7.5 mA

Standby mode − 0 10 µA

Fin operating frequency Fin Fin1 = Fin2 = − 5dBm 200 − 1100 MHz

Vcc=2.2V − 15 − 0

Fin1 = Fin2 = 200MHz

Vcc=3.0V − 15 − 0 Vcc=5.5V − 10 − 0 Vcc=2.2V −15 − 0

Fin input sensitivity Fin

Fin1 = Fin2 = 550MHz

Vcc=3.0V −15 − 0

dBm

Vcc=5.5V − 10 − 0 Vcc=2.7V − 10 − 0

Fin1 = Fin2 = 1.1GHz

Vcc=3.0V − 10 − 0 Vcc=3.6V − 10 − 0

OSCI operating frequency F

osc

= 0dBm, sinewave

Fin

5 - 25 MHz

Vcc=2.2V − 10 0 5

OSCI input voltage

Serial data input high voltage (CK, DATA, EN)

Serial data input low voltage (CK, DATA, EN)

Charge pump output current

Charge pump leakage I

CP1

CP2

CP3

CP4

CPL

= 10MHz

osc

Vcc=3.0V − 10 0 5 Vcc=5.5V 0 - 5

osc

= 20MHz

Vcc=2.2V − 10 0 5 Vcc=3.0V − 10 0 5 Vcc=5.5V − 5 0 5

−

= 2.2 to 5.5V

0.4

− − V

− − 0.4 V

CP1 = 0, CP2 = 0 VCP = 1.5 V – ± 100 − µA CP1 = 0, CP2 = 1 VCP = 1.5V – ± 200 − µA CP1 = 1, CP2 = 0 VCP = 1.5V − ± 400 − µA CP1 = 1, CP2 = 1 VCP = 1.5V − ± 800 − µA Standby mode, Vcp = 1.5V −1 − +1 µA

dBm

Final version ( 99.4.30 )

1.1GHZ DUAL PLL KB8825

FUNCTIONAL DESCRIPTIONS

SERIAL DATA INPUT AND TIMING

CK (Pin6), DATA (Pin7), EN (Pin8) terminals in KB8825 are used for MICOM (MPU) serial data interface (MSB: 1st input data; LSB: Last input data). Serial data controls the programmable reference divider, programmable divider (CH1), programmable divider (CH2), and control latch separately by means of group code. Binary serial data is entered via the DATA pin.

One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from errors caused by noise, etc.

< Notice >

1. When power supply of KB8825 is disconnected, CLK, DATA, EN port from MCU should be pulled low.

2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data.

3. When power goes up first, control data should be entered earlier than N1 and N2 counter data.

≥

0.2us

≥

0.1us

≥

0.2us

LSB MSB

≥ ≥

0.1us 0.2us

≥

0.2us

≥

DATA

≥

1us 0.2us

MSB

N1 (R1) N2 (R2) N3 (R3) N16 (R11) N17 (R12) GC2 GC1

Figure 1.

NOTE: Start data input with MSB first

SERIAL DATA GROUP AND GROUP CODE

The IC can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit group code given below.

Serial Bits Group Location

GC1 (LSB) GC2 (LSB-1)

0 0 Control Latch 0 1 Ch 1 N Latch 1 0 Ch 2 N Latch 1 1 OSC R Latch

Final version ( 99.4.30 )

KB8825 1.1GHZ DUAL PLL

CONTROL LATCH

The control register executes the following functions:

• Mode selection (H: test mode, L: normal mode)

• Charge pump’s polarity and output current selection for each channel.

• Output state selection for Lock Detector.

• Standby control of each channel and reference divider.

• ON / OFF control in filter switch.

CH1 CH2MSB

T CP CP1 CP2 CP1SB1 SB2CP2 SBR LD1 LD2 SW

LSB

GC2

"0"

Group Code

GC1

"0"

Figure 2.

Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Name T CP CP1 CP2 SB1 CP1 CP2 Description test mode charge

pump out polarity

channel 1 charge pump output current

channel 1 standby

channel 2 charge pump output current

Bit Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Name SB2 SBR LD1 LD2 SW GC2 GC1 Description channel 2

standby

reference divider standby

lock detector control 1

lock detector control 2

filter switch group code

“0”

group code “0”

Final version ( 99.4.30 )

1.1GHZ DUAL PLL KB8825

CHARGE PUMP OUTPUT POLARITY (CP)

In normal operation, the CP should be “0”. In reverse operation, the CP should be “1”.

Depending upon VCO characteristics, CP should be set accordingly; When VCO characteristics are like (1), CP should be set low When VCO characteristics are like (2), CP should be set high.

CHARGE PUMP OUTPUT CURRENT (CP1, CP2)

The KB8825 includes a constant current output type charge pump circuit. Output current is varied according to control bit “CP1” and “CP2”. In order to get high speed lock-up, select the best charge pump output current.

Control Bit Charge Pump

CP1 CP2

Output Current

0 0 ±100 µA 0 1 ±200 µA 1 0 ±400 µA 1 1 ±800 µA

VCO

Output

Frequency

VCO Characteristics

(1)

(2)

VCO Input Voltage

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