DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
KB2147 |
DEFLECTION PROCESSOR |
|
|
42-SDIP-600 |
The KB2147 is a monolithic integrated circuit assembled in a |
|
42 pins shrunk dual in line plastic package. |
|
The goal of this IC is to control all the functions related to the |
|
horizontal and vertical deflection in multimodes or multisync |
|
monitors. |
|
FUNCTIONS |
|
• Positive or Negative sync polarities |
|
• Auto-sync horizontal processing |
|
• H-PLL lock/unlock identification |
|
•Auto-sync Vertical processing
•East/West signal processing block
•B+ controller
•Safety blanking output
(HORIZONTAL)
•Dual Pll concept
•Self-adaptative (30 to 70kHz)
•X-ray protection input
•DC adjustable duty-cycle
•Internal 1st PLL lock/unlock information
•Wide range DC controlled H-position
•ON/OFF switch (for PWR management)
•Two H-drive polarities
(VERTICAL)
•Vertical ramp generator
•50 to 120Hz AGC Loop
•DC controlled V-amp, V-pos, S-amp & S-centring
•ON/OFF Switch
(B+ REGULATOR)
•Internal PWM generator for B+ current mode step-up conveter
•DC adjustable B+ voltage
•Output pulse synchronised on horizontal frequency
•Internal MAX current limitation
ORDERING INFORMATION
Device |
Package |
Operation Temperature |
|
|
|
KB2147 |
42-SDIP |
0 °C ~ 70 °C |
|
|
|
(GENERAL)
•Accept Positive or Negative Horizontal & Vertical sync polarities
•Separate H & V TTL input
•Safety blanking output
(EWPCC)
•Vertical parabola generator with DC
•controlled keystone & amplitude
1
KB2147 |
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
|
|
|
|
PLL1NHIB |
H-POS |
PLL1F |
R0 |
C0 |
FH-MIN |
HLOCK-CAP |
HFLY |
PLL2C |
H-DUTY |
|
H-OUTEM |
H-OUTCOL |
|
|
|
|
|
|
35 |
15 |
12 |
11 |
10 |
14 |
13 |
3 |
1 |
2 |
|
20 |
21 |
|
|
HSYNC |
17 |
INPUT |
|
1st PHASE |
|
|
VCO |
|
|
2nd PHASE |
|
PHASE |
|
OUTPUT |
|
|
||
INTERFACE |
COMP |
|
|
|
|
COMP |
|
SHAPER |
|
BUTTER |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
23 |
SBLKOUT |
XRAY-IN |
16 |
|
|
|
|
|
|
|
|
LOCK |
|
|
|
|
|
|
39 |
B+ADJ |
|
|
|
|
|
|
|
DETECT |
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
VREF |
|
|
42 |
I SENSE |
|
HREF |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
H-VREF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
HGND |
4 |
|
|
|
|
|
|
|
|
|
|
+ |
|
- |
R |
22 |
B+OUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
+ |
||||||
|
|
|
|
|
|
|
SAFETY |
|
|
EA |
|
|||||||
|
|
|
|
BANDGAP |
|
|
|
|
|
- |
|
|
|
|
|
|||
|
|
|
|
|
|
|
PROCESSOR |
|
|
|
|
|
|
|
||||
VREF |
26 |
|
|
|
|
|
|
|
|
|
|
|
S |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
24 |
V-VREF |
|
|
|
|
|
|
VCC |
OUTPUT |
|
|
|
|
|
|
|
|
VGND |
|
|
|
|
|
|
|
|
|
|
|
|
41 |
COMP |
||||
|
|
|
|
|
|
|
|
INHIBITION |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
40 |
REGIN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PARABOLA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GENERATOR |
|
|
|
||
VSYNC |
34 |
INPUT |
|
|
VERTICAL |
|
|
S |
|
|
|
|
|
|
|
|
|
|
INTERFACE |
|
OSCILLATOR |
|
CORRECTION |
|
|
|
|
|
|
|
36 |
E/WOUT |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
19 |
18 |
|
27 |
25 |
|
29 |
28 |
33 |
31 |
30 |
32 |
38 |
37 |
|
|
|
|
|
GND |
VCC |
|
VCAP |
VAGCCAP |
|
VS-CENT |
VS-AMP |
V-POS |
V-AMP |
VOUT |
V DCOUT |
KEYST |
EW-AMP |
|
|
|
2
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
KB2147 |
PIN CONFIGURATIONS
1PLL2C
2H-DUTY
3HFLY
4HGND
5HREF
6NC
7NC
8NC
9NC
10C0
11R0
12PLL1F
13HLOCK-CAP
14FH-MIN
15H-POS
16XRAY-IN
17HSYNC
18
VCC
19GND
20H-OUTEM
21H-OUTCOL
KB2147
I-SENSE 42 COMP 41
REGIN 40
B+ ADJ 39
KEYST 38
E/W-AMP 37
E/WOUT 36
PLL1-INHIB 35
VSYNC 34
V-POS 33
V-DCOUT 32
V-AMP 31
VOUT 30
VS-CENT 29
VS-AMP 28
VCAP 27
VREF 26
VAGCCAP 25
VGND 24
SBLK-OUT 23
B+ OUT 22
3
KB2147 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PIN DESCRIPTION
|
|
Table 1. Pin Description |
|
|
|
Pin No |
Pin Name |
Description |
|
|
|
1 |
PLL2C |
Second PLL Loop Filter |
|
|
|
2 |
H-DUTY |
DC Control of Horizontal Drive Output Pulse Duty-cycle. |
|
|
If this pin grounded, the horizontal and vertical outputs are inhibited. By connecting a |
|
|
capacitor on the this pin a soft-start function may be realized on h-drive output. |
|
|
|
3 |
H-FLY |
Horizontal Flyback Input (Positive Polarity) |
|
|
|
4 |
H-GND |
Horizontal section ground. Must be connected only to components related to H |
|
|
blocks. |
|
|
|
5 |
H-REF |
Horizontal section reference voltage. Must be filtered by capacitor to pin 4. |
|
|
|
6 |
NC |
|
|
|
|
7 |
NC |
|
|
|
|
8 |
NC |
|
|
|
|
9 |
NC |
|
|
|
|
10 |
C0 |
Horizontal Oscillator Capacitor. To be connected to pin 4. |
|
|
|
11 |
R0 |
Horizontal Oscillator Resistor. To be connected to pin 4. |
|
|
|
12 |
PLL1F |
First PLL Loop filter. To be connected to pin 4. |
|
|
|
13 |
HLOCK-CAP |
First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the freqency |
|
|
change detected on pin 13. When frequency is changing, a blanking pulse is |
|
|
generated on pin 23, the duration of this pulse is proportionnal to the capacitor on |
|
|
pin 13. To be connected to pin 4. |
|
|
|
14 |
FH-MIN |
DC Control for free running frequency setting. Comming from DAC output or DC |
|
|
voltage generated by a resistor bridge connected between pin 5 and 4. |
|
|
|
15 |
H-POS |
DC Control for Horizontal Centering |
|
|
|
16 |
XRAY-IN |
X-RAY Protection input (with Internal latch function) |
|
|
|
17 |
H-SYNC |
TTL Horizontal Sync Input |
|
|
|
18 |
Vcc |
Supply Voltage (12V Typical) |
|
|
|
19 |
GND |
Ground |
|
|
|
20 |
H-OUTEM |
Horizontal Drive Output (emiter of internal transistor) |
|
|
|
21 |
H-OUTCOL |
Horizontal Drive Output (open collector of internal transistor) |
|
|
|
22 |
B+OUT |
B+ PWM Regulator output |
|
|
|
23 |
SBLK |
Safety Blanking output. Activated during frequency changes, when X-RAY input is |
|
OUT |
triggered or when VS is too low. |
|
|
|
24 |
VGND |
Vertical Section Signal Ground |
|
|
|
25 |
VAGCCAP |
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator |
|
|
|
26 |
VREF |
Vertical Section Reference Voltage |
4
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
KB2147 |
|||
|
|
Table 1. Pin Description (Continued) |
|
|
|
|
|
|
|
Pin No |
Pin Name |
Description |
|
|
|
|
|
|
|
27 |
VCAP |
Vertical Sawtooth Generator Capacitor |
|
|
|
|
|
|
|
28 |
VS-AMP |
DC Control of Vertical S-Shape Amplitude |
|
|
|
|
|
|
|
29 |
VS-CENT |
DC Control of Vertical S-Centering |
|
|
|
|
|
||
30 |
V-OUT |
Vertical Ramp Output (with frequency independant amplitude and S-Correction) |
||
|
|
|
|
|
31 |
V-AMP |
DC Control of Vertical Amplitude Adjustment |
|
|
|
|
|
||
32 |
VDCOUT |
Vertical Position Reference Voltage Output Temperature matched with V-AMP |
||
|
|
output |
|
|
|
|
|
|
|
33 |
V-POS |
DC Control of Vertical Position Adjustment |
|
|
|
|
|
|
|
34 |
V-SYNC |
Vertical TTL Sync Input |
|
|
|
|
|
||
35 |
PLL1INHIB |
TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input |
||
|
|
signal) |
|
|
|
|
|
|
|
36 |
E/WOUT |
East/West Pincushion Correction Parabola Output |
|
|
|
|
|
|
|
37 |
E/W-AMP |
DC Control East/West Pincushion Correction Amplitude |
|
|
|
|
|
|
|
38 |
KEYST |
DC Control of Keystone Correction |
|
|
|
|
|
|
|
39 |
B+ADJ |
DC Control of B+ Adjustment |
|
|
|
|
|
|
|
40 |
REGIN |
Regulation Input of B+ Control Loop |
|
|
|
|
|
|
|
41 |
COMP |
B+ Error Amplifier Output for Frequency Compensation and Gain Setting |
|
|
|
|
|
|
|
42 |
ISENSE |
Sensing of External B+ Switching Transistor Emitter Current |
|
|
5