Datasheet K9F1G08R0A Datasheet (SAMSUNG)

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K9F1G08R0A
K9F1G08U0A

K9K2G08U1A FLASH MEMORY

Document Title

128M x 8 Bit / 256M x 8 Bit NAND Flash Memory

Revision History

Revision No

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

History

1. Initial issue

1. The tADL(Address to Data Loading Time) is added.

- tADL Minimum 100ns (Page 11, 23~26)

-

tADL is the time from the WE rising edge of final address cycle

to the WE

2. Added Addressing method for program operation

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

1. PKG(TSOP1, WSOP1) Dimension Change

1. Technical note is changed

2. Notes of AC timing characteristics are added

3. The description of Copy-back program is changed

4. Voltage range is changed

-1.7V~1.95V -> 1.65V~1.95V

5. Note2 of Command Sets is added

1. CE

1. The value of tREA for 3.3V device is changed.(18ns->20ns)

2. EDO mode is added.

1. The flow chart to creat the initial invalid block table is cahnged.

rising edge of first data cycle at program operation.

access time : 23ns->35ns (p.11)

Draft Date

Aug. 24. 2003
Jan. 27. 2004

Apr. 23. 2004

May. 19. 2004

Jan. 21. 2005

Feb. 14. 2005

May. 24. 2005

May 6. 2005

Remark

Advance
Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.

1

K9F1G08R0A
K9F1G08U0A

K9K2G08U1A FLASH MEMORY

128M x 8 Bit /256M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F1G08R0A 1.65 ~ 1.95V

K9F1G08U0A-Y,P

K9F1G08U0A-V,F WSOP1

K9K2G08U1A-I 52-ULGA

2.7 ~ 3.6V

FEATURES

• Voltage Supply

-1.8V device(K9F1G08R0A): 1.65V~1.95V

-3.3V device(K9F1G08U0A): 2.7 V ~3.6 V

• Organization

- Memory Cell Array : (128M + 4,096K)bit x 8bit

- Data Register : (2K + 64)bit x8bit

- Cache Register : (2K + 64)bit x8bit

• Automatic Program and Erase

- Page Program : (2K + 64)Byte

- Block Erase : (128K + 4K)Byte

• Page Read Operation

- Page Size : 2K-Byte

- Random Read : 25µs(Max.)

- Serial Access : 30ns(Min.) - 3.3v device
50ns(Min.) -1.8v device

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Cache Program Operation for High Performance Program

• Intelligent Copy-Back Operation

• Unique ID for Copyright Protection

• Package :

- K9F1G08U0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1G08U0A-VIB0
48 - Pin WSOP I (12X17X0.7mm)

- K9F1G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1G08U0A-FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0A-V,F(WSOPI ) is the same device as
K9F1G08U0A-Y,P(TSOP1) except package type.

- K9K2G08U1A-ICB0/IIB0
52-ULGA (12X17X0.65mm)

X8

Only available in MCP

TSOP1

GENERAL DESCRIPTION

Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 200µs on the 2112-byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns(50ns with 1.8V
device) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the K9F1G08X0A′s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0A is an optimum solu­tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-v ol at il it y.

2

K9F1G08R0A
K9F1G08U0A

PIN CONFIGURATION (TSOP1)

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

K9K2G08U1A FLASH MEMORY

K9F1G08X0A-YCB0,PCB0/YIB0,PIB0

X8 X8

N.C

N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE

WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48-pin TSOP1

Standard Type
12mm x 20mm

48

N.C

47

N.C

46

N.C

45

I/O7

44

I/O6

43

I/O5

42

I/O4

41

N.C

40

N.C

39

N.C

38

Vcc

37

Vss

36

N.C

35

N.C

34

N.C

33

I/O3

32

I/O2

31

I/O1

30

I/O0

29

N.C

28

N.C

27

N.C

26

N.C

25

48 - TSOP1 - 1220AF

+0.07

-0.03

#1

0.20

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197
#24

TYP

0.25

0.010

0~8°

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#48

#25

Unit :mm/Inch

MAX

0.10

0.004

0.25

0.010

()

MAX

12.00

0.472

0.488

12.40

1.00±0.05

0.039±0.002

1.20
MAX

+0.075

0.035
+0.003

-0.001

0.125

0.005

0.047

0.05

0.002

MIN

0.45~0.75

0.018~0.030

0.50

()

0.020

3

K9F1G08R0A
K9F1G08U0A

PIN CONFIGURATION (WSOP1)

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

K9K2G08U1A FLASH MEMORY

K9F1G08U0A-VIB0,FIB0

N.C
N.C

DNU

N.C
N.C
N.C
R/B
RE

CE

DNU

N.C
Vcc
Vss
N.C

DNU

CLE
ALE

WE
WP
N.C
N.C

DNU

N.C
N.C

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C

48 - WSOP1 - 1217F

#1

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP
(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0

°

~

8

°

0.45~0.75

4

K9F1G08R0A
K9F1G08U0A

PIN CONFIGURATION (ULGA)

K9K2G08U1A FLASH MEMORY

K9K2G08U1A-ICB0/IIB0

AB

CDE

G

F

L

M

K

H

J

N

7

6

5

4

3

2

1

PACKAGE DIMENSIONS

52-ULGA (measured in millimeters)

Top View

12.00±0.10

#A1

NC

NC

Vcc

/CE1

CLE1

Vss

NC

NC

NC NC

NC

/RE1

/RB2

/RE2

/RB1

/CE2

CLE2

/WE1

ALE2

ALE1

/WE2

NC

NC

Vss

/WP1

IO7-2

/WP2

IO0-1

IO0-2

IO7-1

IO1-1

IO6-2

IO6-1

IO2-1

IO1-2

NC

IO5-1

IO3-1

IO5-2

IO4-1

Vss

IO2-2

NC

NC

NC

Vcc

IO4-2

IO3-2

Vss

NC

NC

NC

Bottom View

12.00±0.10

1.00

10.00

1.00

2.00

7 6 5 4 3 2 1

(Datum A)

A

B

C

(Datum B)

17.00±0.10

D

E

F

G

H

J

K

L

M

N

1.00

1.00

A

B

1.30

1.00

2.50

12.00

17.00±0.10

1.00

2.50

1.00

2.00

0.50

0.10 C

12-∅1.00±0.05

Side View

17.00

±

0.10

0.1

ABCM

∅

41-∅0.70±0.05

0.1

∅

ABCM

.)

Max

(

0.65

5

K9F1G08R0A
K9F1G08U0A

PIN DESCRIPTION

Pin Name Pin Function

0 ~ I/O7

I/O

CLE

K9K2G08U1A FLASH MEMORY

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE

signal.

ALE

CE

RE

WE

WP

R/B

Vcc

Vss GROUND

N.C

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE

CHIP ENABLE

The CE
the device does not return to standby mode.

READ ENABLE

The RE
tREA after the falling edge of RE

WRITE ENABLE

The WE
the WE

WRITE PROTECT

The WP
generator is reset when the WP

READY/BUSY OUTPUT

The R/B
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

POWER

V

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

with ALE high.

input is the device selection control. When the device is in the Busy state, CE high is ignored, and

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

which also increments the internal column address counter by one.

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

pulse.

pin provides inadvertent write/erase protection during power transitions. The internal high voltage

pin is active low.

output indicates the status of the device operation. When low, it indicates that a program, erase or

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave V

CC or VSS disconnected.

6

K9F1G08R0A
K9F1G08U0A

Figure 1-1. K9F1G08X0A Functional Block Diagram

VCC

SS

V

K9K2G08U1A FLASH MEMORY

A12 - A27

A0 - A11

Command

CE
RE
WE

X-Buffers
Latches
& Decoders

Y-B uf fers
Latches
& Decoders

Command

Register

Control Logic

& High Voltage

Generator

CLE

ALE PRE

WP

Figure 2-1. K9F1G08X0A Array Organization

1024M + 32M Bit

NAND Flash

ARRAY

(2048 + 64)Byte x 65536

Data Register & S/A

Cache Register

Y-G ating

I/O Buffers & Latches

Global Buffers

1 Block = 64 Pages
(128K + 4k) Byte

Output

Driver

VCC
VSS

I/0 0

I/0 7

64K Pages
(=1,024 Blocks)

2K Bytes 64 Bytes

Page Register

2K Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

2nd Cycle A8 A9 A10 A11 *L *L *L *L

3rd Cycle A

4th Cycle A20 A21 A22 A23 A24 A25 A26 A27

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

0 A1 A2 A3 A4 A5 A6 A7

12 A13 A14 A15 A16 A17 A18 A19

1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 1024 Blocks
= 1056 Mbits

8 bit

I/O 0 ~ I/O 7

64 Bytes

Column Address

Column Address

Row Address
Row Address

7

K9F1G08R0A
K9F1G08U0A

Product Introduction

The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 col­umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con­nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read opera­tions are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 sep­arately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08X0A.

The K9F1G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte physical space
requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper­ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com­mand register. Table 1 defines the specific commands of the K9F1G08X0A.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.

to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

K9K2G08U1A FLASH MEMORY

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 00h 30h

Read for Copy Back 00h 35h

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Cache Program

Copy-Back Program 85h 10h

Block Erase 60h D0h

Random Data Input

Random Data Output

Read Status 70h O

*2

*1

*1

80h 15h

85h -

05h E0h

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Cache program and Copy-Back program are supported only with 3.3V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

8

K9F1G08R0A
K9F1G08U0A

ABSOLUTE MAXIMUM RATINGS

Voltage on any pin relative to V

Temperature Under
Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage V

Supply Voltage V

K9K2G08U1A FLASH MEMORY

Parameter Symbol

SS

K9F1G08X0A-XCB0

K9F1G08X0A-XIB0 -40 to +125

K9F1G08X0A-XCB0

K9F1G08X0A-XIB0

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

V

CC -0.2 to + 2.45 -0.6 to + 4.6

T

BIAS

T

STG -65 to +150 °C

1.8V DEVICE 3.3V DEVICE

K9F1G08R0A(1.8V)

Min Typ . Max Min Typ. Max

CC 1.65 1.8 1.95 2.7 3.3 3.6 V

SS 000000 V

Rating

-10 to +125

K9F1G08U0A(3.3V)

Unit

Unit

V

°C

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

K9F1G08R0A K9F1G08U0A

Parameter Symbol Test Conditions

Min Typ Max Min Ty p Max

Page Read with

Operating

Serial Access

Current

Program ICC2 - - 10 20 - 15 30

Erase I

Stand-by Current(TTL) ISB1CE=VIH, WP=0V/VCC --1--1

Stand-by Current(CMOS) I

Input Leakage Current I

Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10

Input High Voltage V

Input Low Voltage, All inputs VIL* - -0.3 - 0.2xVcc -0.3 - 0.2xVcc

Output High Voltage Level V

Output Low Voltage Level

Output Low Current(R/B

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

)IOL(R/B)

tRC=30ns(50ns with 1.8V device),

I

CC1

CE=VIL

- 10 20 - 15 30

IOUT=0mA

CC3 - - 10 20 - 15 30

CE

SB2

LI VIN=0 to Vcc(max) - - ±10 - - ±10

IH* -0.8xVCC -

OH

OL

V

=VCC-0.2,

=0V/VCC

WP

K9F1G08R0A :IOH=-100µA

K9F1G08U0A :I

OH=-400µA

K9F1G08R0A :IOL=100uA

K9F1G08U0A :I

K9F1G08R0A :V

K9F1G08U0A :V

OL=2.1mA

OL=0.1V

OL=0.4V

- 10 50 - 10 50

V

CC

0.8xVcc -

Vcc

-0.1

+0.3

--2.4--

+0.3

--0.1--0.4

34- 810-mA

V

CC

Unit1.8V 3.3V

mA

µA

V

9

K9F1G08R0A

K9F1G08U0A

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

K9F1G08X0A N

K9K2G08U1A

NOTE :

K9F1G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

1. The
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.

Each K9F1G08U0A chip in the K9K2G08U1A has Maximum 20 invalid blocks.

* :

AC TEST CONDITION

(K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C

K9F1G08R0A : Vcc=1.65V~1.95V, K9F1G08U0A : Vcc=2.7V~3.6V unless otherwise noted)

Input Pulse Levels 0V to Vcc 0V to Vcc

Input Rise and Fall Times 5ns 5ns

Input and Output Timing Levels Vcc/2 Vcc/2

Output Load 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE ALE CE WE RE WP Mode

HLL HX

L H L H X Address Input(4clock)

HLL HH

L H L H H Address Input(4clock)

L L L H H Data Input

L L L H X Data Output

XXXXHX During Read(Busy)

XXXXXH During Program(Busy)

XXXXXH During Erase(Busy)

X

XXHXX

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

Program / Erase Characteristics

Program Time

Dummy Busy Time for Cache Program

Number of Partial Program Cycles
in the Same Page

Block Erase Time t

NOTE : 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V ans 25’C.

2. Max. time of tCBSY depends on timing between internal program completion and data in.

K9K2G08U1A FLASH MEMORY

VB 1004 - 1024 Blocks

VB

N

. Refer to the attached technical notes for appropriate management of invalid blocks.

Parameter K9F1G08R0A K9F1G08U0A

Item Symbol Test Condition Min Max Unit

I/O VIL=0V - 10 pF

IN VIN=0V - 10 pF

*1

X

X X X L Write Protect

Parameter Symbol Min Ty p Max Unit

Main Array

Spare Array - - 4 cycles

2008 - 2048 Blocks

Read Mode

Write Mode

(2)

0V/V

*1

PROG

t

*2

CBSY

t

Nop

BERS -23ms

Stand-by

CC

- 200 700 µs

- - 4 cycles

Command Input

Command Input

3 700

µs

10

K9F1G08R0A

K9F1G08U0A

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol

CLE setup Time

CLE Hold Time t

CE

setup Time

Hold Time tCH 10 5 - - ns

CE

WE

Pulse Width tWP 25 15 - - ns

ALE setup Time

ALE Hold Time t

Data setup Time

Data Hold Time t

Write Cycle Time t

WE

High Hold Time tWH 15 10 - - ns

ALE to Data Loading Time

NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.

2. tADL is the time from the WE

3. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.

K9K2G08U1A FLASH MEMORY

Min Max

K9F1G08R0A K9F1G08U0A K9F1G08R0A K9F1G08U0A

*1

CLS

t

CLH 10 5 - - ns

*1

CS

t

*1

t

ALS

ALH 10 5 - - ns

*1

DS

t

DH 10 5 - - ns

WC 45 30 - - ns

*2

t

ADL

rising edge of final address cycle to the WE rising edge of first data cycle.

25 15 - - ns

35 20 - - ns

25 15 - - ns

20 15 - - ns

100

*2

100

*2

--ns

Unit

AC Characteristics for Operation

Parameter Symbol

K9F1G08R0A K9F1G08U0A K9F1G08R0A K9F1G08U0A

Data Transfer from Cell to Register tR - - 25 25 µs

ALE to RE

CLE to RE

Ready to RE

RE Pulse Width t

WE High to Busy t

Read Cycle Time t

RE

CE

RE

CE

RE

RE

Output Hi-Z to RE

RE

WE

Device Resetting Time
(Read/Program/Erase)

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.

Delay tAR 10 10 - - ns

Delay tCLR 10 10 - - ns

Low tRR 20 20 - - ns

RP 25 15 - - ns

WB - - 100 100 ns

RC 50 30 - - ns

Access Time tREA - - 30 20 ns

Access Time tCEA - - 45 35 ns

High to Output Hi-Z tRHZ - - 30 30 ns

High to Output Hi-Z tCHZ - - 20 20 ns

or CE High to Output hold tOH 15 15 - - ns

High Hold Time tREH 15 10 - - ns

Low tIR 00- -ns

High to WE Low tRHW 100 100 - - ns

High to RE Low tWHR 60 60 - - ns

t

RST --

Min Max

5/10/500

*1

5/10/500

*1

Unit

µs

11

K9F1G08R0A

K9F1G08U0A

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested
flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

K9K2G08U1A FLASH MEMORY

Start

Increment Block Address

Create (or update)

Initial Invalid Block(s) Table

Figure 3. Flow chart to create initial invalid block table.

Set Block Address = 0

No

No

Check "FFh

Yes

Last Block ?

Yes

End

Check "FFh" at the column address

of the 1st and 2nd page in the block

2048

*

12

K9F1G08R0A

K9F1G08U0A

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an
erased empty block and reprogramming the current target data and copying the rest of the replaced block.In case of Read, ECC must
be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed
blocks.

Write

Read Single Bit Failure Verify ECC -> ECC Correction

K9K2G08U1A FLASH MEMORY

Failure Mode Detection and Countermeasure sequence

Erase Failure Status Read after Erase --> Block Replacement

Program Failure Status Read after Program --> Block Replacement

ECC

Program Flow Chart

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

*

Program Error

I/O 6 = 1 ?

or R/B = 1 ?

No

I/O 0 = 0 ?

Program Completed

13

No

Yes

Yes

: If program operation results in an error, map out

*

the block including the page in error and copy the
target data to another block.

K9F1G08R0A

K9F1G08U0A

NAND Flash Technical Notes (Continued)

K9K2G08U1A FLASH MEMORY

Erase Flow Chart

*

Erase Error

No

Start

Write 60h

Write Block Address

Write D0h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

No

Read Flow Chart

Reclaim the Error

Start

Write 00h

Write Address

Write 30h

Read Data

ECC Generation

No

Verify ECC

Yes

Page Read Completed

Erase Completed

: If erase operation results in an error, map out

*

the failing block and replace it with another block.

Block Replacement

Block A

1st

∼

{

(n-1)th

nth

(page)

1st

∼

(n-1)th

nth

(page)

* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

an error occurs.

Block B

{

1

Buffer memory of the controller.

2

14

K9F1G08R0A

K9F1G08U0A

NAND Flash Technical Notes (Continued)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig­nificant bit) pages of the block. Random page address programming is prohibited.

K9K2G08U1A FLASH MEMORY

Page 63

Page 31

Page 2
Page 1
Page 0

From the LSB page to MSB page

DATA IN: Data (1)

(64)

:

(32)

:

(3)
(2)
(1)

Data register

Data (64)

Page 63

Page 31

Page 2
Page 1
Page 0

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

(64)

:

(1)

:

(3)

(32)

(2)

Data register

Data (64)

15

K9F1G08R0A

K9F1G08U0A

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE
would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE

K9K2G08U1A FLASH MEMORY

during the data-loading and serial access

CE don’t-care

WE

ALE

I/Ox

CE

WE

Address(4Cycles)80h Data Input

tCS

tWP

tCH

Figure 5. Read Operation with CE don’t-care.

CLE

CE

≈

CE

RE

I/O0~7

tCEA

tREA

CE

don’t-care

≈

Data Input

out

10h

RE

ALE

R/B

WE

I/Ox

≈

tR

Address(4Cycle)00h

30h

16

Data Output(serial access)

K9F1G08R0A

K9F1G08U0A

NOTE

Device

K9F1G08X0A I/O 0 ~ I/O 7 ~2112byte A0~A7 A8~A11 A12~A19 A20~A27

Command Latch Cycle

K9K2G08U1A FLASH MEMORY

I/O DATA ADDRESS

I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2

CLE

CE

WE

ALE

I/Ox

Address Latch Cycle

CLE

tCLS

tCLS

tCS

tALS

tWP

tDS

Command

tCLH

tCH

tALH

tDH

CE

WE

ALE

I/Ox

tCS

tALS

tWP

tDS

Col. Add1

tWC

tALH

tDH

tWH

tWP

tALS

17

tWC

tALH

tDH

tDS

Col. Add2

tWH

tWP

tALS

Row Add1

tDS

tWC

tALH

tDH

tWH

tWP

tALS

tDS

Row Add2

tALH

tDH

K9F1G08R0A

K9F1G08U0A

Input Data Latch Cycle

CLE

CE

K9K2G08U1A FLASH MEMORY

tCLH

≈

tCH

≈

ALE

WE

I/Ox

tALS

tWP

tWC

tWH

tDH

tDS

DIN 0

NOTES : DIN final means 2112

tWP

tDS

DIN 1

tDH

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

CE

RE

tCEA

tREA

tREH tREA

tRP

≈

≈

≈

≈

tRHZ*

tWP

tDH

tDS

DIN final*

≈ ≈

tREA

tCHZ*

tOH

tRHZ*

I/Ox

R/B

DoutDout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

tRC

This parameter is sampled and not 100% tested.

18

≈≈

tOH

Dout

K9F1G08R0A

K9F1G08U0A

Status Read Cycle

CLE

CE

WE

RE

I/Ox

K9K2G08U1A FLASH MEMORY

tCLS

tCS

tWP

tDS

70h

tCLH

tCH

tDH

tWHR

tCLR

tIR*

tCEA

tREA

tCHZ*

tOH

tRHZ*

tOH

Status Output

19

K9F1G08R0A

K9F1G08U0A

Read Operation

CLE

CE

tWC

WE

ALE

K9K2G08U1A FLASH MEMORY

tCLR

tWB

tAR

tR

tRC

tRHZ

tOH

RE

I/Ox

00h

Col. Add1

Column Address

Col. Add2

R/B

Read Operation(Intercepted by CE)

CLE

CE

WE

ALE

Row Add1

Row Address

Row Add2

30h

tRR

Busy

tWB

tAR

Dout N

Dout N+1

≈

≈≈

Dout M

tCHZ

tOH

RE

I/Ox

R/B

00h

Col. Add1

Column Address

Col. Add2 Row Add1

Row Address

Row Add2

20

30h

tR

tRR

Busy

Dout N

tRC

Dout N+1

Dout N+2

K9F1G08R0A

K9F1G08U0A

K9K2G08U1A FLASH MEMORY

Dout M+1

tCLR

tWB

tWHR

tAR

tREA

tRC

tR

tRR

Dout M

E0h

Col Add2

Col Add1

Dout N Dout N+1

30h 05h

Column Address

Busy

Random Data Output In a Page

CLE

CE

WE

21

ALE

RE

Row Add2

Row Add1

Col. Add2

Col. Add1

00h

I/Ox

Row Address

Column Address

R/B

K9F1G08R0A

K9F1G08U0A

Page Program Operation

CLE

CE

WE

ALE

RE

I/Ox

Input Command

R/B

K9K2G08U1A FLASH MEMORY

tWC

80h 70h I/O0

SerialData

Co.l Add1

Column Address Row Address

tWC

Col. Add2 Row Add1

Row Add2

tADL

Din

N

1 up to m Byte

Serial Input

m = 2112byte

tWC

≈

tPROG

tWB

≈

Din

10h

M

≈

Program
Command

Read Status
Command

≈

I/O

0=0 Successful Program

I/O

0=1 Error in Program

NOTES : tADL is the time from the WE

rising edge of final address cycle to the WE rising edge of first data cycle.

22

K9F1G08R0A

K9F1G08U0A

K9K2G08U1A FLASH MEMORY

0

Read Status

Command

≈

tPROG

tWB

10h

Program

Command

K

Din

≈

≈

tADL

≈

Din

Serial Input

J

tWC

tWC

Col. Add2

Column Address

Col. Add1

85h

Random Data

Input Command

M

Din

≈

≈≈

N

Din

Serial Input

tADL

Row Add3

rising edge of final address cycle to the WE rising edge of first data cycle.

Row Add2

Row Add1

Col. Add2

Column Address Row Address

Col. Add1

Page Program Operation with Random Data Input

CLE

CE

tWC

WE

23

ALE

RE

80h 70h I/O

I/Ox

Serial Data

Input Command

NOTES : tADL is the time from the WE

R/B

K9F1G08R0A

K9F1G08U0A

K9K2G08U1A FLASH MEMORY

Read Status

Command

tPROG

tWB

10h

Data N

≈

≈ ≈

Data 1

tADL

Row Add2

≈

Busy

0=0 Successful Program

0=1 Error in Program

I/O

I/O

tWC

tWB

Row Address

Col Add2 Row Add1

Col Add1

Column Address

85h

≈

Copy-Back Data

Input Command

tR

35h

Row Add2

Row Address

Col Add2 Row Add1

Col Add1

Column Address

00h 70h I/O0

Busy

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

Copy-Back Program Operation with Random Data Input

CLE

CE

WE

24

ALE

RE

I/Ox

R/B

K9F1G08R0A

K9F1G08U0A

K9K2G08U1A FLASH MEMORY

I/O

70h

70h

tPROG

10h

≈

tPROG

tWB

10h

(True)

Command

Program Confirm

M

Din

≈

tADL

≈≈

N

Din

Row Add2

Row Add1

Col Add2

Col Add1

tCBSY

Last Page Input & Program

Address &

Data Input

80h

15h

Address &

Data Input

80h

tCBSY

80h

15h

≈

Address &

tCBSY

tWB

15h

Program

Command

(Dummy)

M

Din

≈

≈

tADL

≈

N

Din

Serial Input

Row Add2

CBSY :

t

max. 700us

tCBSY

Data Input

80h

15h

Address &

Data Input

Data

Cache Program Operation(available only within a block)

CLE

CE

tWC

WE

ALE

RE

25

Row Add1

Col Add2

Col Add1

80h

I/Ox

Serial Data

Row Address

Column Address

Max. 63 times repeatable

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

Input Command

Ex.) Cache Program

R/B

80h

I/Ox

Col Add1,2 & Row Add1,2

R/B

K9F1G08R0A

K9F1G08U0A

BLOCK ERASE OPERATION

CLE

CE

WE

ALE

RE

K9K2G08U1A FLASH MEMORY

tWC

tWB

tBERS

I/Ox

R/B

Row Add1

60h

Auto Block Erase
Setup Command

Row Add2

Row Address

D0h 70h I/O 0

Busy

Erase Command

≈

Read Status
Command

0=0 Successful Erase

I/O
I/O

0=1 Error in Erase

26

K9F1G08R0A

K9F1G08U0A

Read ID Operation

CLE

CE

WE

K9K2G08U1A FLASH MEMORY

ALE

RE

I/Ox

Read ID Command Maker Code

90h

Address. 1cycle

Device Device Code*(2nd Cycle) 4th Cycle*

K9F1G08R0A A1h 15h

K9F1G08U0A F1h 15h

K9K2G08U1A Same as each K9F1G08U0A in it

ID Defintition Table

90 ID : Access command = 90H

tAR

tREA

00h ECh

Device
Code*

Device Code

XXh

4th cyc.*

1
2
3
4

st

Byte

nd

Byte

rd

Byte

th

Byte

Description

Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization,Serial access minimum

27

K9F1G08R0A

K9F1G08U0A

4th ID Data

ITEM Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Page Size
(w/o redundant area )

Block Size
(w/o redundant area )

Redundant Area Size
( byte/512byte)

Organization

Serial Access minimum

K9K2G08U1A FLASH MEMORY

1KB
2KB
Reserved
Reserved

64KB
128KB
256KB
Reserved

8
16

x8
x16

50ns/30ns
25ns
Reserved
Reserved

0 0
0 1
1 0
1 1

0

1

0
1

0
1
0
1

0
0
1
1

0 0
0 1
1 0
1 1

28

K9F1G08R0A

K9F1G08U0A

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25µs(t
this data transfer(tR) by analyzing the output of R/B
out in 30ns cycle time(50ns with 1.8V device) by sequentially pulsing RE
the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com­mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

CE

K9K2G08U1A FLASH MEMORY

R). The system controller can detect the completion of

pin. Once the data in a page is loaded into the data registers, they may be read

. The repetitive high to low transitions of the RE clock make

WE

ALE

R/B

RE

I/Ox

Address(4Cycle)00h

Col Add1,2 & Row Add1,2

tR

30h

Data Field Spare Field

Data Output(Serial Access)

29

K9F1G08R0A

K9F1G08U0A

Figure 7. Random Data Output In a Page

K9K2G08U1A FLASH MEMORY

R/B

tR

RE

I/Ox

00h

Address
4Cycles

Col Add1,2 & Row Add1,2

30h

Data Field

Data Output

Spare Field

05h

Address

2Cycles

E0h

Data Field

Data Output

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare
array(1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data
input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim­ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro­gram cycle by monitoring the R/B
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.

output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset

Figure 8. Program & Read Status Operation

R/B

I/Ox

80h

Address & Data Input

Col Add1,2 & Row Add1,2

Data

10h 70h

30

tPROG

I/O0

Fail

"0"

Pass

"1"

K9F1G08R0A

K9F1G08U0A

Figure 9. Random Data Input In a Page

K9K2G08U1A FLASH MEMORY

R/B

tPROG

"0"

I/Ox

80h

Address & Data Input

Col Add1,2 & Row Add1,2

85h

Data

Address & Data Input

Col Add1,2

Data

10h

70h

I/O0

"1"

Fail

Cache Program

Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.

After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg­isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre­viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B
mand (10h).

, the last page of the target programming sequence must be progammed with actual Page Program com-

Pass

Figure 10. Cache Program(available only within a block)

R/B

tCBSY

Address &

80h

Data Input*

Col Add1,2 & Row Add1,2 Col Add1,2 & Row Add1,2

Data Data

15h

80h

Address &
Data Input

tCBSY

15h

Address &

80h

Data Input

Col Add1,2 & Row Add1,2

Data

15h

tCBSY

80h

Col Add1,2 & Row Add1,2

Address &
Data Input

Data

10h

tPROG

70h

31

K9F1G08R0A

K9F1G08U0A

NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the

previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple­tion of the previous cycle, which can be expressed as the following formula.

tPROG= Program time for the last page+ Program time for the ( last -1 )th page

- (Program command cycle time + Last page data loading time)

Copy-Back Program

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben­efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy­ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command
(85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actu­ally begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 12. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status.

But if the soure page has an error bit by charge loss, accumulated copy-back operations could also accumulate bit errors.
In this case, verifying the source page for a bit error is recommended before Copy-back program"

Figure 11. Page Copy-Back program Operation

R/B

K9K2G08U1A FLASH MEMORY

tR

tPROG

Add.(4Cycles)

I/Ox

NOTE: It’s prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even

address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or
even address pages .

00h

Col. Add1,2 & Row Add1,2

Source Address

35h

Add.(4Cycles)

85h 70h

Col. Add1,2 & Row Add1,2

Destination Address

10h

I/O0

Fail

Figure 12. Page Copy-Back program Operation with Random Data Input

10h

tPROG

70h

R/B

I/Ox

Add.(4Cycles)

00h

Col. Add1,2 & Row Add1,2

Source Address

35h

tR

Add.(4Cycles)

85h

Col. Add1,2 & Row Add1,2

Destination Address

Data

There is no limitation for the number of repetition.

85h

Add.(2Cycles)

Col Add1,2

Data

Pass

32

K9F1G08R0A

K9F1G08U0A

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com­mand(60h). Only address A
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

Figure 13. Block Erase Operation

K9K2G08U1A FLASH MEMORY

18 to A27 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block

after the erase confirm command input, the internal write controller handles erase and erase-verify. When

R/B

tBERS

"0"

I/Ox

60h

Address Input(2Cycle)

Block Add. : A12 ~ A27

D0h

70h

I/O0

"1"

Fail

Pass

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE
the system to poll the progress of each device in multiple memory connections even when R/B
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.

or RE, whichever occurs last. This two line control allows

pins are common-wired. RE or CE

Table2. Read Staus Register Definition

I/O No. Page Program Block Erase Cache Prorgam Read Definition

I/O 0 Pass/Fail Pass/Fail Pass/Fail(N) Not use Pass : "0" Fail : "1"

I/O 1 Not use Not use Pass/Fail(N-1) Not use Pass : "0" Fail : "1"

I/O 2 Not use Not use Not use Not use "0"

I/O 3 Not Use Not Use Not Use Not Use "0"

I/O 4 Not Use Not Use Not Use Not Use "0"

I/O 5 Ready/Busy Ready/Busy True Ready/Busy Ready/Busy Busy : "0" Ready : "1"

I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"

I/O 7 Write Protect Write Protect Write Protect Write Protect Protected:"0" Not Protected:"1"

NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.

2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

33

K9F1G08R0A

K9F1G08U0A

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.

Figure 14. Read ID Operation

K9K2G08U1A FLASH MEMORY

CLE

tCLR

tCEA

CE

WE

tAR

ALE

RE

I/OX

90h

00h

Address. 1cycle

K9F1G08R0A A1h 15h

K9F1G08U0A F1h 15h

K9K2G08U1A Same as each K9F1G08U0A in it

tWHR

Device Device Code*(2nd Cycle) 4th Cycle*

tREA

ECh

Maker code

Device

Code*

Device code

XXh 4th Cyc.*

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP
already in reset state a new reset command will be accepted by the command register. The R/B
the Reset command is written. Refer to Figure 15 below.

is high. Refer to table 3 for device status after reset operation.If the device is

pin transitions to low for tRST after

Figure 15. RESET Operation

R/B

I/OX

FFh

tRST

Table3. Device Status

After Power-up After Reset

Operation Mode 00h command is latched Waiting for next command

34

K9F1G08R0A

K9F1G08U0A

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be
determined by the following guidance.

VCC

K9K2G08U1A FLASH MEMORY

pin is normally high but transitions to low after program or erase command is written to the command regis-

outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

Rp

ibusy

OL : 0.1V, VOH : VCC-0.1V
OL : 0.4V, VOH : 2.4V

VOH

R/B

open drain output

1.8V device - V

3.3V device - V

Ready Vcc

CL

GND

Device

Figure 17. Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 1.8V, Ta = 25°C , CL = 30pF

300n 3m

Ibusy

200n

100n

tr,tf [s]

1.70

30

1.70

0.85

60

tr

1.70

tf

90

1.70

1K 2K 3K

Rp(ohm)

0.57

120

0.43

1.70

4K

VOL

Busy

tf

tr

@ Vcc = 3.3V, Ta = 25°C , CL = 50pF

Ibusy [A]

300n 3m

200n

2m

2.4

Ibusy

1.2

100

150

0.8

tr

1m

100n

tr,tf [s]

50

1.8

1.8

tf

1.8

0.6

1K 2K 3K

Rp(ohm)

200

Ibusy [A]

2m

1m

1.8

4K

Rp value guidance

V

Rp(min, 1.8V part) =

Rp(min, 3.3V part) =

CC(Max.) - VOL(Max.)

IOL + ΣIL

V

CC(Max.) - VOL(Max.)

IOL + ΣIL

=

=

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

35

1.85V

3mA

8mA

+ ΣIL

3.2V

+ ΣIL

K9F1G08R0A

K9F1G08U0A

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP
recommended to be kept at V
gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides addi­tional software protection.

Figure 17. AC Waveforms for Power Transition

K9K2G08U1A FLASH MEMORY

pin provides hardware protection and is

IL during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit

VCC

WP

WE

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

High

≈ ≈≈≈

10µs

36

K9F1G08R0A

K9F1G08U0A

Extended Data Out Mode

For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller
could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly.
The device stops the data input into the I/O bus after RE
O data seems like Figure 18 and the system can access serially the data with EDO mode. tRLOH which is the parameter for fetching
data at RE falling time is necessary. Its appropriate value can be obtained with the reference chart as shown in Figure 19. The tRHOH
value depands on output load(C

Figure 18. Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)

CE

RE

K9K2G08U1A FLASH MEMORY

rising edge. But since the previous data remains in the I/O bus, the flow of I/

L) and I/O bus Pull-up resistor (Rp).

≈

tRP

tRC

tREH

≈

I/Ox

R/B

VCC

GND

tRR

I/O Drive

tREA

tCEA

tREA

tRLOH

≈

Dout Dout

tRHOH

≈

≈

NOTES : Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.

Figure 19. Rp vs tRHOH vs CL

Rp

@ Vcc = 3.3V, Ta = 25

tRHOH

600n

500n

360

180

36

18

30p 50p 70p

Device

CL

400n

300n

200n

100n

50n

tRLOH / tRHOH value guidance

600

300

60

Rp = 100k

30

°C

425

85

tRHOH

600

Rp = 50k

120

Rp = 10k

Rp = 5k

100p

60

C

(F)

L

42

tRHOH = CL * VOL * Rp / Vcc

tRLOH(min, 3.3V part) = tRHOH - tREH

37