SAMSUNG K9F1G08R0A Technical data

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K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

Document Title

128M x 8 Bit / 256M x 8 Bit NAND Flash Memory

Revision History

Revision No History

0.01. Initial issue

0.11. The tADL(Address to Data Loading Time) is added.

-tADL Minimum 100ns (Page 11, 23~26)

-tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation.

2.Added Addressing method for program operation

0.21. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

0.31. PKG(TSOP1, WSOP1) Dimension Change

0.41. Technical note is changed

2.Notes of AC timing characteristics are added

3.The description of Copy-back program is changed

4.Voltage range is changed

-1.7V~1.95V -> 1.65V~1.95V

5.Note2 of Command Sets is added

0.51. CE access time : 23ns->35ns (p.11)

0.61. The value of tREA for 3.3V device is changed.(18ns->20ns)

2.EDO mode is added.

Draft Date	Remark
Aug. 24. 2003	Advance
Jan. 27. 2004	Preliminary

Apr. 23. 2004	Preliminary
May. 19. 2004	Preliminary
Jan. 21. 2005	Preliminary

Feb. 14. 2005

Preliminary

May. 24. 2005

0.7	1. The flow chart to creat the initial invalid block table is cahnged.	May 6. 2005

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.

1

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

128M x 8 Bit /256M x 8 Bit NAND Flash Memory

PRODUCT LIST

	Part Number	Vcc Range	Organization	PKG Type
	K9F1G08R0A	1.65 ~ 1.95V		Only available in MCP
	K9F1G08U0A-Y,P		X8	TSOP1
	K9F1G08U0A-V,F	2.7 ~ 3.6V		WSOP1
	K9K2G08U1A-I			52-ULGA

FEATURES

• Voltage Supply	• Fast Write Cycle Time
-1.8V device(K9F1G08R0A): 1.65V~1.95V	- Program time : 200µs(Typ.)
-3.3V device(K9F1G08U0A): 2.7 V ~3.6 V	- Block Erase Time : 2ms(Typ.)
• Organization	• Command/Address/Data Multiplexed I/O Port
- Memory Cell Array : (128M + 4,096K)bit x 8bit	• Hardware Data Protection
- Data Register : (2K + 64)bit x8bit	- Program/Erase Lockout During Power Transitions
- Cache Register : (2K + 64)bit x8bit	• Reliable CMOS Floating-Gate Technology
• Automatic Program and Erase	- Endurance : 100K Program/Erase Cycles
- Page Program : (2K + 64)Byte	- Data Retention : 10 Years
- Block Erase : (128K + 4K)Byte	• Command Register Operation
• Page Read Operation	• Cache Program Operation for High Performance Program
- Page Size : 2K-Byte	• Intelligent Copy-Back Operation
- Random Read : 25µs(Max.)	• Unique ID for Copyright Protection
- Serial Access : 30ns(Min.) - 3.3v device	• Package :
50ns(Min.) -1.8v device	- K9F1G08U0A-YCB0/YIB0
	48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
	- K9F1G08U0A-VIB0
	48 - Pin WSOP I (12X17X0.7mm)
	- K9F1G08U0A-PCB0/PIB0
	48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
	- K9F1G08U0A-FIB0
	48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
	* K9F1G08U0A-V,F(WSOPI ) is the same device as
	K9F1G08U0A-Y,P(TSOP1) except package type.
	- K9K2G08U1A-ICB0/IIB0
	52-ULGA (12X17X0.65mm)

GENERAL DESCRIPTION

Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 200µs on the 2112-byte page and an erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns(50ns with 1.8V device) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08X0A′s extended reliability of 100K program/ erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

2

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

PIN CONFIGURATION (TSOP1)

K9F1G08X0A-YCB0,PCB0/YIB0,PIB0

X8

X8

N.C		1
N.C		2
N.C		3
N.C		4
N.C		5
N.C		6
R/B		7
RE		8
CE		9
N.C		10
N.C		11
Vcc		12
Vss		13
N.C		14
N.C		15
CLE		16
ALE		17
WE		18
WP		19
N.C		20
N.C		21
N.C		22
N.C		23
N.C		24

48-pin TSOP1 Standard Type 12mm x 20mm

48 N.C

47 N.C

46 N.C

45 N.C

44 I/O7

43 I/O6

42 I/O5

41 I/O4

40 N.C

39 N.C

38 N.C

37 Vcc

36 Vss

35 N.C

34 N.C

33 N.C

32 I/O3

31 I/O2

30 I/O1

29 I/O0

28 N.C

27 N.C

26 N.C

25 N.C

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220AF

Unit :mm/Inch

	+0.07 -0.03
	0.20
+0.07 -0.03		+0.003 -0.001
0.16		0.008

0.50 0.0197

0~8°

20.00±0.20							MAX
							0.10	0.004
	0.787±0.008

#1

#48

)
0.25	0.010
(

MAX	12.00 0.472
12.40 0.488

#24

#25

															1.00±0.05								0.05					MIN
																0.039±0.002											0.002
TYP				18.40±0.10			+0.075 0.035								1.20			MAX
												+0.003	0.001-				0.047
		0.724±0.004
0.25	0.010						0.125					0.005

		0.45~0.75												0.50
													(		)
	0.018~0.030
														0.020

3

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

PIN CONFIGURATION (WSOP1)

K9F1G08U0A-VIB0,FIB0

N.C		1	48		N.C
N.C		2	47		N.C
DNU		3	46		DNU
N.C		4	45		N.C
N.C		5	44		I/O7
N.C		6	43		I/O6
R/B		7	42		I/O5
RE		8	41		I/O4
CE		9	40		N.C
DNU		10	39		DNU
N.C		11	38		N.C
Vcc		12	37		Vcc
Vss		13	36		Vss
N.C		14	35		N.C
DNU		15	34		DNU
CLE		16	33		N.C
ALE		17	32		I/O3
WE		18	31		I/O2
WP		19	30		I/O1
N.C		20	29		I/O0
N.C		21	28		N.C
DNU		22	27		DNU
N.C		23	26		N.C
N.C		24	25		N.C

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

Unit :mm

#1

(00..5050TYP±0.06) 0.20 -+00..0307 0.16 -+00..0307

#24

15.40±0.10

17.00±0.20

0.70 MAX
0.58±0.04
#48
10.0±00.12	40MAX.12
#25
(0.01Min)

+0.075 -0.035

0.10	8
	0
	°
	~
	°
	0.45~0.75

4

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

PIN CONFIGURATION (ULGA)

K9K2G08U1A-ICB0/IIB0

A B C D E F G H J K L M N

	NC	NC		NC				NC		NC	NC
7	NC		/RE1	/RB2			IO7-2
6								IO6-2		IO5-2	NC
	Vcc		/RE2		Vss		IO7-1		IO5-1	Vcc
5	/CE1			/RB1		/WP2		IO6-1	IO4-1
4			/CE2								IO4-2
3	CLE1		CLE2	/WE1			IO0-1	IO2-1		Vss	IO3-2
2
		Vss	ALE2		/WP1		IO1-1		IO3-1	Vss
1
	NC		ALE1	/WE2			IO0-2	IO1-2		IO2-2	NC
	NC	NC		NC				NC		NC	NC

PACKAGE DIMENSIONS

52-ULGA (measured in millimeters)

Top View

12.00±0.10

#A1

17.00±0.10

	Bottom View
	12.00±0.10		A
	1.00 10.00
2.00		1.00

7

6

5

4

3

2

1

B

1.00

1.00

(Datum A)

1.30

A

B

C

D

(Datum B)

1.00

E

J

1.00

1.00

2.502.50

012.0

0.1017.00±

F

G

H

K

2.00

L

M

0.50

N

12- 1.00±0.05

41- 0.70±0.05

0.1 M

C

AB

0.1 M

C

AB

Side View

0.65(Max.)

17.00±0.10

0.10 C

5

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

PIN DESCRIPTION

	Pin Name								Pin Function
							DATA INPUTS/OUTPUTS
	I/O0 ~ I/O7						The I/O pins are used to input command, address and data, and to output data during read operations. The I/
							O pins float to high-z when the chip is deselected or when the outputs are disabled.
							COMMAND LATCH ENABLE
	CLE						The CLE input controls the activating path for commands sent to the command register. When active high,
							commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
							ADDRESS LATCH ENABLE
	ALE						The ALE input controls the activating path for address to the internal address registers. Addresses are
							latched on the rising edge of WE with ALE high.
							CHIP ENABLE
		CE					The CE input is the device selection control. When the device is in the Busy state,			CE	high is ignored, and
							the device does not return to standby mode.
							READ ENABLE
		RE					The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
							tREA after the falling edge of RE which also increments the internal column address counter by one.
							WRITE ENABLE
		WE					The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
							the	WE	pulse.
							WRITE PROTECT
		WP					The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
							generator is reset when the WP pin is active low.
							READY/BUSY OUTPUT
							The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
	R/B
							random read operation is in process and returns to high state upon completion. It is an open drain output and
							does not float to high-z condition when the chip is deselected or when outputs are disabled.
	Vcc						POWER
							VCC is the power supply for device.
	Vss						GROUND
	N.C						NO CONNECTION
							Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

6

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

Figure 1-1. K9F1G08X0A Functional Block Diagram
VCC
VSS
A12 - A27	X-Buffers	1024M + 32M Bit
		NAND Flash
	Latches	ARRAY
	& Decoders
A0 - A11	Y-Buffers	(2048 + 64)Byte x 65536
	Latches
	& Decoders	Data Register & S/A
		Cache Register
Command		Y-Gating
	Command
	Register	I/O Buffers & Latches		VCC
				VSS
CE	Control Logic
RE	& High Voltage		Output	I/0 0
WE	Generator	Global Buffers
			Driver
				I/0 7
	CLE ALE PRE WP
Figure 2-1. K9F1G08X0A Array Organization

64K Pages

(=1,024 Blocks)

1 Block = 64 Pages

(128K + 4k) Byte

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 1024 Blocks = 1056 Mbits

8 bit

2K Bytes

64 Bytes

									I/O 0 ~ I/O 7
		Page Register
		2K Bytes				64 Bytes

	I/O 0	I/O 1	I/O 2	I/O 3	I/O 4	I/O 5	I/O 6	I/O 7
1st Cycle	A0	A1	A2	A3	A4	A5	A6	A7
2nd Cycle	A8	A9	A10	A11	*L	*L	*L	*L
3rd Cycle	A12	A13	A14	A15	A16	A17	A18	A19
4th Cycle	A20	A21	A22	A23	A24	A25	A26	A27

NOTE : Column Address : Starting Address of the Register.

*L must be set to "Low".

*The device ignores any additional input of address cycles than required.

Column Address

Column Address

Row Address

Row Address

7

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

Product Introduction

The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 columns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially connected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08X0A.

The K9F1G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte physical space requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1G08X0A.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function	1st. Cycle	2nd. Cycle	Acceptable Command during Busy
Read	00h	30h
Read for Copy Back	00h	35h
Read ID	90h	-
Reset	FFh	-	O
Page Program	80h	10h
Cache Program*2	80h	15h
Copy-Back Program	85h	10h
Block Erase	60h	D0h
Random Data Input*1	85h	-
Random Data Output*1	05h	E0h
Read Status	70h		O

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Cache program and Copy-Back program are supported only with 3.3V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

8

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter		Symbol			Rating	Unit
			1.8V DEVICE		3.3V DEVICE
Voltage on any pin relative to VSS		VIN/OUT	-0.6 to + 2.45		-0.6 to + 4.6	V
		VCC	-0.2 to + 2.45		-0.6 to + 4.6
Temperature Under	K9F1G08X0A-XCB0	TBIAS		-10 to +125		°C
Bias	K9F1G08X0A-XIB0			-40 to +125
Storage Temperature	K9F1G08X0A-XCB0	TSTG		-65 to +150		°C
	K9F1G08X0A-XIB0
Short Circuit Current		Ios		5		mA

NOTE :

1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C)

	Parameter	Symbol	K9F1G08R0A(1.8V)			K9F1G08U0A(3.3V)			Unit
			Min	Typ.	Max	Min	Typ.	Max
	Supply Voltage	VCC	1.65	1.8	1.95	2.7	3.3	3.6	V
	Supply Voltage	VSS	0	0	0	0	0	0	V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

												K9F1G08R0A			K9F1G08U0A
	Parameter				Symbol				Test Conditions				1.8V			3.3V		Unit
												Min	Typ	Max	Min	Typ	Max
		Page Read with			ICC1			tRC=30ns(50ns with 1.8V device),
								CE=VIL				-	10	20	-	15	30
	Operating	Serial Access
								IOUT=0mA
	Current
																		mA
		Program			ICC2			-				-	10	20	-	15	30
		Erase			ICC3			-				-	10	20	-	15	30
	Stand-by Current(TTL)				ISB1							-	-	1	-	-	1
								CE=VIH, WP=0V/VCC
	Stand-by Current(CMOS)				ISB2			CE=VCC-0.2,				-	10	50	-	10	50
								WP=0V/VCC										µA
	Input Leakage Current				ILI			VIN=0 to Vcc(max)				-	-	±10	-	-	±10
	Output Leakage Current				ILO			VOUT=0 to Vcc(max)				-	-	±10	-	-	±10
	Input High Voltage				VIH*			-				0.8xVCC	-	VCC	0.8xVcc	-	VCC
														+0.3			+0.3
	Input Low Voltage, All inputs				VIL*			-				-0.3	-	0.2xVcc	-0.3	-	0.2xVcc
																		V
	Output High Voltage Level				VOH			K9F1G08R0A :IOH=-100µA				Vcc	-	-	2.4	-	-
								K9F1G08U0A :IOH=-400µA				-0.1
	Output Low Voltage Level				VOL			K9F1G08R0A :IOL=100uA				-	-	0.1	-	-	0.4
								K9F1G08U0A :IOL=2.1mA
								K9F1G08R0A :VOL=0.1V				3	4	-	8	10	-	mA
	Output Low Current(R/B)				IOL(R/B)
								K9F1G08U0A :VOL=0.4V

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

9

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

VALID BLOCK

Parameter	Symbol	Min	Typ.	Max	Unit
K9F1G08X0A	NVB	1004	-	1024	Blocks
K9K2G08U1A	NVB	2008	-	2048	Blocks

NOTE :

1.The K9F1G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2.The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

* : Each K9F1G08U0A chip in the K9K2G08U1A has Maximum 20 invalid blocks.

AC TEST CONDITION

(K9F1G08X0A-XCB0 :TA=0 to 70°C, K9F1G08X0A-XIB0:TA=-40 to 85°C

K9F1G08R0A : Vcc=1.65V~1.95V, K9F1G08U0A : Vcc=2.7V~3.6V unless otherwise noted)

Parameter	K9F1G08R0A	K9F1G08U0A
Input Pulse Levels	0V to Vcc	0V to Vcc
Input Rise and Fall Times	5ns	5ns
Input and Output Timing Levels	Vcc/2	Vcc/2
Output Load	1 TTL GATE and CL=30pF	1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Item	Symbol	Test Condition	Min	Max	Unit
Input/Output Capacitance	CI/O	VIL=0V	-	10	pF
Input Capacitance	CIN	VIN=0V	-	10	pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE	ALE	CE	WE	RE	WP		Mode
H	L	L		H	X	Read Mode	Command Input
L	H	L		H	X		Address Input(4clock)
H	L	L		H	H	Write Mode	Command Input
L	H	L		H	H		Address Input(4clock)
L	L	L		H	H	Data Input
L	L	L	H		X	Data Output
X	X	X	X	H	X	During Read(Busy)
X	X	X	X	X	H	During Program(Busy)
X	X	X	X	X	H	During Erase(Busy)
X	X*1	X	X	X	L	Write Protect
X	X	H	X	X	0V/VCC(2)	Stand-by

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

Program / Erase Characteristics

	Parameter		Symbol	Min	Typ	Max	Unit
	Program Time		tPROG*1	-	200	700	µs
	Dummy Busy Time for Cache Program		tCBSY*2		3	700	µs
	Number of Partial Program Cycles	Main Array	Nop	-	-	4	cycles
	in the Same Page	Spare Array		-	-	4	cycles
	Block Erase Time		tBERS	-	2	3	ms

NOTE : 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V ans 25’C. 2. Max. time of tCBSY depends on timing between internal program completion and data in.

10

K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

		Parameter	Symbol		Min			Max		Unit
				K9F1G08R0A		K9F1G08U0A	K9F1G08R0A		K9F1G08U0A
CLE setup Time			tCLS*1	25		15	-		-	ns
CLE Hold Time			tCLH	10		5	-		-	ns
		setup Time	tCS*1	35		20	-		-	ns
CE
		Hold Time	tCH	10		5	-		-	ns
CE
		Pulse Width	tWP	25		15	-		-	ns
WE
ALE setup Time			tALS*1	25		15	-		-	ns
ALE Hold Time			tALH	10		5	-		-	ns
Data setup Time			tDS*1	20		15	-		-	ns
Data Hold Time			tDH	10		5	-		-	ns
Write Cycle Time			tWC	45		30	-		-	ns
		High Hold Time	tWH	15		10	-		-	ns
WE
ALE to Data Loading Time			tADL*2	100*2		100*2	-		-	ns

NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.

2.tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

3.For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.

AC Characteristics for Operation

																Parameter		Symbol		Min			Max		Unit
																			K9F1G08R0A		K9F1G08U0A	K9F1G08R0A		K9F1G08U0A
	Data Transfer from Cell to Register																	tR	-		-	25		25	µs
	ALE to										Delay							tAR	10		10	-		-	ns
						RE
	CLE to										Delay							tCLR	10		10	-		-	ns
							RE
	Ready to													Low				tRR	20		20	-		-	ns
									RE
	RE Pulse Width																	tRP	25		15	-		-	ns
	WE High to Busy																	tWB	-		-	100		100	ns
	Read Cycle Time																	tRC	50		30	-		-	ns
				Access Time														tREA	-		-	30		20	ns
	RE
				Access Time														tCEA	-		-	45		35	ns
	CE
				High to Output Hi-Z														tRHZ	-		-	30		30	ns
	RE
				High to Output Hi-Z														tCHZ	-		-	20		20	ns
	CE
				or				High to Output hold										tOH	15		15	-		-	ns
	RE				CE
				High Hold Time														tREH	15		10	-		-	ns
	RE
	Output Hi-Z to																Low	tIR	0		0	-		-	ns
															RE
				High to												Low		tRHW	100		100	-		-	ns
	RE											WE
				High to												Low		tWHR	60		60	-		-	ns
	WE												RE
	Device Resetting Time																	tRST	-		-	5/10/500*1		5/10/500*1	µs
	(Read/Program/Erase)

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.

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K9F1G08R0A

K9F1G08U0A K9K2G08U1A

FLASH MEMORY

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

*	Check "FFh" at the column address
	2048 of the 1st and 2nd page in the block

	Create (or update)			No		Check "FFh
	Initial Invalid Block(s) Table
								Yes
				No
						Last Block ?
								Yes

End

Figure 3. Flow chart to create initial invalid block table.

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